[2/3] x86: Correct position of ".s" for CCMPcc in disassembler
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Commit Message
Added new macro %SW to CCMPcc to print ".s" after the mnemonic.
Before:
ccmpbl {dfv=}.s %edx,%eax
After:
ccmpbl.s {dfv=} %edx,%eax
gas/ChangeLog:
* testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc.
* testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Added %SW for CCMPcc swap operands.
* i386-dis.c (struct dis386): Added %SW.
(putop): Handle %SW.
---
gas/testsuite/gas/i386/x86-64-pseudos-apx.d | 10 ++++++++++
gas/testsuite/gas/i386/x86-64-pseudos-apx.s | 4 ++--
opcodes/i386-dis-evex.h | 4 ++--
opcodes/i386-dis.c | 10 ++++++++++
4 files changed, 24 insertions(+), 4 deletions(-)
Comments
On 04.07.2024 10:52, Cui, Lili wrote:
> --- a/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
> +++ b/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
> @@ -16,7 +16,7 @@ _start:
> {store} movaps %xmm2, (%r31)
>
> #APX EVEX promoted from legacy
> - .irp m, adc, add, and, or, sbb, sub, xor
> + .irp m, adc, add, and, or, sbb, sub, xor, cmp
Bette keep alphabetic sorting?
> @@ -36,7 +36,7 @@ _start:
> .endr
>
> #APX News.
> - .irp m, cfcmovb
> + .irp m, cfcmovb, ccmpb
And use alphabetic sorting here, too?
Okay preferably with these adjustments.
Jan
> On 04.07.2024 10:52, Cui, Lili wrote:
> > --- a/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
> > +++ b/gas/testsuite/gas/i386/x86-64-pseudos-apx.s
> > @@ -16,7 +16,7 @@ _start:
> > {store} movaps %xmm2, (%r31)
> >
> > #APX EVEX promoted from legacy
> > - .irp m, adc, add, and, or, sbb, sub, xor
> > + .irp m, adc, add, and, or, sbb, sub, xor, cmp
>
> Bette keep alphabetic sorting?
Done.
>
> > @@ -36,7 +36,7 @@ _start:
> > .endr
> >
> > #APX News.
> > - .irp m, cfcmovb
> > + .irp m, cfcmovb, ccmpb
>
> And use alphabetic sorting here, too?
>
Done.
> Okay preferably with these adjustments.
Submitted.
Thanks,
Lili.
@@ -100,6 +100,11 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 dc 7c 08 31 cf[ ]+xorl %ecx,%r31d
[ ]*[a-f0-9]+:[ ]*67 62 64 7c 08 33 39[ ]+xorl \(%ecx\),%r31d
[ ]*[a-f0-9]+:[ ]*67 62 64 7c 08 31 39[ ]+xorl %r31d,\(%ecx\)
+[ ]*[a-f0-9]+:[ ]*62 dc 04 0a 39 cf[ ]+ccmptl \{dfv=\} %ecx,%r31d
+[ ]*[a-f0-9]+:[ ]*62 64 04 0a 3b f9[ ]+ccmptl.s \{dfv=\} %ecx,%r31d
+[ ]*[a-f0-9]+:[ ]*62 dc 04 0a 39 cf[ ]+ccmptl \{dfv=\} %ecx,%r31d
+[ ]*[a-f0-9]+:[ ]*67 62 64 04 0a 3b 39[ ]+ccmptl \{dfv=\} \(%ecx\),%r31d
+[ ]*[a-f0-9]+:[ ]*67 62 64 04 0a 39 39[ ]+ccmptl \{dfv=\} %r31d,\(%ecx\)
[ ]*[a-f0-9]+:[ ]*62 dc 7c 18 01 cf[ ]+addl %ecx,%r31d,%eax
[ ]*[a-f0-9]+:[ ]*62 64 7c 18 03 f9[ ]+addl.s %ecx,%r31d,%eax
[ ]*[a-f0-9]+:[ ]*62 dc 7c 18 01 cf[ ]+addl %ecx,%r31d,%eax
@@ -154,4 +159,9 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c 42 d0[ ]+cfcmovbl.s %edx,%eax
[ ]*[a-f0-9]+:[ ]*67 62 f4 7c 08 42 02[ ]+cfcmovbl \(%edx\),%eax
[ ]*[a-f0-9]+:[ ]*67 62 f4 7c 0c 42 02[ ]+cfcmovbl %eax,\(%edx\)
+[ ]*[a-f0-9]+:[ ]*62 f4 04 02 39 d0[ ]+ccmpbl \{dfv=\} %edx,%eax
+[ ]*[a-f0-9]+:[ ]*62 f4 04 02 3b c2[ ]+ccmpbl.s \{dfv=\} %edx,%eax
+[ ]*[a-f0-9]+:[ ]*62 f4 04 02 39 d0[ ]+ccmpbl \{dfv=\} %edx,%eax
+[ ]*[a-f0-9]+:[ ]*67 62 f4 04 02 3b 02[ ]+ccmpbl \{dfv=\} \(%edx\),%eax
+[ ]*[a-f0-9]+:[ ]*67 62 f4 04 02 39 02[ ]+ccmpbl \{dfv=\} %eax,\(%edx\)
#pass
@@ -16,7 +16,7 @@ _start:
{store} movaps %xmm2, (%r31)
#APX EVEX promoted from legacy
- .irp m, adc, add, and, or, sbb, sub, xor
+ .irp m, adc, add, and, or, sbb, sub, xor, cmp
{evex} \m %ecx, %r31d
{evex} {load} \m %ecx, %r31d
{evex} {store} \m %ecx, %r31d
@@ -36,7 +36,7 @@ _start:
.endr
#APX News.
- .irp m, cfcmovb
+ .irp m, cfcmovb, ccmpb
\m %edx, %eax
{load} \m %edx, %eax
{store} \m %edx, %eax
@@ -940,8 +940,8 @@ static const struct dis386 evex_table[][256] = {
/* 38 */
{ "%NEccmp%SCB%DF", { Eb, Gb }, 0 },
{ "%NEccmp%SCS%DF", { Ev, Gv }, PREFIX_NP_OR_DATA },
- { "%NEccmp%SCB%DF", { Gb, EbS }, 0 },
- { "%NEccmp%SCS%DF", { Gv, EvS }, PREFIX_NP_OR_DATA },
+ { "%NEccmp%SCB%SW%DF", { Gb, Eb }, 0 },
+ { "%NEccmp%SCS%SW%DF", { Gv, Ev }, PREFIX_NP_OR_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1809,6 +1809,8 @@ struct dis386 {
in MAP4.
"ZU" => print 'zu' if EVEX.ZU=1.
"SC" => print suffix SCC for SCC insns
+ "SW" => print '.s' to indicate operands were swapped when suffix_always is
+ true.
"YK" keep unused, to avoid ambiguity with the combined use of Y and K.
"YX" keep unused, to avoid ambiguity with the combined use of Y and X.
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
@@ -10927,6 +10929,14 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
*ins->obufp++ = ins->vex.w ? 'd': 's';
else if (last[0] == 'B')
*ins->obufp++ = ins->vex.w ? 'w': 'b';
+ else if (last[0] == 'S')
+ {
+ if (ins->modrm.mod == 3 && (sizeflag & SUFFIX_ALWAYS))
+ {
+ *ins->obufp++ = '.';
+ *ins->obufp++ = 's';
+ }
+ }
else
abort ();
}