RISC-V: Tidy and complete testing of all architecture imply rules.
Checks
| Context |
Check |
Description |
| linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 |
success
|
Build passed
|
| linaro-tcwg-bot/tcwg_binutils_build--master-arm |
success
|
Build passed
|
| linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 |
success
|
Test passed
|
| linaro-tcwg-bot/tcwg_binutils_check--master-arm |
success
|
Test passed
|
Commit Message
gas/
* testsuite/gas/riscv/imply.s: New testcase for all imply cases.
* testsuite/gas/riscv/imply.d: Likewise.
* testsuite/gas/riscv/march-imply-i.s: Renamed to
imply-zicsr-zifencei.s.
* testsuite/gas/riscv/march-imply-i2p0-02.d: Renamed to
imply-zicsr-zifencei-i2p0-misa-spec-2p2.d.
* testsuite/gas/riscv/march-imply-i2p1-01.d/l: Renamed to
imply-zicsr-zifencei-i2p1-misa-spec-20191213.d.
* testsuite/gas/riscv/march-imply-i2p0-01.d: Removed.
Combined into new imply testcase.
* testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise.
* testsuite/gas/riscv/march-imply-a.d: Likewise.
* testsuite/gas/riscv/march-imply-b.d: Likewise.
* testsuite/gas/riscv/march-imply-f.d: Likewise.
* testsuite/gas/riscv/march-imply-g.d: Likewise.
* testsuite/gas/riscv/march-imply-h.d: Likewise.
* testsuite/gas/riscv/march-imply-q.d: Likewise.
* testsuite/gas/riscv/march-imply-smcsrind.d: Likewise.
* testsuite/gas/riscv/march-imply-smstateen.d: Likewise.
* testsuite/gas/riscv/march-imply-unsupported.d: Likewise.
* testsuite/gas/riscv/march-imply-v.d: Likewise.
* testsuite/gas/riscv/march-imply-zcd.d: Likewise.
* testsuite/gas/riscv/march-imply-zcf.d: Likewise.
---
...imply-zicsr-zifencei-i2p0-misa-spec-2p2.d} | 2 +-
...-zicsr-zifencei-i2p1-misa-spec-20191213.d} | 4 +-
...march-imply-i.s => imply-zicsr-zifencei.s} | 0
gas/testsuite/gas/riscv/imply.d | 82 +++++++++++++++++
gas/testsuite/gas/riscv/imply.s | 91 +++++++++++++++++++
gas/testsuite/gas/riscv/march-imply-a.d | 6 --
gas/testsuite/gas/riscv/march-imply-b.d | 6 --
gas/testsuite/gas/riscv/march-imply-d.d | 6 --
gas/testsuite/gas/riscv/march-imply-f.d | 6 --
gas/testsuite/gas/riscv/march-imply-g.d | 6 --
gas/testsuite/gas/riscv/march-imply-h.d | 6 --
gas/testsuite/gas/riscv/march-imply-i2p0-01.d | 7 --
gas/testsuite/gas/riscv/march-imply-i2p1-01.d | 3 -
gas/testsuite/gas/riscv/march-imply-i2p1-02.d | 7 --
gas/testsuite/gas/riscv/march-imply-q.d | 6 --
.../gas/riscv/march-imply-smcsrind.d | 6 --
.../gas/riscv/march-imply-smstateen.d | 6 --
.../gas/riscv/march-imply-unsupported.d | 6 --
gas/testsuite/gas/riscv/march-imply-v.d | 6 --
gas/testsuite/gas/riscv/march-imply-zcd.d | 6 --
gas/testsuite/gas/riscv/march-imply-zcf.d | 6 --
21 files changed, 177 insertions(+), 97 deletions(-)
rename gas/testsuite/gas/riscv/{march-imply-i2p0-02.d => imply-zicsr-zifencei-i2p0-misa-spec-2p2.d} (80%)
rename gas/testsuite/gas/riscv/{march-imply-i2p1-01.l => imply-zicsr-zifencei-i2p1-misa-spec-20191213.d} (93%)
rename gas/testsuite/gas/riscv/{march-imply-i.s => imply-zicsr-zifencei.s} (100%)
create mode 100644 gas/testsuite/gas/riscv/imply.d
create mode 100644 gas/testsuite/gas/riscv/imply.s
delete mode 100644 gas/testsuite/gas/riscv/march-imply-a.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-b.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-d.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-f.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-g.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-h.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p0-01.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-01.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-02.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-q.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-smcsrind.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-smstateen.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-unsupported.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-v.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-zcd.d
delete mode 100644 gas/testsuite/gas/riscv/march-imply-zcf.d
Comments
Committed, thanks.
Nelson
On Tue, Jul 2, 2024 at 3:55 PM Nelson Chu <nelson@rivosinc.com> wrote:
> gas/
> * testsuite/gas/riscv/imply.s: New testcase for all imply cases.
> * testsuite/gas/riscv/imply.d: Likewise.
> * testsuite/gas/riscv/march-imply-i.s: Renamed to
> imply-zicsr-zifencei.s.
> * testsuite/gas/riscv/march-imply-i2p0-02.d: Renamed to
> imply-zicsr-zifencei-i2p0-misa-spec-2p2.d.
> * testsuite/gas/riscv/march-imply-i2p1-01.d/l: Renamed to
> imply-zicsr-zifencei-i2p1-misa-spec-20191213.d.
> * testsuite/gas/riscv/march-imply-i2p0-01.d: Removed.
> Combined into new imply testcase.
> * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise.
> * testsuite/gas/riscv/march-imply-a.d: Likewise.
> * testsuite/gas/riscv/march-imply-b.d: Likewise.
> * testsuite/gas/riscv/march-imply-f.d: Likewise.
> * testsuite/gas/riscv/march-imply-g.d: Likewise.
> * testsuite/gas/riscv/march-imply-h.d: Likewise.
> * testsuite/gas/riscv/march-imply-q.d: Likewise.
> * testsuite/gas/riscv/march-imply-smcsrind.d: Likewise.
> * testsuite/gas/riscv/march-imply-smstateen.d: Likewise.
> * testsuite/gas/riscv/march-imply-unsupported.d: Likewise.
> * testsuite/gas/riscv/march-imply-v.d: Likewise.
> * testsuite/gas/riscv/march-imply-zcd.d: Likewise.
> * testsuite/gas/riscv/march-imply-zcf.d: Likewise.
> ---
> ...imply-zicsr-zifencei-i2p0-misa-spec-2p2.d} | 2 +-
> ...-zicsr-zifencei-i2p1-misa-spec-20191213.d} | 4 +-
> ...march-imply-i.s => imply-zicsr-zifencei.s} | 0
> gas/testsuite/gas/riscv/imply.d | 82 +++++++++++++++++
> gas/testsuite/gas/riscv/imply.s | 91 +++++++++++++++++++
> gas/testsuite/gas/riscv/march-imply-a.d | 6 --
> gas/testsuite/gas/riscv/march-imply-b.d | 6 --
> gas/testsuite/gas/riscv/march-imply-d.d | 6 --
> gas/testsuite/gas/riscv/march-imply-f.d | 6 --
> gas/testsuite/gas/riscv/march-imply-g.d | 6 --
> gas/testsuite/gas/riscv/march-imply-h.d | 6 --
> gas/testsuite/gas/riscv/march-imply-i2p0-01.d | 7 --
> gas/testsuite/gas/riscv/march-imply-i2p1-01.d | 3 -
> gas/testsuite/gas/riscv/march-imply-i2p1-02.d | 7 --
> gas/testsuite/gas/riscv/march-imply-q.d | 6 --
> .../gas/riscv/march-imply-smcsrind.d | 6 --
> .../gas/riscv/march-imply-smstateen.d | 6 --
> .../gas/riscv/march-imply-unsupported.d | 6 --
> gas/testsuite/gas/riscv/march-imply-v.d | 6 --
> gas/testsuite/gas/riscv/march-imply-zcd.d | 6 --
> gas/testsuite/gas/riscv/march-imply-zcf.d | 6 --
> 21 files changed, 177 insertions(+), 97 deletions(-)
> rename gas/testsuite/gas/riscv/{march-imply-i2p0-02.d =>
> imply-zicsr-zifencei-i2p0-misa-spec-2p2.d} (80%)
> rename gas/testsuite/gas/riscv/{march-imply-i2p1-01.l =>
> imply-zicsr-zifencei-i2p1-misa-spec-20191213.d} (93%)
> rename gas/testsuite/gas/riscv/{march-imply-i.s =>
> imply-zicsr-zifencei.s} (100%)
> create mode 100644 gas/testsuite/gas/riscv/imply.d
> create mode 100644 gas/testsuite/gas/riscv/imply.s
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-a.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-b.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-d.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-f.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-g.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-h.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p0-01.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-01.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-i2p1-02.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-q.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-smcsrind.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-smstateen.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-unsupported.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-v.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-zcd.d
> delete mode 100644 gas/testsuite/gas/riscv/march-imply-zcf.d
>
> diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0-02.d
> b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d
> similarity index 80%
> rename from gas/testsuite/gas/riscv/march-imply-i2p0-02.d
> rename to gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d
> index 7686296ca71..2f5ed9937d8 100644
> --- a/gas/testsuite/gas/riscv/march-imply-i2p0-02.d
> +++ b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d
> @@ -1,6 +1,6 @@
> #as: -march=rv32i -march-attr -misa-spec=2.2
> #readelf: -A
> -#source: march-imply-i.s
> +#source: imply-zicsr-zifencei.s
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_arch: "rv32i2p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-01.l
> b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d
> similarity index 93%
> rename from gas/testsuite/gas/riscv/march-imply-i2p1-01.l
> rename to
> gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d
> index 7fbee14fe83..80630f44e7d 100644
> --- a/gas/testsuite/gas/riscv/march-imply-i2p1-01.l
> +++
> b/gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d
> @@ -1,4 +1,6 @@
> -.*Assembler messages:
> +#as: -march=rv32i -march-attr -misa-spec=20191213
> +#source: imply-zicsr-zifencei.s
> +#error: .*Assembler messages:
> .*Error: unrecognized opcode `csrr t0,ustatus', extension `zicsr' required
> .*Error: unrecognized opcode `csrwi ustatus,0x0', extension `zicsr'
> required
> .*Error: unrecognized opcode `csrsi ustatus,0x0', extension `zicsr'
> required
> diff --git a/gas/testsuite/gas/riscv/march-imply-i.s
> b/gas/testsuite/gas/riscv/imply-zicsr-zifencei.s
> similarity index 100%
> rename from gas/testsuite/gas/riscv/march-imply-i.s
> rename to gas/testsuite/gas/riscv/imply-zicsr-zifencei.s
> diff --git a/gas/testsuite/gas/riscv/imply.d
> b/gas/testsuite/gas/riscv/imply.d
> new file mode 100644
> index 00000000000..dee889099f4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/imply.d
> @@ -0,0 +1,82 @@
> +#source: imply.s
> +#as: -misa-spec=20191213
> +#objdump: --syms --special-syms
> +
> +.*file format.*riscv.*
> +
> +SYMBOL TABLE:
> +[0-9a-f]+ l d .text 0+000 .text
> +[0-9a-f]+ l d .data 0+000 .data
> +[0-9a-f]+ l d .bss 0+000 .bss
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32e1p9
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p0_zicsr2p0_zifencei2p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicntr2p0_zicsr2p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zihpm2p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_zmmul1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_a2p1_zaamo1p0_zabha1p0_zalrsc1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvl64b1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcb1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_q2p2_zicsr2p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0_zqinx1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfa1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_f2p2_zicsr2p0_zfh1p0_zfhmin1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0
> +[0-9a-f]+ l .text 0+000
> \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0
> +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0
> +[0-9a-f]+ l d .riscv.attributes 0+000 .riscv.attributes
> diff --git a/gas/testsuite/gas/riscv/imply.s
> b/gas/testsuite/gas/riscv/imply.s
> new file mode 100644
> index 00000000000..f341283c968
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/imply.s
> @@ -0,0 +1,91 @@
> +.macro imply string base=i
> +.option push
> +.option arch, rv32\base\string
> +nop
> +.option pop
> +.endm
> +
> +.text
> +imply ,g
> +imply ,e
> +imply ,i
> +imply ,i2p0
> +
> +imply zicntr
> +imply zihpm
> +
> +imply m
> +
> +imply zabha
> +imply zacas
> +imply a
> +
> +imply xsfvcp
> +imply v
> +imply zvfh
> +imply zvfhmin
> +imply zvfbfwma
> +imply zvfbfmin
> +imply zve64d
> +imply zve64f
> +imply zve32f
> +imply zve64x
> +imply zve32x
> +imply zve32x_zvl65536b
> +imply zve32x_zvl32768b
> +imply zve32x_zvl16384b
> +imply zve32x_zvl8192b
> +imply zve32x_zvl4096b
> +imply zve32x_zvl2048b
> +imply zve32x_zvl1024b
> +imply zve32x_zvl512b
> +imply zve32x_zvl256b
> +imply zve32x_zvl128b
> +imply zve32x_zvl64b
> +
> +imply zcb
> +imply zcd
> +imply zcf
> +imply zcmp
> +
> +imply h
> +imply zhinx
> +imply zhinxmin
> +
> +imply q
> +imply zqinx
> +
> +imply d
> +imply zdinx
> +
> +imply zfa
> +imply zfbfmin
> +imply zfh
> +imply zfhmin
> +imply zfinx
> +imply f
> +
> +imply b
> +
> +imply zk
> +imply zkn
> +imply zks
> +imply zvbb
> +imply zvkng
> +imply zvknc
> +imply zvkn
> +imply zvksg
> +imply zvksc
> +imply zvks
> +
> +imply smaia
> +imply smcsrind
> +imply smcntrpmf
> +imply smstateen
> +imply smepmp
> +imply ssaia
> +imply sscsrind
> +imply sscofpmf
> +imply ssstateen
> +imply sstc
> +imply svadu
> diff --git a/gas/testsuite/gas/riscv/march-imply-a.d
> b/gas/testsuite/gas/riscv/march-imply-a.d
> deleted file mode 100644
> index b2cbfcf8376..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-a.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32ia -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-b.d
> b/gas/testsuite/gas/riscv/march-imply-b.d
> deleted file mode 100644
> index 82506c9a3e1..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-b.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32ib -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-d.d
> b/gas/testsuite/gas/riscv/march-imply-d.d
> deleted file mode 100644
> index ce2b47929f9..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-d.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32id -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-f.d
> b/gas/testsuite/gas/riscv/march-imply-f.d
> deleted file mode 100644
> index bc372aed0e7..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-f.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32if -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-g.d
> b/gas/testsuite/gas/riscv/march-imply-g.d
> deleted file mode 100644
> index 7e7a96785bf..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-g.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32g -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch:
> "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-h.d
> b/gas/testsuite/gas/riscv/march-imply-h.d
> deleted file mode 100644
> index 04ad9f6c0a5..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-h.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-i2p0-01.d
> b/gas/testsuite/gas/riscv/march-imply-i2p0-01.d
> deleted file mode 100644
> index 6d86034f8c7..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-i2p0-01.d
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -#as: -march=rv32i2p0 -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: march-imply-i.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p0_zicsr2p0_zifencei2p0"
> -#...
> diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-01.d
> b/gas/testsuite/gas/riscv/march-imply-i2p1-01.d
> deleted file mode 100644
> index fcf22ed3aee..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-i2p1-01.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as: -march=rv32i -march-attr -misa-spec=20191213
> -#source: march-imply-i.s
> -#error_output: march-imply-i2p1-01.l
> diff --git a/gas/testsuite/gas/riscv/march-imply-i2p1-02.d
> b/gas/testsuite/gas/riscv/march-imply-i2p1-02.d
> deleted file mode 100644
> index b8065b62520..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-i2p1-02.d
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -#as: -march=rv32i_zicsr_zifencei -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: march-imply-i.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zifencei2p0"
> -#...
> diff --git a/gas/testsuite/gas/riscv/march-imply-q.d
> b/gas/testsuite/gas/riscv/march-imply-q.d
> deleted file mode 100644
> index d631d6f3218..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-q.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv64iq -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_q2p2_zicsr2p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-smcsrind.d
> b/gas/testsuite/gas/riscv/march-imply-smcsrind.d
> deleted file mode 100644
> index e028a067a43..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-smcsrind.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32i_smcsrind -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-smstateen.d
> b/gas/testsuite/gas/riscv/march-imply-smstateen.d
> deleted file mode 100644
> index 2db14fd612b..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-smstateen.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32i_smstateen -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d
> b/gas/testsuite/gas/riscv/march-imply-unsupported.d
> deleted file mode 100644
> index 5615d590866..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-unsupported.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32g -march-attr -misa-spec=2.2
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-v.d
> b/gas/testsuite/gas/riscv/march-imply-v.d
> deleted file mode 100644
> index e07eecf16e6..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-v.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32iv -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch:
> "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-zcd.d
> b/gas/testsuite/gas/riscv/march-imply-zcd.d
> deleted file mode 100644
> index e7c75f649a8..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-zcd.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32i_zcd -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-zcf.d
> b/gas/testsuite/gas/riscv/march-imply-zcf.d
> deleted file mode 100644
> index 3829637a16f..00000000000
> --- a/gas/testsuite/gas/riscv/march-imply-zcf.d
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -#as: -march=rv32i_zcf -march-attr -misa-spec=20191213
> -#readelf: -A
> -#source: empty.s
> -Attribute Section: riscv
> -File Attributes
> - Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"
> --
> 2.39.3 (Apple Git-146)
>
>
similarity index 80%
rename from gas/testsuite/gas/riscv/march-imply-i2p0-02.d
rename to gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p0-misa-spec-2p2.d
@@ -1,6 +1,6 @@
#as: -march=rv32i -march-attr -misa-spec=2.2
#readelf: -A
-#source: march-imply-i.s
+#source: imply-zicsr-zifencei.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0"
similarity index 93%
rename from gas/testsuite/gas/riscv/march-imply-i2p1-01.l
rename to gas/testsuite/gas/riscv/imply-zicsr-zifencei-i2p1-misa-spec-20191213.d
@@ -1,4 +1,6 @@
-.*Assembler messages:
+#as: -march=rv32i -march-attr -misa-spec=20191213
+#source: imply-zicsr-zifencei.s
+#error: .*Assembler messages:
.*Error: unrecognized opcode `csrr t0,ustatus', extension `zicsr' required
.*Error: unrecognized opcode `csrwi ustatus,0x0', extension `zicsr' required
.*Error: unrecognized opcode `csrsi ustatus,0x0', extension `zicsr' required
similarity index 100%
rename from gas/testsuite/gas/riscv/march-imply-i.s
rename to gas/testsuite/gas/riscv/imply-zicsr-zifencei.s
new file mode 100644
@@ -0,0 +1,82 @@
+#source: imply.s
+#as: -misa-spec=20191213
+#objdump: --syms --special-syms
+
+.*file format.*riscv.*
+
+SYMBOL TABLE:
+[0-9a-f]+ l d .text 0+000 .text
+[0-9a-f]+ l d .data 0+000 .data
+[0-9a-f]+ l d .bss 0+000 .bss
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0
+[0-9a-f]+ l .text 0+000 \$xrv32e1p9
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1
+[0-9a-f]+ l .text 0+000 \$xrv32i2p0_zicsr2p0_zifencei2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicntr2p0_zicsr2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zihpm2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_zmmul1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zabha1p0_zalrsc1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvl64b1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcb1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_q2p2_zicsr2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0_zqinx1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfa1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfh1p0_zfhmin1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0
+[0-9a-f]+ l d .riscv.attributes 0+000 .riscv.attributes
new file mode 100644
@@ -0,0 +1,91 @@
+.macro imply string base=i
+.option push
+.option arch, rv32\base\string
+nop
+.option pop
+.endm
+
+.text
+imply ,g
+imply ,e
+imply ,i
+imply ,i2p0
+
+imply zicntr
+imply zihpm
+
+imply m
+
+imply zabha
+imply zacas
+imply a
+
+imply xsfvcp
+imply v
+imply zvfh
+imply zvfhmin
+imply zvfbfwma
+imply zvfbfmin
+imply zve64d
+imply zve64f
+imply zve32f
+imply zve64x
+imply zve32x
+imply zve32x_zvl65536b
+imply zve32x_zvl32768b
+imply zve32x_zvl16384b
+imply zve32x_zvl8192b
+imply zve32x_zvl4096b
+imply zve32x_zvl2048b
+imply zve32x_zvl1024b
+imply zve32x_zvl512b
+imply zve32x_zvl256b
+imply zve32x_zvl128b
+imply zve32x_zvl64b
+
+imply zcb
+imply zcd
+imply zcf
+imply zcmp
+
+imply h
+imply zhinx
+imply zhinxmin
+
+imply q
+imply zqinx
+
+imply d
+imply zdinx
+
+imply zfa
+imply zfbfmin
+imply zfh
+imply zfhmin
+imply zfinx
+imply f
+
+imply b
+
+imply zk
+imply zkn
+imply zks
+imply zvbb
+imply zvkng
+imply zvknc
+imply zvkn
+imply zvksg
+imply zvksc
+imply zvks
+
+imply smaia
+imply smcsrind
+imply smcntrpmf
+imply smstateen
+imply smepmp
+imply ssaia
+imply sscsrind
+imply sscofpmf
+imply ssstateen
+imply sstc
+imply svadu
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32ia -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32ib -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32id -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32if -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32g -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0"
deleted file mode 100644
@@ -1,7 +0,0 @@
-#as: -march=rv32i2p0 -march-attr -misa-spec=20191213
-#readelf: -A
-#source: march-imply-i.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p0_zicsr2p0_zifencei2p0"
-#...
deleted file mode 100644
@@ -1,3 +0,0 @@
-#as: -march=rv32i -march-attr -misa-spec=20191213
-#source: march-imply-i.s
-#error_output: march-imply-i2p1-01.l
deleted file mode 100644
@@ -1,7 +0,0 @@
-#as: -march=rv32i_zicsr_zifencei -march-attr -misa-spec=20191213
-#readelf: -A
-#source: march-imply-i.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zifencei2p0"
-#...
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv64iq -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv64i2p1_f2p2_d2p2_q2p2_zicsr2p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32i_smcsrind -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32i_smstateen -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32g -march-attr -misa-spec=2.2
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32iv -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32i_zcd -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
deleted file mode 100644
@@ -1,6 +0,0 @@
-#as: -march=rv32i_zcf -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
- Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"