[V4,7/8] gas: aarch64: add experimental support for SCFI

Message ID 20240701025404.3361349-8-indu.bhagat@oracle.com
State New
Headers
Series Add SCFI support for aarch64 |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Indu Bhagat July 1, 2024, 2:54 a.m. UTC
  [Changes in V4]
 - Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
   for DWARF register numbers.  Use offsetT where applicable.
 - Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
   common code out of switch case.
 - Add FP/Advanced SIMD registers to callee-saved registers too.
   Updated commit log to include some of the details.
 - Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
   aarch64_ginsn_ldstp () to detect 32-bit word operations.
 - Skip generating ginsns for movk, movz, movn.  These do more work than
   just simple mov; Skip generating ginsn altogether for these.
 - ginsn_dw2_regnum () is now switch case on opnd_class.  Each case
   exposed by the current set of ginsn creation logic is handled.
 - Skip Z register usage altogether for now.  Skip sve_misc iclass but
   error out if callee-saved FP/Advanced SIMD registers or stack
   management are involved.
[End of changes in V4]

[No changes in V3]

[Changes in V2]
- Factored out the ginsn creation functionality from tc-aarch64.c into
tc-aarch64-ginsn.c.
- The switch case in aarch64_ginsn_new now is based on iclass rather
than (earlier) opcode.
- Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
- Explicitly whitelist irg insn.
- Other minor code comment and readability fixes.
[End of changes in V2]

For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
GAS works on the generic GAS insns (ginsns).  This patch adds support in
the aarch64 backend to create ginsns for a subset of the supported
machine instructions.  The subset includes the minimal necessary
instructions to ensure SCFI correctness:

- Any potential register saves and unsaves.  Hence, process instructions
  belonging to a variety of iclasses involving str, ldr, stp, ldp.
- Any change of flow instructions.  This includes all conditional and
  unconditional branches, call (bl, blr, etc.) and return.
- Most importantly, any instruction that could affect the two registers
  of interest: REG_SP, REG_FP.  This set includes all pre-indexed and
  post-indexed memory operations, with writeback, on the stack.  This
  set must also include other instructions (e.g., arithmetic insns)
  where the destination register is one of the afore-mentioned registers.

With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
registers D8-D15 are included along with the relevant GPRs.  Calculating
offsets for loads and stores especially for Q registers needs special
attention here.

As an example,
   str q8, [sp, #16]
On big-endian:
   STR Qn stores as a 128-bit integer (MSB first), hence, should record
   D8 as being saved at sp+24 rather than sp+16.
On little-endian:
   should record D8 as being saved at sp+16

D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
hence, they remain "interesting" for SCFI purposes in such cases.  A CFI
save slot always represents the low 64 bits, regardless of whether a
save occurs on D, Q or Z registers.  Currently, the ginsn creation
machinery can handle D and Q registers on little-endian and big-endian.

Apart from creating ginsn, another key responsibility of the backend is
to make sure there are safeguards in place to detect and alert if an
instruction of interest may have been skipped.  This is done via
aarch64_ginsn_unhandled () (similar to the x86 backend).  This function
, hence, is also intended to alert when future ISA changes may otherwise
render SCFI results incorrect, because of missing ginsns for the newly
added machine instructions.

At this time, becuase of the complexities wrt endianness in handling Z
register usage, skip sve_misc opclass altogether for now.  The SCFI
machinery will error out (using the aarch64_ginsn_unhandled () code
path) though if Z register usage affects correctness.

The current SCFI machinery does not currently synthesize the
PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame.  The
support for this is planned for near future.

SCFI is enabled for ELF targets only.

gas/
	* config/tc-aarch64-ginsn.c: New file.
	* config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
	file.  Invoke aarch64_ginsn_new.
	* config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
	enablement.
	(TARGET_USE_SCFI): Likewise.
	(SCFI_MAX_REG_ID): New definition.
	(REG_FP): Likewise.
	(REG_LR): Likewise.
	(REG_SP): Likewise.
	(SCFI_INIT_CFA_OFFSET): Likewise.
	(SCFI_CALLEE_SAVED_REG_P): Likewise.
	(aarch64_scfi_callee_saved_p): New declaration.
---
 gas/config/tc-aarch64-ginsn.c | 797 ++++++++++++++++++++++++++++++++++
 gas/config/tc-aarch64.c       |  15 +
 gas/config/tc-aarch64.h       |  21 +
 3 files changed, 833 insertions(+)
 create mode 100644 gas/config/tc-aarch64-ginsn.c
  

Comments

Richard Sandiford July 1, 2024, 7:49 p.m. UTC | #1
Indu Bhagat <indu.bhagat@oracle.com> writes:
> [Changes in V4]
>  - Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
>    for DWARF register numbers.  Use offsetT where applicable.
>  - Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
>    common code out of switch case.
>  - Add FP/Advanced SIMD registers to callee-saved registers too.
>    Updated commit log to include some of the details.
>  - Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
>    aarch64_ginsn_ldstp () to detect 32-bit word operations.
>  - Skip generating ginsns for movk, movz, movn.  These do more work than
>    just simple mov; Skip generating ginsn altogether for these.
>  - ginsn_dw2_regnum () is now switch case on opnd_class.  Each case
>    exposed by the current set of ginsn creation logic is handled.
>  - Skip Z register usage altogether for now.  Skip sve_misc iclass but
>    error out if callee-saved FP/Advanced SIMD registers or stack
>    management are involved.
> [End of changes in V4]
>
> [No changes in V3]
>
> [Changes in V2]
> - Factored out the ginsn creation functionality from tc-aarch64.c into
> tc-aarch64-ginsn.c.
> - The switch case in aarch64_ginsn_new now is based on iclass rather
> than (earlier) opcode.
> - Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
> aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
> - Explicitly whitelist irg insn.
> - Other minor code comment and readability fixes.
> [End of changes in V2]
>
> For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
> GAS works on the generic GAS insns (ginsns).  This patch adds support in
> the aarch64 backend to create ginsns for a subset of the supported
> machine instructions.  The subset includes the minimal necessary
> instructions to ensure SCFI correctness:
>
> - Any potential register saves and unsaves.  Hence, process instructions
>   belonging to a variety of iclasses involving str, ldr, stp, ldp.
> - Any change of flow instructions.  This includes all conditional and
>   unconditional branches, call (bl, blr, etc.) and return.
> - Most importantly, any instruction that could affect the two registers
>   of interest: REG_SP, REG_FP.  This set includes all pre-indexed and
>   post-indexed memory operations, with writeback, on the stack.  This
>   set must also include other instructions (e.g., arithmetic insns)
>   where the destination register is one of the afore-mentioned registers.
>
> With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
> registers D8-D15 are included along with the relevant GPRs.  Calculating
> offsets for loads and stores especially for Q registers needs special
> attention here.
>
> As an example,
>    str q8, [sp, #16]
> On big-endian:
>    STR Qn stores as a 128-bit integer (MSB first), hence, should record
>    D8 as being saved at sp+24 rather than sp+16.
> On little-endian:
>    should record D8 as being saved at sp+16
>
> D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
> hence, they remain "interesting" for SCFI purposes in such cases.  A CFI
> save slot always represents the low 64 bits, regardless of whether a
> save occurs on D, Q or Z registers.  Currently, the ginsn creation
> machinery can handle D and Q registers on little-endian and big-endian.
>
> Apart from creating ginsn, another key responsibility of the backend is
> to make sure there are safeguards in place to detect and alert if an
> instruction of interest may have been skipped.  This is done via
> aarch64_ginsn_unhandled () (similar to the x86 backend).  This function
> , hence, is also intended to alert when future ISA changes may otherwise
> render SCFI results incorrect, because of missing ginsns for the newly
> added machine instructions.
>
> At this time, becuase of the complexities wrt endianness in handling Z
> register usage, skip sve_misc opclass altogether for now.  The SCFI
> machinery will error out (using the aarch64_ginsn_unhandled () code
> path) though if Z register usage affects correctness.
>
> The current SCFI machinery does not currently synthesize the
> PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame.  The
> support for this is planned for near future.
>
> SCFI is enabled for ELF targets only.
>
> gas/
> 	* config/tc-aarch64-ginsn.c: New file.
> 	* config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
> 	file.  Invoke aarch64_ginsn_new.
> 	* config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
> 	enablement.
> 	(TARGET_USE_SCFI): Likewise.
> 	(SCFI_MAX_REG_ID): New definition.
> 	(REG_FP): Likewise.
> 	(REG_LR): Likewise.
> 	(REG_SP): Likewise.
> 	(SCFI_INIT_CFA_OFFSET): Likewise.
> 	(SCFI_CALLEE_SAVED_REG_P): Likewise.
> 	(aarch64_scfi_callee_saved_p): New declaration.
> ---
>  gas/config/tc-aarch64-ginsn.c | 797 ++++++++++++++++++++++++++++++++++
>  gas/config/tc-aarch64.c       |  15 +
>  gas/config/tc-aarch64.h       |  21 +
>  3 files changed, 833 insertions(+)
>  create mode 100644 gas/config/tc-aarch64-ginsn.c
>
> diff --git a/gas/config/tc-aarch64-ginsn.c b/gas/config/tc-aarch64-ginsn.c
> new file mode 100644
> index 00000000000..dbee8df88b1
> --- /dev/null
> +++ b/gas/config/tc-aarch64-ginsn.c
> @@ -0,0 +1,797 @@
> +/* tc-aarch64-ginsn.c -- Ginsn generation for the AArch64 ISA
> +
> +   Copyright (C) 2024 Free Software Foundation, Inc.
> +   Contributed by ARM Ltd.

Not so :)

> +
> +   This file is part of GAS.
> +
> +   GAS is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3 of the license, or
> +   (at your option) any later version.
> +
> +   GAS is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with this program; see the file COPYING3. If not,
> +   see <http://www.gnu.org/licenses/>.  */
> +
> +/* This file contains the implementation of the ginsn creation for aarch64
> +   instructions.  Most functions will read the aarch64_instruction inst
> +   object, but none should need to modify it.  */
> +
> +#ifdef OBJ_ELF
> +
> +/* DWARF register number for R1.  Used as dummy value when WZR.  */
> +#define GINSN_DW2_REGNUM_R1_DUMMY 1
> +
> +/* Return whether the given register number is a callee-saved register for
> +   SCFI purposes.
> +
> +   Apart from the callee-saved GPRs, SCFI always tracks SP, FP and LR
> +   additionally.  As for the FP/Advanced SIMD registers, v8-v15 are
> +   callee-saved.  */
> +
> +bool
> +aarch64_scfi_callee_saved_p (unsigned int dw2reg_num)
> +{
> +  /* PS: Ensure SCFI_MAX_REG_ID is the max DWARF register number to cover
> +     all the registers here.  */
> +  if (dw2reg_num == REG_SP /* x31.  */
> +      || dw2reg_num == REG_FP /* x29.  */
> +      || dw2reg_num == REG_LR /* x30.  */
> +      || (dw2reg_num >= 19 && dw2reg_num <= 28) /* x19 - x28.  */
> +      || (dw2reg_num >= 72 && dw2reg_num <= 79) /* v8 - v15.  */)
> +    return true;
> +
> +  return false;
> +}
> +
> +/* Get the DWARF register number for the given OPND.
> +   Whether 31 is used to encode WZR or SP is specified via SP_ALLOWED_P.
> +
> +   The caller must decide the value of SP_ALLOWED_P based on the instruction
> +   encoding.  */
> +
> +static unsigned int
> +ginsn_dw2_regnum (aarch64_opnd_info *opnd, bool sp_allowed_p)

Couldn't this use operand_maybe_stack_pointer instead of taking
an sp_allowed_p parameter?

> +{
> +  enum aarch64_operand_class opnd_class;
> +  unsigned int dw2reg_num = 0;
> +
> +  opnd_class = aarch64_get_operand_class (opnd->type);
> +
> +  switch (opnd_class)
> +    {
> +    case AARCH64_OPND_CLASS_FP_REG:
> +      dw2reg_num = opnd->reg.regno + 64;
> +      break;
> +    case AARCH64_OPND_CLASS_SVE_REGLIST:
> +      dw2reg_num = opnd->reglist.first_regno + 64;
> +      break;
> +    case AARCH64_OPND_CLASS_MODIFIED_REG:
> +    case AARCH64_OPND_CLASS_INT_REG:
> +    case AARCH64_OPND_CLASS_ADDRESS:
> +      /* Use a dummy register value in case of WZR, else this will be an
> +	 incorrect dependency on REG_SP.  */
> +      if (!sp_allowed_p && opnd->reg.regno == REG_SP)
> +	dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
> +      else
> +	/* For GPRs of our interest (callee-saved regs, SP, FP, LR),
> +	   DWARF register number is the same as AArch64 register number.  */
> +	dw2reg_num = opnd->reg.regno;
> +      break;

I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
instead.  AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.

> +    case AARCH64_OPND_CLASS_SYSTEM:
> +      /* For prfm etc., where a opnd->type AARCH64_OPND_PRFOP is seen.  */
> +      dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
> +      break;

Hopefully this goes away if we treat PRFM as "other".

> +    default:
> +      as_bad ("Unexpected value in ginsn_dw2_regnum");
> +      break;
> +    }
> +
> +  return dw2reg_num;
> +}
> +
> +/* Generate ginsn for addsub instructions with immediate opnd.  */
> +
> +static ginsnS *
> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn = NULL;
> +  bool add_p, sub_p;
> +  offsetT src_imm = 0;
> +  unsigned int dst_reg, opnd_reg;
> +  aarch64_opnd_info *dst, *opnd;
> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
> +			 enum ginsn_src_type, unsigned int, offsetT,
> +			 enum ginsn_src_type, unsigned int, offsetT,
> +			 enum ginsn_dst_type, unsigned int, offsetT);
> +
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
> +  gas_assert (add_p || sub_p);
> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
> +
> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
> +  dst = &base->operands[0];
> +  opnd = &base->operands[1];
> +
> +  dst_reg = ginsn_dw2_regnum (dst, true);
> +
> +  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
> +    src_imm = inst.reloc.exp.X_add_number;
> +  /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
> +     and handle via aarch64_ginsn_unhandled () code path.  */
> +  else if (inst.reloc.type != BFD_RELOC_UNUSED)
> +    return ginsn;
> +  /* FIXME - verify the understanding and remove assert.  */
> +  else
> +    gas_assert (0);
> +
> +  opnd_reg = ginsn_dw2_regnum (opnd, true);
> +
> +  ginsn = ginsn_func (insn_end_sym, true,
> +		      GINSN_SRC_REG, opnd_reg, 0,
> +		      GINSN_SRC_IMM, 0, src_imm,
> +		      GINSN_DST_REG, dst_reg, 0);
> +  ginsn_set_where (ginsn);
> +
> +  return ginsn;
> +}
> +
> +/* Generate ginsn for addsub instructions with reg opnd.  */
> +
> +static ginsnS *
> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn = NULL;
> +  bool add_p, sub_p;
> +  unsigned int dst_reg, src1_reg, src2_reg;
> +  aarch64_opnd_info *dst, *src1, *src2;
> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
> +			 enum ginsn_src_type, unsigned int, offsetT,
> +			 enum ginsn_src_type, unsigned int, offsetT,
> +			 enum ginsn_dst_type, unsigned int, offsetT);
> +
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
> +  gas_assert (add_p || sub_p);
> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
> +
> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
> +  dst = &base->operands[0];
> +  src1 = &base->operands[1];
> +  src2 = &base->operands[2];
> +
> +  dst_reg = ginsn_dw2_regnum (dst, true);
> +  src1_reg = ginsn_dw2_regnum (src1, true);
> +  src2_reg = ginsn_dw2_regnum (src2, false);
> +
> +  ginsn = ginsn_func (insn_end_sym, true,
> +		      GINSN_SRC_REG, src1_reg, 0,
> +		      GINSN_SRC_REG, src2_reg, 0,
> +		      GINSN_DST_REG, dst_reg, 0);
> +  ginsn_set_where (ginsn);

It looks like this ignores any shift that is applied to src2_reg.

> +
> +  return ginsn;
> +}
> +
> +/* Generate ginsn for the load pair and store pair instructions.  */
> +
> +static ginsnS *
> +aarch64_ginsn_ldstp (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn = NULL;
> +  ginsnS *ginsn_ind = NULL;
> +  ginsnS *ginsn_mem1 = NULL;
> +  ginsnS *ginsn_mem2 = NULL;
> +  unsigned int opnd_reg, addr_reg;
> +  offsetT offset, mem_offset;
> +  unsigned int width = 8;
> +  bool store_p = false;
> +
> +  aarch64_opnd_info *opnd1, *opnd2, *addr;
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  /* This function is for handling ldp / stp ops only.  */
> +  gas_assert (opcode->iclass == ldstpair_indexed
> +	      || opcode->iclass == ldstpair_off);
> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
> +
> +  opnd1 = &base->operands[0];
> +  opnd2 = &base->operands[1];
> +  addr = &base->operands[2];
> +  store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
> +
> +  addr_reg = ginsn_dw2_regnum (addr, true);
> +  gas_assert (!addr->addr.offset.is_reg);
> +  mem_offset = addr->addr.offset.imm;
> +
> +  /* ldstp may load or store two 32-bit words or two 64-bit doublewords.  */
> +  if (opnd1->qualifier == AARCH64_OPND_QLF_W
> +      || opnd1->qualifier == AARCH64_OPND_QLF_S_S)
> +    width = 4;
> +
> +  /* Handle address calculation.  */
> +  if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
> +    {
> +      /* Pre-indexed store, e.g., stp x29, x30, [sp, -128]!
> +	 Pre-indexed addressing is like offset addressing, except that
> +	 the base pointer is updated as a result of the instruction.
> +
> +	 Post-indexed store, e.g., stp     x29, x30, [sp],128
> +	 Post-index addressing is useful for popping off the stack.  The
> +	 instruction loads the value from the location pointed at by the stack
> +	 pointer, and then moves the stack pointer on to the next full location
> +	 in the stack.  */
> +      ginsn_ind = ginsn_new_add (insn_end_sym, false,
> +				 GINSN_SRC_REG, addr_reg, 0,
> +				 GINSN_SRC_IMM, 0, mem_offset,
> +				 GINSN_DST_REG, addr_reg, 0);
> +      ginsn_set_where (ginsn_ind);
> +    }
> +
> +  /* Save / restore of WZR is not of interest for SCFI.  However, the address
> +     processing component may have updated the stack pointer.  At least, emit
> +     that ginsn and return.  PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
> +     now;  Check explicitly the regno for WZR.  Also note,
> +     TBD_GINSN_GEN_NOT_SCFI.  */
> +  if (opnd1->reg.regno == REG_SP /* WZR.  */)
> +    return ginsn_ind;
> +
> +  /* With post-index addressing, the value is loaded from the
> +     address in the base pointer, and then the pointer is updated.
> +     With pre-index addressing, the addr computation has already
> +     been explicitly done.  */
> +  offset = mem_offset;
> +  if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
> +    offset = 0;

I guess this is personal taste, but IMO it would be easier to follow if
this were combined with the "if" above, so that the compensating action
of ginsn_ind is next to the creation of ginsn_ind itself.

> +
> +  if (opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
> +    {
> +      width = 16;
> +      if (target_big_endian)
> +	offset += 8;
> +    }
> +
> +  opnd_reg = ginsn_dw2_regnum (opnd1, false);
> +  if (store_p)
> +    {
> +      ginsn_mem1 = ginsn_new_store (insn_end_sym, false,
> +				    GINSN_SRC_REG, opnd_reg,
> +				    GINSN_DST_INDIRECT, addr_reg, offset);
> +      ginsn_set_where (ginsn_mem1);
> +
> +      opnd_reg = ginsn_dw2_regnum (opnd2, false);
> +      ginsn_mem2 = ginsn_new_store (insn_end_sym, false,
> +				    GINSN_SRC_REG, opnd_reg,
> +				    GINSN_DST_INDIRECT, addr_reg,
> +				    offset + width);
> +      ginsn_set_where (ginsn_mem2);
> +    }
> +  else
> +    {
> +      opnd_reg = ginsn_dw2_regnum (opnd1, false);
> +      ginsn_mem1 = ginsn_new_load (insn_end_sym, false,
> +				   GINSN_SRC_INDIRECT, addr_reg, offset,
> +				   GINSN_DST_REG, opnd_reg);
> +      ginsn_set_where (ginsn_mem1);
> +
> +      opnd_reg = ginsn_dw2_regnum (opnd2, false);
> +      ginsn_mem2 = ginsn_new_load (insn_end_sym, false,
> +				   GINSN_SRC_INDIRECT, addr_reg, offset + width,
> +				   GINSN_DST_REG, opnd_reg);
> +      ginsn_set_where (ginsn_mem2);
> +    }
> +
> +  /* Link the list of ginsns created.  */
> +  if (addr->addr.preind && addr->addr.writeback)
> +    gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem1));
> +
> +  gas_assert (!ginsn_link_next (ginsn_mem1, ginsn_mem2));
> +
> +  if (addr->addr.postind && addr->addr.writeback)
> +    gas_assert (!ginsn_link_next (ginsn_mem2, ginsn_ind));
> +
> +  /* Make note of the first instruction in the list.  */
> +  ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem1;
> +  return ginsn;
> +}
> +
> +/* Generate ginsn for load and store instructions.  */
> +
> +static ginsnS *
> +aarch64_ginsn_ldstr (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn = NULL;
> +  ginsnS *ginsn_ind = NULL;
> +  ginsnS *ginsn_mem = NULL;
> +  unsigned int opnd_reg, addr_reg;
> +  offsetT offset, mem_offset;
> +  bool store_p = false;
> +
> +  aarch64_opnd_info *opnd1, *addr;
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  /* This function is for handling ldr, str ops only.  */
> +  gas_assert (opcode->iclass == ldst_imm9 || opcode->iclass == ldst_pos);
> +  gas_assert (aarch64_num_of_operands (opcode) == 2);
> +
> +  opnd1 = &base->operands[0];
> +  addr = &base->operands[1];
> +  store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
> +
> +  addr_reg = ginsn_dw2_regnum (addr, true);
> +
> +  /* STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}].
> +     LDR <Xt>, [<Xn|SP>], #<simm>.  */
> +  opnd_reg = ginsn_dw2_regnum (opnd1, false);
> +
> +  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
> +    mem_offset = inst.reloc.exp.X_add_number;
> +  else
> +    {
> +      gas_assert (!addr->addr.offset.is_reg);
> +      mem_offset = addr->addr.offset.imm;
> +    }
> +
> +  /* Handle address calculation.  */
> +  if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
> +    {
> +      ginsn_ind = ginsn_new_add (insn_end_sym, false,
> +				 GINSN_SRC_REG, addr_reg, 0,
> +				 GINSN_SRC_IMM, 0, mem_offset,
> +				 GINSN_DST_REG, addr_reg, 0);
> +      ginsn_set_where (ginsn_ind);
> +    }
> +
> +  /* Save / restore of WZR is not of interest for SCFI.  However, the address
> +     processing component may have updated the stack pointer.  At least, emit
> +     that ginsn and return.  PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
> +     now;  Check explicitly the regno for WZR.  Also note,
> +     TBD_GINSN_GEN_NOT_SCFI.  */
> +  if (opnd1->reg.regno == REG_SP /* WZR.  */)
> +    return ginsn_ind;
> +
> +  /* With post-index addressing, the value is loaded from the
> +     address in the base pointer, and then the pointer is updated.
> +     With pre-index addressing, the addr computation has already
> +     been explicitly done.  */
> +  offset = mem_offset;
> +  if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
> +    offset = 0;

Same comment as above.

> +  if (target_big_endian && opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
> +    offset += 8;
> +
> +  if (store_p)
> +    ginsn_mem = ginsn_new_store (insn_end_sym, false,
> +				 GINSN_SRC_REG, opnd_reg,
> +				 GINSN_DST_INDIRECT, addr_reg, offset);
> +  else
> +    ginsn_mem = ginsn_new_load (insn_end_sym, false,
> +				GINSN_SRC_INDIRECT, addr_reg, offset,
> +				GINSN_DST_REG, opnd_reg);
> +  ginsn_set_where (ginsn_mem);
> +
> +  if (addr->addr.preind && addr->addr.writeback)
> +    gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem));
> +  else if (addr->addr.postind && addr->addr.writeback)
> +    gas_assert (!ginsn_link_next (ginsn_mem, ginsn_ind));
> +
> +  /* Make note of the first instruction in the list.  */
> +  ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem;
> +
> +  return ginsn;
> +}
> +
> +/* Generate ginsn for unconditional branch instructions.  */
> +
> +static ginsnS *
> +aarch64_ginsn_branch_uncond (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn = NULL;
> +  const symbolS *src_symbol = NULL;
> +  enum ginsn_src_type src_type = GINSN_SRC_UNKNOWN;
> +  unsigned int src_reg = 0;
> +
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  if (opcode->iclass == branch_imm)
> +    {
> +      /* b or bl.  opcode 0x14000000 or 0x94000000.  */
> +      gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_CALL26
> +		  || inst.reloc.type == BFD_RELOC_AARCH64_JUMP26);

It's possible to specify an immediate operand too:

	b	4

> +      src_symbol = inst.reloc.exp.X_add_symbol;
> +      src_type = GINSN_SRC_SYMBOL;
> +    }
> +  else if (aarch64_num_of_operands (opcode) >= 1)
> +    {
> +      gas_assert (opcode->iclass == branch_reg);
> +      /* Some insns (e.g., braa, blraa etc.) may have > 1 operands.  For
> +	 current SCFI implementation, it suffices however to simply pass
> +	 the information about the first source.  Although, strictly speaking,
> +	 (if reg) the source info is currently of no material use either.  */
> +      src_type = GINSN_SRC_REG;
> +      src_reg = ginsn_dw2_regnum (&base->operands[0], false);
> +    }
> +
> +  if (aarch64_opcode_subclass_p (opcode, F_BRANCH_CALL))
> +    {
> +      gas_assert (src_type != GINSN_SRC_UNKNOWN);
> +      ginsn = ginsn_new_call (insn_end_sym, true,
> +			      src_type, src_reg, src_symbol);
> +    }
> +  else if (aarch64_opcode_subclass_p (opcode, F_BRANCH_RET))
> +    /* TBD_GINSN_REPRESENTATION_LIMIT.  The following function to create a
> +       GINSN_TYPE_RETURN does not allow src info ATM.  */
> +    ginsn = ginsn_new_return (insn_end_sym, true);
> +  else
> +    ginsn = ginsn_new_jump (insn_end_sym, true,
> +			    src_type, src_reg, src_symbol);
> +
> +  ginsn_set_where (ginsn);
> +
> +  return ginsn;
> +}
> +
> +/* Generate ginsn for conditional branch instructions.  */
> +
> +static ginsnS *
> +aarch64_ginsn_branch_cond (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn;
> +  const symbolS *src_symbol;
> +  enum ginsn_src_type src_type;
> +
> +  gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_BRANCH19
> +	      || inst.reloc.type == BFD_RELOC_AARCH64_TSTBR14);

Similarly here, it's possible to write:

	cbz	x0, 4

> +
> +  src_symbol = inst.reloc.exp.X_add_symbol;
> +  src_type = GINSN_SRC_SYMBOL;
> +  ginsn = ginsn_new_jump_cond (insn_end_sym, true, src_type, 0, src_symbol);
> +  ginsn_set_where (ginsn);
> +
> +  return ginsn;
> +}
> +
> +/* Generate ginsn for mov instructions.  */
> +
> +static ginsnS *
> +aarch64_ginsn_mov (const symbolS *insn_end_sym)
> +{
> +  ginsnS *ginsn = NULL;
> +  unsigned int src_reg = 0, dst_reg;
> +  aarch64_opnd_info *src, *dst;
> +  offsetT src_imm = 0;
> +  enum ginsn_src_type src_type;
> +
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  gas_assert (aarch64_num_of_operands (opcode) == 2);
> +
> +  dst = &base->operands[0];
> +  src = &base->operands[1];
> +
> +  dst_reg = ginsn_dw2_regnum (dst, true);
> +
> +  /* For some mov ops, e.g., movn, movk, or movz, there may optionally be more
> +     work than just a simple mov.  Skip handling these mov altogether and let
> +     the aarch64_ginsn_unhandled () alert if these insns affect SCFI
> +     correctness.  TBD_GINSN_GEN_NOT_SCFI.  */
> +  if (src->type == AARCH64_OPND_HALF)
> +    return ginsn;
> +
> +  if (src->type == AARCH64_OPND_IMM_MOV
> +      && aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
> +    {
> +      src_imm = inst.reloc.exp.X_add_number;
> +      src_type = GINSN_SRC_IMM;
> +    }
> +  else
> +    {
> +      /* mov   x27, sp.  */
> +      src_reg = ginsn_dw2_regnum (src, true);
> +      src_type = GINSN_SRC_REG;
> +    }

The condition makes it seem like we could enter the "else" for
src->type == AARCH64_OPND_IMM_MOV, although the code only accepts
registers.

It might be better to put the immediate and register cases in
separate functions, as for add/sub.  It's probably safer to punt
for the immediate else case, since it is possible in principle
to have a relocated MOV.

> +
> +  ginsn = ginsn_new_mov (insn_end_sym, false,
> +			 src_type, src_reg, src_imm,
> +			 GINSN_DST_REG, dst_reg, 0);
> +  ginsn_set_where (ginsn);
> +
> +  return ginsn;
> +}
> +
> +/* Check if an instruction is whitelisted.
> +
> +   An instruction is a candidate for whitelisting if not generating ginsn for
> +   it, does not affect SCFI correctness.
> +
> +   TBD_GINSN_GEN_NOT_SCFI.  This function assumes GINSN_GEN_SCFI is in effect.
> +   When other ginsn_gen_mode are added, this will need fixing.  */
> +
> +static bool
> +aarch64_ginsn_safe_to_skip_p (void)
> +{
> +  bool skip_p = false;
> +  aarch64_opnd_info *opnd = NULL;
> +  unsigned int dw2_regnum;
> +  unsigned int opnd_reg;
> +  int num_opnds = 0;
> +
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  /* ATM, whitelisting operations with no operands does not seem to be
> +     necessary.  */
> +  num_opnds = aarch64_num_of_operands (opcode);
> +  if (!num_opnds)
> +    return skip_p;

Things like ERET show that this would be dangerous, so it might be better
to make the false return explicit (and adjust the comment).

> +
> +  opnd = &base->operands[0];
> +
> +  switch (opcode->iclass)
> +    {
> +    case ldst_regoff:
> +      /* It is not expected to have reg offset based ld/st ops to be used
> +	 for reg save and restore operations.  Warn the user though.  */
> +      opnd_reg = ginsn_dw2_regnum (opnd, false);
> +      if (aarch64_scfi_callee_saved_p (opnd_reg))
> +	{
> +	  skip_p = true;
> +	  as_warn ("SCFI: ignored probable save/restore op with reg offset");
> +	}
> +      break;
> +
> +    case dp_2src:
> +      /* irg insn needs to be explicitly whitelisted.  This is because the
> +	 dest is Rd_SP, but irg insn affects the tag only.  To detect irg
> +	 insn, avoid an opcode-based check, however.  */

I think we should check specifically for IRG (via subclasses).
Admittedly none of the others do anything sensible for SP, but other
instructions could be added in future.

> +      if (opnd->type == AARCH64_OPND_Rd_SP)
> +	{
> +	  dw2_regnum = ginsn_dw2_regnum (opnd, true);
> +	  if (dw2_regnum == REG_SP)
> +	    skip_p = true;
> +	}
> +      break;
> +
> +    default:
> +      break;
> +    }
> +
> +  return skip_p;
> +}
> +
> +#define AARCH64_GINSN_UNHANDLED_NONE        0
> +#define AARCH64_GINSN_UNHANDLED_DEST_REG    1
> +#define AARCH64_GINSN_UNHANDLED_CFG         2
> +#define AARCH64_GINSN_UNHANDLED_STACKOP     3
> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED  4
> +
> +/* Check the input insn for its impact on the correctness of the synthesized
> +   CFI.  Returns an error code to the caller.  */
> +
> +static int
> +aarch64_ginsn_unhandled (void)
> +{
> +  int err = AARCH64_GINSN_UNHANDLED_NONE;
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +  aarch64_opnd_info *dest = &base->operands[0];
> +  int num_opnds = aarch64_num_of_operands (opcode);
> +  aarch64_opnd_info *addr;
> +  unsigned int dw2_regnum;
> +  unsigned int addr_reg;
> +  aarch64_opnd_info *opnd = NULL;
> +  unsigned int opnd_reg;
> +  bool sp_allowed_p = false;
> +
> +  /* All change of flow instructions are important for SCFI.  */
> +  if (opcode->iclass == condbranch
> +      || opcode->iclass == compbranch
> +      || opcode->iclass == testbranch
> +      || opcode->iclass == branch_imm
> +      || opcode->iclass == branch_reg)
> +    err = AARCH64_GINSN_UNHANDLED_CFG;
> +  /* Also, any memory instructions that may involve an update to the stack
> +     pointer or save/restore of callee-saved registers must not be skipped.
> +     Note that, some iclasses cannot be used to push or pop stack because of
> +     disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
> +     loadlit, ldstnapair_offs.  FIXME double-check.
> +     Also, these iclasses do not seem to be amenable to being used for
> +     save/restore ops either.  FIXME double-check.  */
> +  else if (opcode->iclass == ldstpair_off
> +	   || opcode->iclass == ldstpair_indexed
> +	   || opcode->iclass == ldst_imm9
> +	   || opcode->iclass == ldst_imm10
> +	   || opcode->iclass == ldst_pos
> +  /* STR Zn are especially complicated as they do not store in the same byte
> +     order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
> +     whereas STR Zn stores as a stream of bytes (LSB first).  FIXME Simply punt
> +     on the big-endian and little-endian SVE PCS case for now.  */
> +	   || opcode->iclass == sve_misc)
> +    {
> +      opnd = &base->operands[0];
> +      addr = &base->operands[num_opnds - 1];
> +      addr_reg = ginsn_dw2_regnum (addr, true);
> +      opnd_reg = ginsn_dw2_regnum (opnd, false);
> +      /* For all skipped memory operations, check if an update to REG_SP or
> +	 REG_FP is involved.  */
> +      if ((addr_reg == REG_SP || addr_reg == REG_FP)
> +	  && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
> +	      || aarch64_scfi_callee_saved_p (opnd_reg)))
> +
> +	err = AARCH64_GINSN_UNHANDLED_STACKOP;

The way I'd imagined this working is that we'd use two-directional data
flow to record which callee-saved registers are "protected" at which
instructions.  That is, for saves we'd walk the cfg forward from the
entry point, recording which registers have been saved earlier in the walk
(and being conservatively correct for cycles).  And for restores we'd
walk the cfg backwards from the exit points, recording which registers
are restored later in the walk.  If a register is both "saved ealier" and
"restored later" for a given instruction, it wouldn't matter what the
instruction does with that register.

(For infinite loops we would pretend that all registers are restored later.)

It seems like instead, we'd generate a warning for:

        ...
        str     d8, [sp, #...]
        ...
        ld1d    z8.b, p0/z, [sp, #...]
        ...
        ldr     d8, [sp, #...]
        ...
        ret

even though that should be ok (even without interpreting SVE instructions).

On the other hand, any read or write of a callee-saved register is suspicious
if it isn't saved earlier or isn't restored later.

In other words, it seems like this information should be context-dependent,
or used in a context-dependent way.  Whether a particular register matters
depends on whether the register might still contain the caller's data.

Thanks,
Richard

> +    }
> +  /* Finally, irrespective of the iclass, check if the missed instructions are
> +     affecting REG_SP or REG_FP.  */
> +  else if (dest && (dest->type == AARCH64_OPND_Rd
> +		    || dest->type == AARCH64_OPND_Rd_SP))
> +    {
> +      sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
> +      dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
> +
> +      if (dw2_regnum == REG_SP || dw2_regnum == REG_FP)
> +	err = AARCH64_GINSN_UNHANDLED_DEST_REG;
> +    }
> +
> +  return err;
> +}
> +
> +/* Generate one or more generic GAS instructions, a.k.a, ginsns for the
> +   current machine instruction.
> +
> +   Returns the head of linked list of ginsn(s) added, if success; Returns NULL
> +   if failure.
> +
> +   The input ginsn_gen_mode GMODE determines the set of minimal necessary
> +   ginsns necessary for correctness of any passes applicable for that mode.
> +   For supporting the GINSN_GEN_SCFI generation mode, following is the list of
> +   machine instructions that must be translated into the corresponding ginsns
> +   to ensure correctness of SCFI:
> +     - All instructions affecting the two registers that could potentially
> +       be used as the base register for CFA tracking.  For SCFI, the base
> +       register for CFA tracking is limited to REG_SP and REG_FP only.
> +     - All change of flow instructions: conditional and unconditional
> +       branches, call and return from functions.
> +     - All instructions that can potentially be a register save / restore
> +       operations.
> +     - All instructions that may update the stack pointer: pre-indexed and
> +     post-indexed stack operations with writeback.
> +
> +   The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
> +   To support other generation modes will require work on this target-specific
> +   process of creation of ginsns:
> +     - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
> +       possible starting points.
> +     - Also note that ginsn representation may need enhancements.  Specifically,
> +       note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
> +   */
> +
> +static ginsnS *
> +aarch64_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode)
> +{
> +  int err = 0;
> +  ginsnS *ginsn = NULL;
> +  unsigned int dw2_regnum;
> +  aarch64_opnd_info *dest = NULL;
> +  bool sp_allowed_p = false;
> +  aarch64_inst *base = &inst.base;
> +  const aarch64_opcode *opcode = base->opcode;
> +
> +  /* Currently supports generation of selected ginsns, sufficient for
> +     the use-case of SCFI only.  To remove this condition will require
> +     work on this target-specific process of creation of ginsns.  Some
> +     of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
> +     examples.  */
> +  if (gmode != GINSN_GEN_SCFI)
> +    return ginsn;
> +
> +  switch (opcode->iclass)
> +    {
> +    case addsub_ext:
> +      /* TBD_GINSN_GEN_NOT_SCFI: other insns are not of interest for SCFI.  */
> +      if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
> +	   || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
> +	ginsn = aarch64_ginsn_addsub_reg (insn_end_sym);
> +      break;
> +
> +    case addsub_imm:
> +      if (aarch64_opcode_subclass_p (opcode, F_ARITH_MOV))
> +	ginsn = aarch64_ginsn_mov (insn_end_sym);
> +      else if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
> +	       || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
> +	ginsn = aarch64_ginsn_addsub_imm (insn_end_sym);
> +      break;
> +
> +    case movewide:
> +      ginsn = aarch64_ginsn_mov (insn_end_sym);
> +      break;
> +
> +    case ldst_imm9:
> +    case ldst_pos:
> +      ginsn = aarch64_ginsn_ldstr (insn_end_sym);
> +      break;
> +
> +    case ldstpair_indexed:
> +    case ldstpair_off:
> +      ginsn = aarch64_ginsn_ldstp (insn_end_sym);
> +      break;
> +
> +    case branch_imm:
> +    case branch_reg:
> +      ginsn = aarch64_ginsn_branch_uncond (insn_end_sym);
> +      break;
> +
> +    case compbranch:
> +      /* Although cbz/cbnz has an additional operand and are functionally
> +	 distinct from conditional branches, it is fine to use the same ginsn
> +	 type for both from the perspective of SCFI.  */
> +    case testbranch:
> +    case condbranch:
> +      ginsn = aarch64_ginsn_branch_cond (insn_end_sym);
> +      break;
> +
> +    default:
> +      /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
> +	 GINSN_GEN_SCFI mode.  */
> +      break;
> +    }
> +
> +  if (!ginsn && !aarch64_ginsn_safe_to_skip_p ())
> +    {
> +      /* For all unhandled insns, check that they no not impact SCFI
> +	 correctness.  */
> +      err = aarch64_ginsn_unhandled ();
> +      switch (err)
> +	{
> +	case AARCH64_GINSN_UNHANDLED_NONE:
> +	  break;
> +	case AARCH64_GINSN_UNHANDLED_DEST_REG:
> +	  /* Not all writes to REG_FP are harmful in context of SCFI.  Simply
> +	     generate a GINSN_TYPE_OTHER with destination set to the
> +	     appropriate register.  The SCFI machinery will bail out if this
> +	     ginsn affects SCFI correctness.  */
> +	  dest = &base->operands[0];
> +	  sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
> +	  dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
> +	  ginsn = ginsn_new_other (insn_end_sym, true,
> +				   GINSN_SRC_IMM, 0,
> +				   GINSN_SRC_IMM, 0,
> +				   GINSN_DST_REG, dw2_regnum);
> +	  ginsn_set_where (ginsn);
> +	  break;
> +	case AARCH64_GINSN_UNHANDLED_CFG:
> +	case AARCH64_GINSN_UNHANDLED_STACKOP:
> +	  as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"),
> +		  opcode->opcode);
> +	  break;
> +	case AARCH64_GINSN_UNHANDLED_UNEXPECTED:
> +	  as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
> +		  opcode->opcode);
> +	  break;
> +	default:
> +	  abort ();
> +	  break;
> +	}
> +    }
> +
> +  return ginsn;
> +}
> +
> +#endif /* OBJ_ELF.  */
> +
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 5d15ee9fc02..4f4dd404551 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -33,6 +33,7 @@
>  #include "dw2gencfi.h"
>  #include "sframe.h"
>  #include "gen-sframe.h"
> +#include "scfi.h"
>  #endif
>  
>  #include "dw2gencfi.h"
> @@ -8591,6 +8592,10 @@ dump_opcode_operands (const aarch64_opcode *opcode)
>  }
>  #endif /* DEBUG_AARCH64 */
>  
> +#ifdef OBJ_ELF
> +# include "tc-aarch64-ginsn.c"
> +#endif
> +
>  /* This is the guts of the machine-dependent assembler.  STR points to a
>     machine dependent instruction.  This function is supposed to emit
>     the frags/bytes it assembles to.  */
> @@ -8728,6 +8733,16 @@ md_assemble (char *str)
>  	      output_inst (copy);
>  	    }
>  
> +#ifdef OBJ_ELF
> +	  if (flag_synth_cfi)
> +	    {
> +	      ginsnS *ginsn;
> +	      ginsn = aarch64_ginsn_new (symbol_temp_new_now (),
> +					 frch_ginsn_gen_mode ());
> +	      frch_ginsn_data_append (ginsn);
> +	    }
> +#endif
> +
>  	  /* Issue non-fatal messages if any.  */
>  	  output_operand_error_report (str, true);
>  	  return;
> diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
> index 1b8badad9fd..4906a6e7000 100644
> --- a/gas/config/tc-aarch64.h
> +++ b/gas/config/tc-aarch64.h
> @@ -263,6 +263,27 @@ extern void aarch64_after_parse_args (void);
>  
>  #ifdef OBJ_ELF
>  
> +#define TARGET_USE_GINSN 1
> +/* Allow GAS to synthesize DWARF CFI for hand-written asm.
> +   PS: TARGET_USE_CFIPOP is a pre-condition.  */
> +#define TARGET_USE_SCFI 1
> +/* Identify the maximum DWARF register number of all the registers being
> +   tracked for SCFI.  This is the last DWARF register number of the set
> +   of SP, FP, and all callee-saved registers.  For Aarch64, this means 79
> +   because FP/Advanced SIMD v8-v15 are also callee-saved registers.  */
> +# define SCFI_MAX_REG_ID 79
> +/* Identify the DWARF register number of the frame-pointer register.  */
> +# define REG_FP 29
> +/* Identify the DWARF register number of the link register.  */
> +# define REG_LR 30
> +/* Identify the DWARF register number of the stack-pointer register.  */
> +# define REG_SP 31
> +
> +#define SCFI_INIT_CFA_OFFSET 0
> +
> +#define SCFI_CALLEE_SAVED_REG_P(dw2reg)  aarch64_scfi_callee_saved_p (dw2reg)
> +extern bool aarch64_scfi_callee_saved_p (uint32_t dw2reg_num);
> +
>  /* Whether SFrame stack trace info is supported.  */
>  extern bool aarch64_support_sframe_p (void);
>  #define support_sframe_p aarch64_support_sframe_p
  
Indu Bhagat July 11, 2024, 6:30 a.m. UTC | #2
On 7/1/24 12:49, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> [Changes in V4]
>>   - Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
>>     for DWARF register numbers.  Use offsetT where applicable.
>>   - Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
>>     common code out of switch case.
>>   - Add FP/Advanced SIMD registers to callee-saved registers too.
>>     Updated commit log to include some of the details.
>>   - Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
>>     aarch64_ginsn_ldstp () to detect 32-bit word operations.
>>   - Skip generating ginsns for movk, movz, movn.  These do more work than
>>     just simple mov; Skip generating ginsn altogether for these.
>>   - ginsn_dw2_regnum () is now switch case on opnd_class.  Each case
>>     exposed by the current set of ginsn creation logic is handled.
>>   - Skip Z register usage altogether for now.  Skip sve_misc iclass but
>>     error out if callee-saved FP/Advanced SIMD registers or stack
>>     management are involved.
>> [End of changes in V4]
>>
>> [No changes in V3]
>>
>> [Changes in V2]
>> - Factored out the ginsn creation functionality from tc-aarch64.c into
>> tc-aarch64-ginsn.c.
>> - The switch case in aarch64_ginsn_new now is based on iclass rather
>> than (earlier) opcode.
>> - Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
>> aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
>> - Explicitly whitelist irg insn.
>> - Other minor code comment and readability fixes.
>> [End of changes in V2]
>>
>> For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
>> GAS works on the generic GAS insns (ginsns).  This patch adds support in
>> the aarch64 backend to create ginsns for a subset of the supported
>> machine instructions.  The subset includes the minimal necessary
>> instructions to ensure SCFI correctness:
>>
>> - Any potential register saves and unsaves.  Hence, process instructions
>>    belonging to a variety of iclasses involving str, ldr, stp, ldp.
>> - Any change of flow instructions.  This includes all conditional and
>>    unconditional branches, call (bl, blr, etc.) and return.
>> - Most importantly, any instruction that could affect the two registers
>>    of interest: REG_SP, REG_FP.  This set includes all pre-indexed and
>>    post-indexed memory operations, with writeback, on the stack.  This
>>    set must also include other instructions (e.g., arithmetic insns)
>>    where the destination register is one of the afore-mentioned registers.
>>
>> With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
>> registers D8-D15 are included along with the relevant GPRs.  Calculating
>> offsets for loads and stores especially for Q registers needs special
>> attention here.
>>
>> As an example,
>>     str q8, [sp, #16]
>> On big-endian:
>>     STR Qn stores as a 128-bit integer (MSB first), hence, should record
>>     D8 as being saved at sp+24 rather than sp+16.
>> On little-endian:
>>     should record D8 as being saved at sp+16
>>
>> D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
>> hence, they remain "interesting" for SCFI purposes in such cases.  A CFI
>> save slot always represents the low 64 bits, regardless of whether a
>> save occurs on D, Q or Z registers.  Currently, the ginsn creation
>> machinery can handle D and Q registers on little-endian and big-endian.
>>
>> Apart from creating ginsn, another key responsibility of the backend is
>> to make sure there are safeguards in place to detect and alert if an
>> instruction of interest may have been skipped.  This is done via
>> aarch64_ginsn_unhandled () (similar to the x86 backend).  This function
>> , hence, is also intended to alert when future ISA changes may otherwise
>> render SCFI results incorrect, because of missing ginsns for the newly
>> added machine instructions.
>>
>> At this time, becuase of the complexities wrt endianness in handling Z
>> register usage, skip sve_misc opclass altogether for now.  The SCFI
>> machinery will error out (using the aarch64_ginsn_unhandled () code
>> path) though if Z register usage affects correctness.
>>
>> The current SCFI machinery does not currently synthesize the
>> PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame.  The
>> support for this is planned for near future.
>>
>> SCFI is enabled for ELF targets only.
>>
>> gas/
>> 	* config/tc-aarch64-ginsn.c: New file.
>> 	* config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
>> 	file.  Invoke aarch64_ginsn_new.
>> 	* config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
>> 	enablement.
>> 	(TARGET_USE_SCFI): Likewise.
>> 	(SCFI_MAX_REG_ID): New definition.
>> 	(REG_FP): Likewise.
>> 	(REG_LR): Likewise.
>> 	(REG_SP): Likewise.
>> 	(SCFI_INIT_CFA_OFFSET): Likewise.
>> 	(SCFI_CALLEE_SAVED_REG_P): Likewise.
>> 	(aarch64_scfi_callee_saved_p): New declaration.
>> ---
>>   gas/config/tc-aarch64-ginsn.c | 797 ++++++++++++++++++++++++++++++++++
>>   gas/config/tc-aarch64.c       |  15 +
>>   gas/config/tc-aarch64.h       |  21 +
>>   3 files changed, 833 insertions(+)
>>   create mode 100644 gas/config/tc-aarch64-ginsn.c
>>
>> diff --git a/gas/config/tc-aarch64-ginsn.c b/gas/config/tc-aarch64-ginsn.c
>> new file mode 100644
>> index 00000000000..dbee8df88b1
>> --- /dev/null
>> +++ b/gas/config/tc-aarch64-ginsn.c
>> @@ -0,0 +1,797 @@
>> +/* tc-aarch64-ginsn.c -- Ginsn generation for the AArch64 ISA
>> +
>> +   Copyright (C) 2024 Free Software Foundation, Inc.
>> +   Contributed by ARM Ltd.
> 
> Not so :)
> 

Removed the line.

>> +
>> +   This file is part of GAS.
>> +
>> +   GAS is free software; you can redistribute it and/or modify
>> +   it under the terms of the GNU General Public License as published by
>> +   the Free Software Foundation; either version 3 of the license, or
>> +   (at your option) any later version.
>> +
>> +   GAS is distributed in the hope that it will be useful,
>> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
>> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> +   GNU General Public License for more details.
>> +
>> +   You should have received a copy of the GNU General Public License
>> +   along with this program; see the file COPYING3. If not,
>> +   see <http://www.gnu.org/licenses/>.  */
>> +
>> +/* This file contains the implementation of the ginsn creation for aarch64
>> +   instructions.  Most functions will read the aarch64_instruction inst
>> +   object, but none should need to modify it.  */
>> +
>> +#ifdef OBJ_ELF
>> +
>> +/* DWARF register number for R1.  Used as dummy value when WZR.  */
>> +#define GINSN_DW2_REGNUM_R1_DUMMY 1
>> +
>> +/* Return whether the given register number is a callee-saved register for
>> +   SCFI purposes.
>> +
>> +   Apart from the callee-saved GPRs, SCFI always tracks SP, FP and LR
>> +   additionally.  As for the FP/Advanced SIMD registers, v8-v15 are
>> +   callee-saved.  */
>> +
>> +bool
>> +aarch64_scfi_callee_saved_p (unsigned int dw2reg_num)
>> +{
>> +  /* PS: Ensure SCFI_MAX_REG_ID is the max DWARF register number to cover
>> +     all the registers here.  */
>> +  if (dw2reg_num == REG_SP /* x31.  */
>> +      || dw2reg_num == REG_FP /* x29.  */
>> +      || dw2reg_num == REG_LR /* x30.  */
>> +      || (dw2reg_num >= 19 && dw2reg_num <= 28) /* x19 - x28.  */
>> +      || (dw2reg_num >= 72 && dw2reg_num <= 79) /* v8 - v15.  */)
>> +    return true;
>> +
>> +  return false;
>> +}
>> +
>> +/* Get the DWARF register number for the given OPND.
>> +   Whether 31 is used to encode WZR or SP is specified via SP_ALLOWED_P.
>> +
>> +   The caller must decide the value of SP_ALLOWED_P based on the instruction
>> +   encoding.  */
>> +
>> +static unsigned int
>> +ginsn_dw2_regnum (aarch64_opnd_info *opnd, bool sp_allowed_p)
> 
> Couldn't this use operand_maybe_stack_pointer instead of taking
> an sp_allowed_p parameter?
> 

Thanks. I can get rid of sp_allowed_p arg altogether now, and simply use:

       if (aarch64_zero_register_p (opnd))
         dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
       else
         ...

for appropriate opnd_class.  The sp_allowed_p was only to detect WZR vs 
REG_SP.

>> +{
>> +  enum aarch64_operand_class opnd_class;
>> +  unsigned int dw2reg_num = 0;
>> +
>> +  opnd_class = aarch64_get_operand_class (opnd->type);
>> +
>> +  switch (opnd_class)
>> +    {
>> +    case AARCH64_OPND_CLASS_FP_REG:
>> +      dw2reg_num = opnd->reg.regno + 64;
>> +      break;
>> +    case AARCH64_OPND_CLASS_SVE_REGLIST:
>> +      dw2reg_num = opnd->reglist.first_regno + 64;
>> +      break;
>> +    case AARCH64_OPND_CLASS_MODIFIED_REG:
>> +    case AARCH64_OPND_CLASS_INT_REG:
>> +    case AARCH64_OPND_CLASS_ADDRESS:
>> +      /* Use a dummy register value in case of WZR, else this will be an
>> +	 incorrect dependency on REG_SP.  */
>> +      if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>> +	dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>> +      else
>> +	/* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>> +	   DWARF register number is the same as AArch64 register number.  */
>> +	dw2reg_num = opnd->reg.regno;
>> +      break;
> 
> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
> instead.  AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
> 

Made the correction for AARCH64_OPND_CLASS_ADDRESS.

But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is 
still correct in opnd->reg.regno, IIUC.  It seems to me that the only 
information available in the opnd->shifter is how the register is 
modified by additional work (shift, multiply etc.); This information is 
not used by SCFI:
   - an add/sub with two source register and destination REG_SP/ REG_FP 
makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does 
not hurt SCFI correctness.
   - Cant think of other operations where the shift amount will affect 
SCFI correctness..

So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at 
opnd->shifter." of the review comment.

>> +    case AARCH64_OPND_CLASS_SYSTEM:
>> +      /* For prfm etc., where a opnd->type AARCH64_OPND_PRFOP is seen.  */
>> +      dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>> +      break;
> 
> Hopefully this goes away if we treat PRFM as "other".
> 

There were workflows from aarch64_ginsn_unhandled () where we were 
calling ginsn_dw2_regnum (). But I have now corrected that callsite to 
first check for !aarch64_opcode_subclass_p (opcode, F_SUBCLASS_OTHER) 
which was necessary to be checked anyway.

So, yes, this stub for AARCH64_OPND_CLASS_SYSTEM in ginsn_dw2_regnum () 
can now go away.

>> +    default:
>> +      as_bad ("Unexpected value in ginsn_dw2_regnum");
>> +      break;
>> +    }
>> +
>> +  return dw2reg_num;
>> +}
>> +
>> +/* Generate ginsn for addsub instructions with immediate opnd.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn = NULL;
>> +  bool add_p, sub_p;
>> +  offsetT src_imm = 0;
>> +  unsigned int dst_reg, opnd_reg;
>> +  aarch64_opnd_info *dst, *opnd;
>> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
>> +			 enum ginsn_src_type, unsigned int, offsetT,
>> +			 enum ginsn_src_type, unsigned int, offsetT,
>> +			 enum ginsn_dst_type, unsigned int, offsetT);
>> +
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>> +  gas_assert (add_p || sub_p);
>> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>> +
>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>> +  dst = &base->operands[0];
>> +  opnd = &base->operands[1];
>> +
>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>> +
>> +  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>> +    src_imm = inst.reloc.exp.X_add_number;
>> +  /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
>> +     and handle via aarch64_ginsn_unhandled () code path.  */
>> +  else if (inst.reloc.type != BFD_RELOC_UNUSED)
>> +    return ginsn;
>> +  /* FIXME - verify the understanding and remove assert.  */
>> +  else
>> +    gas_assert (0);
>> +
>> +  opnd_reg = ginsn_dw2_regnum (opnd, true);
>> +
>> +  ginsn = ginsn_func (insn_end_sym, true,
>> +		      GINSN_SRC_REG, opnd_reg, 0,
>> +		      GINSN_SRC_IMM, 0, src_imm,
>> +		      GINSN_DST_REG, dst_reg, 0);
>> +  ginsn_set_where (ginsn);
>> +
>> +  return ginsn;
>> +}
>> +
>> +/* Generate ginsn for addsub instructions with reg opnd.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn = NULL;
>> +  bool add_p, sub_p;
>> +  unsigned int dst_reg, src1_reg, src2_reg;
>> +  aarch64_opnd_info *dst, *src1, *src2;
>> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
>> +			 enum ginsn_src_type, unsigned int, offsetT,
>> +			 enum ginsn_src_type, unsigned int, offsetT,
>> +			 enum ginsn_dst_type, unsigned int, offsetT);
>> +
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>> +  gas_assert (add_p || sub_p);
>> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>> +
>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>> +  dst = &base->operands[0];
>> +  src1 = &base->operands[1];
>> +  src2 = &base->operands[2];
>> +
>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>> +  src1_reg = ginsn_dw2_regnum (src1, true);
>> +  src2_reg = ginsn_dw2_regnum (src2, false);
>> +
>> +  ginsn = ginsn_func (insn_end_sym, true,
>> +		      GINSN_SRC_REG, src1_reg, 0,
>> +		      GINSN_SRC_REG, src2_reg, 0,
>> +		      GINSN_DST_REG, dst_reg, 0);
>> +  ginsn_set_where (ginsn);
> 
> It looks like this ignores any shift that is applied to src2_reg.
> 

Yes.  An add/sub operation with two source registers makes REG_SP/REG_FP 
untraceable (if dest is REG_SP/REG_FP), so any further information 
carried forward in the ginsn is of little use for SCFI.

For a usecase apart from SCFI, yes, this may amount to loss of vital 
information. I will add a TBD_GINSN_INFO_LOSS comment.

>> +
>> +  return ginsn;
>> +}
>> +
>> +/* Generate ginsn for the load pair and store pair instructions.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_ldstp (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn = NULL;
>> +  ginsnS *ginsn_ind = NULL;
>> +  ginsnS *ginsn_mem1 = NULL;
>> +  ginsnS *ginsn_mem2 = NULL;
>> +  unsigned int opnd_reg, addr_reg;
>> +  offsetT offset, mem_offset;
>> +  unsigned int width = 8;
>> +  bool store_p = false;
>> +
>> +  aarch64_opnd_info *opnd1, *opnd2, *addr;
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  /* This function is for handling ldp / stp ops only.  */
>> +  gas_assert (opcode->iclass == ldstpair_indexed
>> +	      || opcode->iclass == ldstpair_off);
>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>> +
>> +  opnd1 = &base->operands[0];
>> +  opnd2 = &base->operands[1];
>> +  addr = &base->operands[2];
>> +  store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
>> +
>> +  addr_reg = ginsn_dw2_regnum (addr, true);
>> +  gas_assert (!addr->addr.offset.is_reg);
>> +  mem_offset = addr->addr.offset.imm;
>> +
>> +  /* ldstp may load or store two 32-bit words or two 64-bit doublewords.  */
>> +  if (opnd1->qualifier == AARCH64_OPND_QLF_W
>> +      || opnd1->qualifier == AARCH64_OPND_QLF_S_S)
>> +    width = 4;
>> +
>> +  /* Handle address calculation.  */
>> +  if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
>> +    {
>> +      /* Pre-indexed store, e.g., stp x29, x30, [sp, -128]!
>> +	 Pre-indexed addressing is like offset addressing, except that
>> +	 the base pointer is updated as a result of the instruction.
>> +
>> +	 Post-indexed store, e.g., stp     x29, x30, [sp],128
>> +	 Post-index addressing is useful for popping off the stack.  The
>> +	 instruction loads the value from the location pointed at by the stack
>> +	 pointer, and then moves the stack pointer on to the next full location
>> +	 in the stack.  */
>> +      ginsn_ind = ginsn_new_add (insn_end_sym, false,
>> +				 GINSN_SRC_REG, addr_reg, 0,
>> +				 GINSN_SRC_IMM, 0, mem_offset,
>> +				 GINSN_DST_REG, addr_reg, 0);
>> +      ginsn_set_where (ginsn_ind);
>> +    }
>> +
>> +  /* Save / restore of WZR is not of interest for SCFI.  However, the address
>> +     processing component may have updated the stack pointer.  At least, emit
>> +     that ginsn and return.  PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
>> +     now;  Check explicitly the regno for WZR.  Also note,
>> +     TBD_GINSN_GEN_NOT_SCFI.  */
>> +  if (opnd1->reg.regno == REG_SP /* WZR.  */)
>> +    return ginsn_ind;
>> +
>> +  /* With post-index addressing, the value is loaded from the
>> +     address in the base pointer, and then the pointer is updated.
>> +     With pre-index addressing, the addr computation has already
>> +     been explicitly done.  */
>> +  offset = mem_offset;
>> +  if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>> +    offset = 0;
> 
> I guess this is personal taste, but IMO it would be easier to follow if
> this were combined with the "if" above, so that the compensating action
> of ginsn_ind is next to the creation of ginsn_ind itself.
> 

Yes, makes it easier to parse. I have restructured the code a bit.

>> +
>> +  if (opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
>> +    {
>> +      width = 16;
>> +      if (target_big_endian)
>> +	offset += 8;
>> +    }
>> +
>> +  opnd_reg = ginsn_dw2_regnum (opnd1, false);
>> +  if (store_p)
>> +    {
>> +      ginsn_mem1 = ginsn_new_store (insn_end_sym, false,
>> +				    GINSN_SRC_REG, opnd_reg,
>> +				    GINSN_DST_INDIRECT, addr_reg, offset);
>> +      ginsn_set_where (ginsn_mem1);
>> +
>> +      opnd_reg = ginsn_dw2_regnum (opnd2, false);
>> +      ginsn_mem2 = ginsn_new_store (insn_end_sym, false,
>> +				    GINSN_SRC_REG, opnd_reg,
>> +				    GINSN_DST_INDIRECT, addr_reg,
>> +				    offset + width);
>> +      ginsn_set_where (ginsn_mem2);
>> +    }
>> +  else
>> +    {
>> +      opnd_reg = ginsn_dw2_regnum (opnd1, false);
>> +      ginsn_mem1 = ginsn_new_load (insn_end_sym, false,
>> +				   GINSN_SRC_INDIRECT, addr_reg, offset,
>> +				   GINSN_DST_REG, opnd_reg);
>> +      ginsn_set_where (ginsn_mem1);
>> +
>> +      opnd_reg = ginsn_dw2_regnum (opnd2, false);
>> +      ginsn_mem2 = ginsn_new_load (insn_end_sym, false,
>> +				   GINSN_SRC_INDIRECT, addr_reg, offset + width,
>> +				   GINSN_DST_REG, opnd_reg);
>> +      ginsn_set_where (ginsn_mem2);
>> +    }
>> +
>> +  /* Link the list of ginsns created.  */
>> +  if (addr->addr.preind && addr->addr.writeback)
>> +    gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem1));
>> +
>> +  gas_assert (!ginsn_link_next (ginsn_mem1, ginsn_mem2));
>> +
>> +  if (addr->addr.postind && addr->addr.writeback)
>> +    gas_assert (!ginsn_link_next (ginsn_mem2, ginsn_ind));
>> +
>> +  /* Make note of the first instruction in the list.  */
>> +  ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem1;
>> +  return ginsn;
>> +}
>> +
>> +/* Generate ginsn for load and store instructions.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_ldstr (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn = NULL;
>> +  ginsnS *ginsn_ind = NULL;
>> +  ginsnS *ginsn_mem = NULL;
>> +  unsigned int opnd_reg, addr_reg;
>> +  offsetT offset, mem_offset;
>> +  bool store_p = false;
>> +
>> +  aarch64_opnd_info *opnd1, *addr;
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  /* This function is for handling ldr, str ops only.  */
>> +  gas_assert (opcode->iclass == ldst_imm9 || opcode->iclass == ldst_pos);
>> +  gas_assert (aarch64_num_of_operands (opcode) == 2);
>> +
>> +  opnd1 = &base->operands[0];
>> +  addr = &base->operands[1];
>> +  store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
>> +
>> +  addr_reg = ginsn_dw2_regnum (addr, true);
>> +
>> +  /* STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}].
>> +     LDR <Xt>, [<Xn|SP>], #<simm>.  */
>> +  opnd_reg = ginsn_dw2_regnum (opnd1, false);
>> +
>> +  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>> +    mem_offset = inst.reloc.exp.X_add_number;
>> +  else
>> +    {
>> +      gas_assert (!addr->addr.offset.is_reg);
>> +      mem_offset = addr->addr.offset.imm;
>> +    }
>> +
>> +  /* Handle address calculation.  */
>> +  if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
>> +    {
>> +      ginsn_ind = ginsn_new_add (insn_end_sym, false,
>> +				 GINSN_SRC_REG, addr_reg, 0,
>> +				 GINSN_SRC_IMM, 0, mem_offset,
>> +				 GINSN_DST_REG, addr_reg, 0);
>> +      ginsn_set_where (ginsn_ind);
>> +    }
>> +
>> +  /* Save / restore of WZR is not of interest for SCFI.  However, the address
>> +     processing component may have updated the stack pointer.  At least, emit
>> +     that ginsn and return.  PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
>> +     now;  Check explicitly the regno for WZR.  Also note,
>> +     TBD_GINSN_GEN_NOT_SCFI.  */
>> +  if (opnd1->reg.regno == REG_SP /* WZR.  */)
>> +    return ginsn_ind;
>> +
>> +  /* With post-index addressing, the value is loaded from the
>> +     address in the base pointer, and then the pointer is updated.
>> +     With pre-index addressing, the addr computation has already
>> +     been explicitly done.  */
>> +  offset = mem_offset;
>> +  if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>> +    offset = 0;
> 
> Same comment as above.
> 

Done.

>> +  if (target_big_endian && opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
>> +    offset += 8;
>> +
>> +  if (store_p)
>> +    ginsn_mem = ginsn_new_store (insn_end_sym, false,
>> +				 GINSN_SRC_REG, opnd_reg,
>> +				 GINSN_DST_INDIRECT, addr_reg, offset);
>> +  else
>> +    ginsn_mem = ginsn_new_load (insn_end_sym, false,
>> +				GINSN_SRC_INDIRECT, addr_reg, offset,
>> +				GINSN_DST_REG, opnd_reg);
>> +  ginsn_set_where (ginsn_mem);
>> +
>> +  if (addr->addr.preind && addr->addr.writeback)
>> +    gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem));
>> +  else if (addr->addr.postind && addr->addr.writeback)
>> +    gas_assert (!ginsn_link_next (ginsn_mem, ginsn_ind));
>> +
>> +  /* Make note of the first instruction in the list.  */
>> +  ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem;
>> +
>> +  return ginsn;
>> +}
>> +
>> +/* Generate ginsn for unconditional branch instructions.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_branch_uncond (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn = NULL;
>> +  const symbolS *src_symbol = NULL;
>> +  enum ginsn_src_type src_type = GINSN_SRC_UNKNOWN;
>> +  unsigned int src_reg = 0;
>> +
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  if (opcode->iclass == branch_imm)
>> +    {
>> +      /* b or bl.  opcode 0x14000000 or 0x94000000.  */
>> +      gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_CALL26
>> +		  || inst.reloc.type == BFD_RELOC_AARCH64_JUMP26);
> 
> It's possible to specify an immediate operand too:
> 
> 	b	4
> 

I should explicitly skip these instructions and error out.  These 
instructions make CFG creation not easy.

The same behaviour should be done for "b symbol+1", i.e., symbol+addend.

>> +      src_symbol = inst.reloc.exp.X_add_symbol;
>> +      src_type = GINSN_SRC_SYMBOL;
>> +    }
>> +  else if (aarch64_num_of_operands (opcode) >= 1)
>> +    {
>> +      gas_assert (opcode->iclass == branch_reg);
>> +      /* Some insns (e.g., braa, blraa etc.) may have > 1 operands.  For
>> +	 current SCFI implementation, it suffices however to simply pass
>> +	 the information about the first source.  Although, strictly speaking,
>> +	 (if reg) the source info is currently of no material use either.  */
>> +      src_type = GINSN_SRC_REG;
>> +      src_reg = ginsn_dw2_regnum (&base->operands[0], false);
>> +    }
>> +
>> +  if (aarch64_opcode_subclass_p (opcode, F_BRANCH_CALL))
>> +    {
>> +      gas_assert (src_type != GINSN_SRC_UNKNOWN);
>> +      ginsn = ginsn_new_call (insn_end_sym, true,
>> +			      src_type, src_reg, src_symbol);
>> +    }
>> +  else if (aarch64_opcode_subclass_p (opcode, F_BRANCH_RET))
>> +    /* TBD_GINSN_REPRESENTATION_LIMIT.  The following function to create a
>> +       GINSN_TYPE_RETURN does not allow src info ATM.  */
>> +    ginsn = ginsn_new_return (insn_end_sym, true);
>> +  else
>> +    ginsn = ginsn_new_jump (insn_end_sym, true,
>> +			    src_type, src_reg, src_symbol);
>> +
>> +  ginsn_set_where (ginsn);
>> +
>> +  return ginsn;
>> +}
>> +
>> +/* Generate ginsn for conditional branch instructions.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_branch_cond (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn;
>> +  const symbolS *src_symbol;
>> +  enum ginsn_src_type src_type;
>> +
>> +  gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_BRANCH19
>> +	      || inst.reloc.type == BFD_RELOC_AARCH64_TSTBR14);
> 
> Similarly here, it's possible to write:
> 
> 	cbz	x0, 4
> 

Thank you for bringing these up. I will need to explicitly skip these 
instructions and error out.  These instructions make CFG creation not easy.

>> +
>> +  src_symbol = inst.reloc.exp.X_add_symbol;
>> +  src_type = GINSN_SRC_SYMBOL;
>> +  ginsn = ginsn_new_jump_cond (insn_end_sym, true, src_type, 0, src_symbol);
>> +  ginsn_set_where (ginsn);
>> +
>> +  return ginsn;
>> +}
>> +
>> +/* Generate ginsn for mov instructions.  */
>> +
>> +static ginsnS *
>> +aarch64_ginsn_mov (const symbolS *insn_end_sym)
>> +{
>> +  ginsnS *ginsn = NULL;
>> +  unsigned int src_reg = 0, dst_reg;
>> +  aarch64_opnd_info *src, *dst;
>> +  offsetT src_imm = 0;
>> +  enum ginsn_src_type src_type;
>> +
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  gas_assert (aarch64_num_of_operands (opcode) == 2);
>> +
>> +  dst = &base->operands[0];
>> +  src = &base->operands[1];
>> +
>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>> +
>> +  /* For some mov ops, e.g., movn, movk, or movz, there may optionally be more
>> +     work than just a simple mov.  Skip handling these mov altogether and let
>> +     the aarch64_ginsn_unhandled () alert if these insns affect SCFI
>> +     correctness.  TBD_GINSN_GEN_NOT_SCFI.  */
>> +  if (src->type == AARCH64_OPND_HALF)
>> +    return ginsn;
>> +
>> +  if (src->type == AARCH64_OPND_IMM_MOV
>> +      && aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>> +    {
>> +      src_imm = inst.reloc.exp.X_add_number;
>> +      src_type = GINSN_SRC_IMM;
>> +    }
>> +  else
>> +    {
>> +      /* mov   x27, sp.  */
>> +      src_reg = ginsn_dw2_regnum (src, true);
>> +      src_type = GINSN_SRC_REG;
>> +    }
> 
> The condition makes it seem like we could enter the "else" for
> src->type == AARCH64_OPND_IMM_MOV, although the code only accepts
> registers.
> 
> It might be better to put the immediate and register cases in
> separate functions, as for add/sub.  It's probably safer to punt
> for the immediate else case, since it is possible in principle
> to have a relocated MOV.
> 

Okay. I have created two versions of the mov functions:
  - aarch64_ginsn_mov_imm
  - aarch64_ginsn_mov_reg

>> +
>> +  ginsn = ginsn_new_mov (insn_end_sym, false,
>> +			 src_type, src_reg, src_imm,
>> +			 GINSN_DST_REG, dst_reg, 0);
>> +  ginsn_set_where (ginsn);
>> +
>> +  return ginsn;
>> +}
>> +
>> +/* Check if an instruction is whitelisted.
>> +
>> +   An instruction is a candidate for whitelisting if not generating ginsn for
>> +   it, does not affect SCFI correctness.
>> +
>> +   TBD_GINSN_GEN_NOT_SCFI.  This function assumes GINSN_GEN_SCFI is in effect.
>> +   When other ginsn_gen_mode are added, this will need fixing.  */
>> +
>> +static bool
>> +aarch64_ginsn_safe_to_skip_p (void)
>> +{
>> +  bool skip_p = false;
>> +  aarch64_opnd_info *opnd = NULL;
>> +  unsigned int dw2_regnum;
>> +  unsigned int opnd_reg;
>> +  int num_opnds = 0;
>> +
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +
>> +  /* ATM, whitelisting operations with no operands does not seem to be
>> +     necessary.  */
>> +  num_opnds = aarch64_num_of_operands (opcode);
>> +  if (!num_opnds)
>> +    return skip_p;
> 
> Things like ERET show that this would be dangerous, so it might be better
> to make the false return explicit (and adjust the comment).
> 

I am not sure I understand the "make false return explicit".  I have 
adjusted the code and comment:

   /* ATM, whitelisting operations with no operands does not seem to be
      necessary.  In fact, whitelisting insns like ERET will be 
dangerous for
      SCFI.  So, return false now and bar any such insns from being 
whitelisted
      altogether.  */
   num_opnds = aarch64_num_of_operands (opcode);
   if (!num_opnds)
     return false;

Is this what you meant ?

>> +
>> +  opnd = &base->operands[0];
>> +
>> +  switch (opcode->iclass)
>> +    {
>> +    case ldst_regoff:
>> +      /* It is not expected to have reg offset based ld/st ops to be used
>> +	 for reg save and restore operations.  Warn the user though.  */
>> +      opnd_reg = ginsn_dw2_regnum (opnd, false);
>> +      if (aarch64_scfi_callee_saved_p (opnd_reg))
>> +	{
>> +	  skip_p = true;
>> +	  as_warn ("SCFI: ignored probable save/restore op with reg offset");
>> +	}
>> +      break;
>> +
>> +    case dp_2src:
>> +      /* irg insn needs to be explicitly whitelisted.  This is because the
>> +	 dest is Rd_SP, but irg insn affects the tag only.  To detect irg
>> +	 insn, avoid an opcode-based check, however.  */
> 
> I think we should check specifically for IRG (via subclasses).
> Admittedly none of the others do anything sensible for SP, but other
> instructions could be added in future.
> 

True.

I added a new patch that adds subclass flags for the dp_2src insns:
   - F_DP_TAG_ONLY for irg (How suitable is the name ?)
   - F_SUBCLASS_OTHER for all other insns of iclass dp_2src

Now the above check looks for irg via that subclass flag.

>> +      if (opnd->type == AARCH64_OPND_Rd_SP)
>> +	{
>> +	  dw2_regnum = ginsn_dw2_regnum (opnd, true);
>> +	  if (dw2_regnum == REG_SP)
>> +	    skip_p = true;
>> +	}
>> +      break;
>> +
>> +    default:
>> +      break;
>> +    }
>> +
>> +  return skip_p;
>> +}
>> +
>> +#define AARCH64_GINSN_UNHANDLED_NONE        0
>> +#define AARCH64_GINSN_UNHANDLED_DEST_REG    1
>> +#define AARCH64_GINSN_UNHANDLED_CFG         2
>> +#define AARCH64_GINSN_UNHANDLED_STACKOP     3
>> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED  4
>> +
>> +/* Check the input insn for its impact on the correctness of the synthesized
>> +   CFI.  Returns an error code to the caller.  */
>> +
>> +static int
>> +aarch64_ginsn_unhandled (void)
>> +{
>> +  int err = AARCH64_GINSN_UNHANDLED_NONE;
>> +  aarch64_inst *base = &inst.base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +  aarch64_opnd_info *dest = &base->operands[0];
>> +  int num_opnds = aarch64_num_of_operands (opcode);
>> +  aarch64_opnd_info *addr;
>> +  unsigned int dw2_regnum;
>> +  unsigned int addr_reg;
>> +  aarch64_opnd_info *opnd = NULL;
>> +  unsigned int opnd_reg;
>> +  bool sp_allowed_p = false;
>> +
>> +  /* All change of flow instructions are important for SCFI.  */
>> +  if (opcode->iclass == condbranch
>> +      || opcode->iclass == compbranch
>> +      || opcode->iclass == testbranch
>> +      || opcode->iclass == branch_imm
>> +      || opcode->iclass == branch_reg)
>> +    err = AARCH64_GINSN_UNHANDLED_CFG;
>> +  /* Also, any memory instructions that may involve an update to the stack
>> +     pointer or save/restore of callee-saved registers must not be skipped.
>> +     Note that, some iclasses cannot be used to push or pop stack because of
>> +     disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
>> +     loadlit, ldstnapair_offs.  FIXME double-check.
>> +     Also, these iclasses do not seem to be amenable to being used for
>> +     save/restore ops either.  FIXME double-check.  */
>> +  else if (opcode->iclass == ldstpair_off
>> +	   || opcode->iclass == ldstpair_indexed
>> +	   || opcode->iclass == ldst_imm9
>> +	   || opcode->iclass == ldst_imm10
>> +	   || opcode->iclass == ldst_pos
>> +  /* STR Zn are especially complicated as they do not store in the same byte
>> +     order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
>> +     whereas STR Zn stores as a stream of bytes (LSB first).  FIXME Simply punt
>> +     on the big-endian and little-endian SVE PCS case for now.  */
>> +	   || opcode->iclass == sve_misc)
>> +    {
>> +      opnd = &base->operands[0];
>> +      addr = &base->operands[num_opnds - 1];
>> +      addr_reg = ginsn_dw2_regnum (addr, true);
>> +      opnd_reg = ginsn_dw2_regnum (opnd, false);
>> +      /* For all skipped memory operations, check if an update to REG_SP or
>> +	 REG_FP is involved.  */
>> +      if ((addr_reg == REG_SP || addr_reg == REG_FP)
>> +	  && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>> +	      || aarch64_scfi_callee_saved_p (opnd_reg)))
>> +
>> +	err = AARCH64_GINSN_UNHANDLED_STACKOP;
> 
> The way I'd imagined this working is that we'd use two-directional data
> flow to record which callee-saved registers are "protected" at which
> instructions.  That is, for saves we'd walk the cfg forward from the
> entry point, recording which registers have been saved earlier in the walk
> (and being conservatively correct for cycles).  And for restores we'd
> walk the cfg backwards from the exit points, recording which registers
> are restored later in the walk.  If a register is both "saved ealier" and
> "restored later" for a given instruction, it wouldn't matter what the
> instruction does with that register.
> 
> (For infinite loops we would pretend that all registers are restored later.)
> 
> It seems like instead, we'd generate a warning for:
> 
>          ...
>          str     d8, [sp, #...]
>          ...
>          ld1d    z8.b, p0/z, [sp, #...]
>          ...
>          ldr     d8, [sp, #...]
>          ...
>          ret
> 
> even though that should be ok (even without interpreting SVE instructions).
> 
> On the other hand, any read or write of a callee-saved register is suspicious
> if it isn't saved earlier or isn't restored later.
> 
> In other words, it seems like this information should be context-dependent,
> or used in a context-dependent way.  Whether a particular register matters
> depends on whether the register might still contain the caller's data.
> 

We do something similar for non-memory ops:
  - In the aarch64_ginsn_unhandled () codepath, if the destination is of 
interest (REG_SP, REG_FP), synthesize a GINSN_TYPE_OTHER with the 
appropriate destination register if no ginsn has been generated.
  - The SCFI machinery checks if this instruction affects SCFI correctness.
  - If it does, only then the insn is issued a complaint for and brought 
to attention.

What you suggest is take a similar approach for memory operations too. 
I think it makes sense.  It needs some work now to accommodate this, but 
I think we can re-evaluate after some basic handling for Z registers is 
in place ? I plan to work on adding handling for Z registers after this 
series is merged. (I have renamed an old testcase involving Z registers 
to "scfi-unsupported-2.s" to keep track of the currently unsupported 
cases to be worked on in near future, so I dont lose track of this..).

Thanks
Indu
  
Richard Sandiford July 11, 2024, 1:15 p.m. UTC | #3
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/1/24 12:49, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> +{
>>> +  enum aarch64_operand_class opnd_class;
>>> +  unsigned int dw2reg_num = 0;
>>> +
>>> +  opnd_class = aarch64_get_operand_class (opnd->type);
>>> +
>>> +  switch (opnd_class)
>>> +    {
>>> +    case AARCH64_OPND_CLASS_FP_REG:
>>> +      dw2reg_num = opnd->reg.regno + 64;
>>> +      break;
>>> +    case AARCH64_OPND_CLASS_SVE_REGLIST:
>>> +      dw2reg_num = opnd->reglist.first_regno + 64;
>>> +      break;
>>> +    case AARCH64_OPND_CLASS_MODIFIED_REG:
>>> +    case AARCH64_OPND_CLASS_INT_REG:
>>> +    case AARCH64_OPND_CLASS_ADDRESS:
>>> +      /* Use a dummy register value in case of WZR, else this will be an
>>> +	 incorrect dependency on REG_SP.  */
>>> +      if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>>> +	dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>>> +      else
>>> +	/* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>>> +	   DWARF register number is the same as AArch64 register number.  */
>>> +	dw2reg_num = opnd->reg.regno;
>>> +      break;
>> 
>> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
>> instead.  AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>> 
>
> Made the correction for AARCH64_OPND_CLASS_ADDRESS.
>
> But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is 
> still correct in opnd->reg.regno, IIUC.  It seems to me that the only 
> information available in the opnd->shifter is how the register is 
> modified by additional work (shift, multiply etc.); This information is 
> not used by SCFI:
>    - an add/sub with two source register and destination REG_SP/ REG_FP 
> makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does 
> not hurt SCFI correctness.
>    - Cant think of other operations where the shift amount will affect 
> SCFI correctness..
>
> So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at 
> opnd->shifter." of the review comment.

It's more about type correctness.  "shifter" is the data associated with
AARCH64_OPND_CLASS_MODIFIED_REG and "reg" is the data associated with
AARCH64_OPND_CLASS_INT_REG etc.  I think it's mostly a coincidence
that the "reg" and "shifter" alternatives of the union put the register
at the same byte offset from the start of the structure.

>>> +    default:
>>> +      as_bad ("Unexpected value in ginsn_dw2_regnum");
>>> +      break;
>>> +    }
>>> +
>>> +  return dw2reg_num;
>>> +}
>>> +
>>> +/* Generate ginsn for addsub instructions with immediate opnd.  */
>>> +
>>> +static ginsnS *
>>> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
>>> +{
>>> +  ginsnS *ginsn = NULL;
>>> +  bool add_p, sub_p;
>>> +  offsetT src_imm = 0;
>>> +  unsigned int dst_reg, opnd_reg;
>>> +  aarch64_opnd_info *dst, *opnd;
>>> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>> +			 enum ginsn_dst_type, unsigned int, offsetT);
>>> +
>>> +  aarch64_inst *base = &inst.base;
>>> +  const aarch64_opcode *opcode = base->opcode;
>>> +
>>> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>> +  gas_assert (add_p || sub_p);
>>> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>> +
>>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>>> +  dst = &base->operands[0];
>>> +  opnd = &base->operands[1];
>>> +
>>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>>> +
>>> +  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>>> +    src_imm = inst.reloc.exp.X_add_number;
>>> +  /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
>>> +     and handle via aarch64_ginsn_unhandled () code path.  */
>>> +  else if (inst.reloc.type != BFD_RELOC_UNUSED)
>>> +    return ginsn;
>>> +  /* FIXME - verify the understanding and remove assert.  */
>>> +  else
>>> +    gas_assert (0);
>>> +
>>> +  opnd_reg = ginsn_dw2_regnum (opnd, true);
>>> +
>>> +  ginsn = ginsn_func (insn_end_sym, true,
>>> +		      GINSN_SRC_REG, opnd_reg, 0,
>>> +		      GINSN_SRC_IMM, 0, src_imm,
>>> +		      GINSN_DST_REG, dst_reg, 0);
>>> +  ginsn_set_where (ginsn);
>>> +
>>> +  return ginsn;
>>> +}
>>> +
>>> +/* Generate ginsn for addsub instructions with reg opnd.  */
>>> +
>>> +static ginsnS *
>>> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
>>> +{
>>> +  ginsnS *ginsn = NULL;
>>> +  bool add_p, sub_p;
>>> +  unsigned int dst_reg, src1_reg, src2_reg;
>>> +  aarch64_opnd_info *dst, *src1, *src2;
>>> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>> +			 enum ginsn_dst_type, unsigned int, offsetT);
>>> +
>>> +  aarch64_inst *base = &inst.base;
>>> +  const aarch64_opcode *opcode = base->opcode;
>>> +
>>> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>> +  gas_assert (add_p || sub_p);
>>> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>> +
>>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>>> +  dst = &base->operands[0];
>>> +  src1 = &base->operands[1];
>>> +  src2 = &base->operands[2];
>>> +
>>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>>> +  src1_reg = ginsn_dw2_regnum (src1, true);
>>> +  src2_reg = ginsn_dw2_regnum (src2, false);
>>> +
>>> +  ginsn = ginsn_func (insn_end_sym, true,
>>> +		      GINSN_SRC_REG, src1_reg, 0,
>>> +		      GINSN_SRC_REG, src2_reg, 0,
>>> +		      GINSN_DST_REG, dst_reg, 0);
>>> +  ginsn_set_where (ginsn);
>> 
>> It looks like this ignores any shift that is applied to src2_reg.
>> 
>
> Yes.  An add/sub operation with two source registers makes REG_SP/REG_FP 
> untraceable (if dest is REG_SP/REG_FP), so any further information 
> carried forward in the ginsn is of little use for SCFI.
>
> For a usecase apart from SCFI, yes, this may amount to loss of vital 
> information. I will add a TBD_GINSN_INFO_LOSS comment.

If SCFI doesn't handle add/sub of two registers, then do we still
need this code for correctness?  I would have expected SCFI to handle
unrecognised writes to SP in a conservative way, even if there is no
ginsn type defined for the instruction that sets SP.

>>> +
>>> +  ginsn = ginsn_new_mov (insn_end_sym, false,
>>> +			 src_type, src_reg, src_imm,
>>> +			 GINSN_DST_REG, dst_reg, 0);
>>> +  ginsn_set_where (ginsn);
>>> +
>>> +  return ginsn;
>>> +}
>>> +
>>> +/* Check if an instruction is whitelisted.
>>> +
>>> +   An instruction is a candidate for whitelisting if not generating ginsn for
>>> +   it, does not affect SCFI correctness.
>>> +
>>> +   TBD_GINSN_GEN_NOT_SCFI.  This function assumes GINSN_GEN_SCFI is in effect.
>>> +   When other ginsn_gen_mode are added, this will need fixing.  */
>>> +
>>> +static bool
>>> +aarch64_ginsn_safe_to_skip_p (void)
>>> +{
>>> +  bool skip_p = false;
>>> +  aarch64_opnd_info *opnd = NULL;
>>> +  unsigned int dw2_regnum;
>>> +  unsigned int opnd_reg;
>>> +  int num_opnds = 0;
>>> +
>>> +  aarch64_inst *base = &inst.base;
>>> +  const aarch64_opcode *opcode = base->opcode;
>>> +
>>> +  /* ATM, whitelisting operations with no operands does not seem to be
>>> +     necessary.  */
>>> +  num_opnds = aarch64_num_of_operands (opcode);
>>> +  if (!num_opnds)
>>> +    return skip_p;
>> 
>> Things like ERET show that this would be dangerous, so it might be better
>> to make the false return explicit (and adjust the comment).
>> 
>
> I am not sure I understand the "make false return explicit".  I have 
> adjusted the code and comment:
>
>    /* ATM, whitelisting operations with no operands does not seem to be
>       necessary.  In fact, whitelisting insns like ERET will be 
> dangerous for
>       SCFI.  So, return false now and bar any such insns from being 
> whitelisted
>       altogether.  */
>    num_opnds = aarch64_num_of_operands (opcode);
>    if (!num_opnds)
>      return false;
>
> Is this what you meant ?

Yes, thanks.

>>> +      if (opnd->type == AARCH64_OPND_Rd_SP)
>>> +	{
>>> +	  dw2_regnum = ginsn_dw2_regnum (opnd, true);
>>> +	  if (dw2_regnum == REG_SP)
>>> +	    skip_p = true;
>>> +	}
>>> +      break;
>>> +
>>> +    default:
>>> +      break;
>>> +    }
>>> +
>>> +  return skip_p;
>>> +}
>>> +
>>> +#define AARCH64_GINSN_UNHANDLED_NONE        0
>>> +#define AARCH64_GINSN_UNHANDLED_DEST_REG    1
>>> +#define AARCH64_GINSN_UNHANDLED_CFG         2
>>> +#define AARCH64_GINSN_UNHANDLED_STACKOP     3
>>> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED  4
>>> +
>>> +/* Check the input insn for its impact on the correctness of the synthesized
>>> +   CFI.  Returns an error code to the caller.  */
>>> +
>>> +static int
>>> +aarch64_ginsn_unhandled (void)
>>> +{
>>> +  int err = AARCH64_GINSN_UNHANDLED_NONE;
>>> +  aarch64_inst *base = &inst.base;
>>> +  const aarch64_opcode *opcode = base->opcode;
>>> +  aarch64_opnd_info *dest = &base->operands[0];
>>> +  int num_opnds = aarch64_num_of_operands (opcode);
>>> +  aarch64_opnd_info *addr;
>>> +  unsigned int dw2_regnum;
>>> +  unsigned int addr_reg;
>>> +  aarch64_opnd_info *opnd = NULL;
>>> +  unsigned int opnd_reg;
>>> +  bool sp_allowed_p = false;
>>> +
>>> +  /* All change of flow instructions are important for SCFI.  */
>>> +  if (opcode->iclass == condbranch
>>> +      || opcode->iclass == compbranch
>>> +      || opcode->iclass == testbranch
>>> +      || opcode->iclass == branch_imm
>>> +      || opcode->iclass == branch_reg)
>>> +    err = AARCH64_GINSN_UNHANDLED_CFG;
>>> +  /* Also, any memory instructions that may involve an update to the stack
>>> +     pointer or save/restore of callee-saved registers must not be skipped.
>>> +     Note that, some iclasses cannot be used to push or pop stack because of
>>> +     disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
>>> +     loadlit, ldstnapair_offs.  FIXME double-check.
>>> +     Also, these iclasses do not seem to be amenable to being used for
>>> +     save/restore ops either.  FIXME double-check.  */
>>> +  else if (opcode->iclass == ldstpair_off
>>> +	   || opcode->iclass == ldstpair_indexed
>>> +	   || opcode->iclass == ldst_imm9
>>> +	   || opcode->iclass == ldst_imm10
>>> +	   || opcode->iclass == ldst_pos
>>> +  /* STR Zn are especially complicated as they do not store in the same byte
>>> +     order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
>>> +     whereas STR Zn stores as a stream of bytes (LSB first).  FIXME Simply punt
>>> +     on the big-endian and little-endian SVE PCS case for now.  */
>>> +	   || opcode->iclass == sve_misc)
>>> +    {
>>> +      opnd = &base->operands[0];
>>> +      addr = &base->operands[num_opnds - 1];
>>> +      addr_reg = ginsn_dw2_regnum (addr, true);
>>> +      opnd_reg = ginsn_dw2_regnum (opnd, false);
>>> +      /* For all skipped memory operations, check if an update to REG_SP or
>>> +	 REG_FP is involved.  */
>>> +      if ((addr_reg == REG_SP || addr_reg == REG_FP)
>>> +	  && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>>> +	      || aarch64_scfi_callee_saved_p (opnd_reg)))
>>> +
>>> +	err = AARCH64_GINSN_UNHANDLED_STACKOP;
>> 
>> The way I'd imagined this working is that we'd use two-directional data
>> flow to record which callee-saved registers are "protected" at which
>> instructions.  That is, for saves we'd walk the cfg forward from the
>> entry point, recording which registers have been saved earlier in the walk
>> (and being conservatively correct for cycles).  And for restores we'd
>> walk the cfg backwards from the exit points, recording which registers
>> are restored later in the walk.  If a register is both "saved ealier" and
>> "restored later" for a given instruction, it wouldn't matter what the
>> instruction does with that register.
>> 
>> (For infinite loops we would pretend that all registers are restored later.)
>> 
>> It seems like instead, we'd generate a warning for:
>> 
>>          ...
>>          str     d8, [sp, #...]
>>          ...
>>          ld1d    z8.b, p0/z, [sp, #...]
>>          ...
>>          ldr     d8, [sp, #...]
>>          ...
>>          ret
>> 
>> even though that should be ok (even without interpreting SVE instructions).
>> 
>> On the other hand, any read or write of a callee-saved register is suspicious
>> if it isn't saved earlier or isn't restored later.
>> 
>> In other words, it seems like this information should be context-dependent,
>> or used in a context-dependent way.  Whether a particular register matters
>> depends on whether the register might still contain the caller's data.
>> 
>
> We do something similar for non-memory ops:
>   - In the aarch64_ginsn_unhandled () codepath, if the destination is of 
> interest (REG_SP, REG_FP), synthesize a GINSN_TYPE_OTHER with the 
> appropriate destination register if no ginsn has been generated.
>   - The SCFI machinery checks if this instruction affects SCFI correctness.
>   - If it does, only then the insn is issued a complaint for and brought 
> to attention.
>
> What you suggest is take a similar approach for memory operations too. 
> I think it makes sense.  It needs some work now to accommodate this, but 
> I think we can re-evaluate after some basic handling for Z registers is 
> in place ? I plan to work on adding handling for Z registers after this 
> series is merged. (I have renamed an old testcase involving Z registers 
> to "scfi-unsupported-2.s" to keep track of the currently unsupported 
> cases to be worked on in near future, so I dont lose track of this..).

Yeah, leaving it till later sounds ok.  But I don't think this should
depend on recognising Z loads and stores.  It should just depend on
processing Z registers in the operand lists, and recognising that the
low 64 bits of Z8-Z15 are the same as D8-D15.

In other words, I imagined the set-up would be:

(1) the operand list should tell us whether a register is referenced

(2) recognising 8-byte+ loads and stores, plus support arithmetic,
    lets us recognise instructions that would function as a save or
    restore (and at what offset)

(3) dataflow analysis based on (2) tells us, for a given instruction,
    which registers might have caller data

(4) A reference to possible caller data triggers a warning
    (references detected by (1), caller data by (3))

Is that roughly how it works?

Thanks,
Richard
  
Indu Bhagat July 11, 2024, 7:07 p.m. UTC | #4
On 7/11/24 06:15, Richard Sandiford wrote:
> Indu Bhagat <indu.bhagat@oracle.com> writes:
>> On 7/1/24 12:49, Richard Sandiford wrote:
>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>> +{
>>>> +  enum aarch64_operand_class opnd_class;
>>>> +  unsigned int dw2reg_num = 0;
>>>> +
>>>> +  opnd_class = aarch64_get_operand_class (opnd->type);
>>>> +
>>>> +  switch (opnd_class)
>>>> +    {
>>>> +    case AARCH64_OPND_CLASS_FP_REG:
>>>> +      dw2reg_num = opnd->reg.regno + 64;
>>>> +      break;
>>>> +    case AARCH64_OPND_CLASS_SVE_REGLIST:
>>>> +      dw2reg_num = opnd->reglist.first_regno + 64;
>>>> +      break;
>>>> +    case AARCH64_OPND_CLASS_MODIFIED_REG:
>>>> +    case AARCH64_OPND_CLASS_INT_REG:
>>>> +    case AARCH64_OPND_CLASS_ADDRESS:
>>>> +      /* Use a dummy register value in case of WZR, else this will be an
>>>> +	 incorrect dependency on REG_SP.  */
>>>> +      if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>>>> +	dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>>>> +      else
>>>> +	/* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>>>> +	   DWARF register number is the same as AArch64 register number.  */
>>>> +	dw2reg_num = opnd->reg.regno;
>>>> +      break;
>>>
>>> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
>>> instead.  AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>>>
>>
>> Made the correction for AARCH64_OPND_CLASS_ADDRESS.
>>
>> But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is
>> still correct in opnd->reg.regno, IIUC.  It seems to me that the only
>> information available in the opnd->shifter is how the register is
>> modified by additional work (shift, multiply etc.); This information is
>> not used by SCFI:
>>     - an add/sub with two source register and destination REG_SP/ REG_FP
>> makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does
>> not hurt SCFI correctness.
>>     - Cant think of other operations where the shift amount will affect
>> SCFI correctness..
>>
>> So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at
>> opnd->shifter." of the review comment.
> 
> It's more about type correctness.  "shifter" is the data associated with
> AARCH64_OPND_CLASS_MODIFIED_REG and "reg" is the data associated with
> AARCH64_OPND_CLASS_INT_REG etc.  I think it's mostly a coincidence
> that the "reg" and "shifter" alternatives of the union put the register
> at the same byte offset from the start of the structure.
> 

The shifter struct is out of the union in struct aarch64_opnd_info.

>>>> +    default:
>>>> +      as_bad ("Unexpected value in ginsn_dw2_regnum");
>>>> +      break;
>>>> +    }
>>>> +
>>>> +  return dw2reg_num;
>>>> +}
>>>> +
>>>> +/* Generate ginsn for addsub instructions with immediate opnd.  */
>>>> +
>>>> +static ginsnS *
>>>> +aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
>>>> +{
>>>> +  ginsnS *ginsn = NULL;
>>>> +  bool add_p, sub_p;
>>>> +  offsetT src_imm = 0;
>>>> +  unsigned int dst_reg, opnd_reg;
>>>> +  aarch64_opnd_info *dst, *opnd;
>>>> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
>>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>>> +			 enum ginsn_dst_type, unsigned int, offsetT);
>>>> +
>>>> +  aarch64_inst *base = &inst.base;
>>>> +  const aarch64_opcode *opcode = base->opcode;
>>>> +
>>>> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>>> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>>> +  gas_assert (add_p || sub_p);
>>>> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>>> +
>>>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>>>> +  dst = &base->operands[0];
>>>> +  opnd = &base->operands[1];
>>>> +
>>>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>>>> +
>>>> +  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
>>>> +    src_imm = inst.reloc.exp.X_add_number;
>>>> +  /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
>>>> +     and handle via aarch64_ginsn_unhandled () code path.  */
>>>> +  else if (inst.reloc.type != BFD_RELOC_UNUSED)
>>>> +    return ginsn;
>>>> +  /* FIXME - verify the understanding and remove assert.  */
>>>> +  else
>>>> +    gas_assert (0);
>>>> +
>>>> +  opnd_reg = ginsn_dw2_regnum (opnd, true);
>>>> +
>>>> +  ginsn = ginsn_func (insn_end_sym, true,
>>>> +		      GINSN_SRC_REG, opnd_reg, 0,
>>>> +		      GINSN_SRC_IMM, 0, src_imm,
>>>> +		      GINSN_DST_REG, dst_reg, 0);
>>>> +  ginsn_set_where (ginsn);
>>>> +
>>>> +  return ginsn;
>>>> +}
>>>> +
>>>> +/* Generate ginsn for addsub instructions with reg opnd.  */
>>>> +
>>>> +static ginsnS *
>>>> +aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
>>>> +{
>>>> +  ginsnS *ginsn = NULL;
>>>> +  bool add_p, sub_p;
>>>> +  unsigned int dst_reg, src1_reg, src2_reg;
>>>> +  aarch64_opnd_info *dst, *src1, *src2;
>>>> +  ginsnS *(*ginsn_func) (const symbolS *, bool,
>>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>>> +			 enum ginsn_src_type, unsigned int, offsetT,
>>>> +			 enum ginsn_dst_type, unsigned int, offsetT);
>>>> +
>>>> +  aarch64_inst *base = &inst.base;
>>>> +  const aarch64_opcode *opcode = base->opcode;
>>>> +
>>>> +  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
>>>> +  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
>>>> +  gas_assert (add_p || sub_p);
>>>> +  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
>>>> +
>>>> +  gas_assert (aarch64_num_of_operands (opcode) == 3);
>>>> +  dst = &base->operands[0];
>>>> +  src1 = &base->operands[1];
>>>> +  src2 = &base->operands[2];
>>>> +
>>>> +  dst_reg = ginsn_dw2_regnum (dst, true);
>>>> +  src1_reg = ginsn_dw2_regnum (src1, true);
>>>> +  src2_reg = ginsn_dw2_regnum (src2, false);
>>>> +
>>>> +  ginsn = ginsn_func (insn_end_sym, true,
>>>> +		      GINSN_SRC_REG, src1_reg, 0,
>>>> +		      GINSN_SRC_REG, src2_reg, 0,
>>>> +		      GINSN_DST_REG, dst_reg, 0);
>>>> +  ginsn_set_where (ginsn);
>>>
>>> It looks like this ignores any shift that is applied to src2_reg.
>>>
>>
>> Yes.  An add/sub operation with two source registers makes REG_SP/REG_FP
>> untraceable (if dest is REG_SP/REG_FP), so any further information
>> carried forward in the ginsn is of little use for SCFI.
>>
>> For a usecase apart from SCFI, yes, this may amount to loss of vital
>> information. I will add a TBD_GINSN_INFO_LOSS comment.
> 
> If SCFI doesn't handle add/sub of two registers, then do we still
> need this code for correctness?  I would have expected SCFI to handle
> unrecognised writes to SP in a conservative way, even if there is no
> ginsn type defined for the instruction that sets SP.
> 

Correct, we dont need the two register ADD/SUB for SCFI correctness. A 
placeholder insn like GINSN_TYPE_OTHER emitted via the 
aarch64_ginsn_unhandled () code path should also be sufficient for SCFI.

>>>> +      if (opnd->type == AARCH64_OPND_Rd_SP)
>>>> +	{
>>>> +	  dw2_regnum = ginsn_dw2_regnum (opnd, true);
>>>> +	  if (dw2_regnum == REG_SP)
>>>> +	    skip_p = true;
>>>> +	}
>>>> +      break;
>>>> +
>>>> +    default:
>>>> +      break;
>>>> +    }
>>>> +
>>>> +  return skip_p;
>>>> +}
>>>> +
>>>> +#define AARCH64_GINSN_UNHANDLED_NONE        0
>>>> +#define AARCH64_GINSN_UNHANDLED_DEST_REG    1
>>>> +#define AARCH64_GINSN_UNHANDLED_CFG         2
>>>> +#define AARCH64_GINSN_UNHANDLED_STACKOP     3
>>>> +#define AARCH64_GINSN_UNHANDLED_UNEXPECTED  4
>>>> +
>>>> +/* Check the input insn for its impact on the correctness of the synthesized
>>>> +   CFI.  Returns an error code to the caller.  */
>>>> +
>>>> +static int
>>>> +aarch64_ginsn_unhandled (void)
>>>> +{
>>>> +  int err = AARCH64_GINSN_UNHANDLED_NONE;
>>>> +  aarch64_inst *base = &inst.base;
>>>> +  const aarch64_opcode *opcode = base->opcode;
>>>> +  aarch64_opnd_info *dest = &base->operands[0];
>>>> +  int num_opnds = aarch64_num_of_operands (opcode);
>>>> +  aarch64_opnd_info *addr;
>>>> +  unsigned int dw2_regnum;
>>>> +  unsigned int addr_reg;
>>>> +  aarch64_opnd_info *opnd = NULL;
>>>> +  unsigned int opnd_reg;
>>>> +  bool sp_allowed_p = false;
>>>> +
>>>> +  /* All change of flow instructions are important for SCFI.  */
>>>> +  if (opcode->iclass == condbranch
>>>> +      || opcode->iclass == compbranch
>>>> +      || opcode->iclass == testbranch
>>>> +      || opcode->iclass == branch_imm
>>>> +      || opcode->iclass == branch_reg)
>>>> +    err = AARCH64_GINSN_UNHANDLED_CFG;
>>>> +  /* Also, any memory instructions that may involve an update to the stack
>>>> +     pointer or save/restore of callee-saved registers must not be skipped.
>>>> +     Note that, some iclasses cannot be used to push or pop stack because of
>>>> +     disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
>>>> +     loadlit, ldstnapair_offs.  FIXME double-check.
>>>> +     Also, these iclasses do not seem to be amenable to being used for
>>>> +     save/restore ops either.  FIXME double-check.  */
>>>> +  else if (opcode->iclass == ldstpair_off
>>>> +	   || opcode->iclass == ldstpair_indexed
>>>> +	   || opcode->iclass == ldst_imm9
>>>> +	   || opcode->iclass == ldst_imm10
>>>> +	   || opcode->iclass == ldst_pos
>>>> +  /* STR Zn are especially complicated as they do not store in the same byte
>>>> +     order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
>>>> +     whereas STR Zn stores as a stream of bytes (LSB first).  FIXME Simply punt
>>>> +     on the big-endian and little-endian SVE PCS case for now.  */
>>>> +	   || opcode->iclass == sve_misc)
>>>> +    {
>>>> +      opnd = &base->operands[0];
>>>> +      addr = &base->operands[num_opnds - 1];
>>>> +      addr_reg = ginsn_dw2_regnum (addr, true);
>>>> +      opnd_reg = ginsn_dw2_regnum (opnd, false);
>>>> +      /* For all skipped memory operations, check if an update to REG_SP or
>>>> +	 REG_FP is involved.  */
>>>> +      if ((addr_reg == REG_SP || addr_reg == REG_FP)
>>>> +	  && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
>>>> +	      || aarch64_scfi_callee_saved_p (opnd_reg)))
>>>> +
>>>> +	err = AARCH64_GINSN_UNHANDLED_STACKOP;
>>>
>>> The way I'd imagined this working is that we'd use two-directional data
>>> flow to record which callee-saved registers are "protected" at which
>>> instructions.  That is, for saves we'd walk the cfg forward from the
>>> entry point, recording which registers have been saved earlier in the walk
>>> (and being conservatively correct for cycles).  And for restores we'd
>>> walk the cfg backwards from the exit points, recording which registers
>>> are restored later in the walk.  If a register is both "saved ealier" and
>>> "restored later" for a given instruction, it wouldn't matter what the
>>> instruction does with that register.
>>>
>>> (For infinite loops we would pretend that all registers are restored later.)
>>>
>>> It seems like instead, we'd generate a warning for:
>>>
>>>           ...
>>>           str     d8, [sp, #...]
>>>           ...
>>>           ld1d    z8.b, p0/z, [sp, #...]
>>>           ...
>>>           ldr     d8, [sp, #...]
>>>           ...
>>>           ret
>>>
>>> even though that should be ok (even without interpreting SVE instructions).
>>>
>>> On the other hand, any read or write of a callee-saved register is suspicious
>>> if it isn't saved earlier or isn't restored later.
>>>
>>> In other words, it seems like this information should be context-dependent,
>>> or used in a context-dependent way.  Whether a particular register matters
>>> depends on whether the register might still contain the caller's data.
>>>
>>
>> We do something similar for non-memory ops:
>>    - In the aarch64_ginsn_unhandled () codepath, if the destination is of
>> interest (REG_SP, REG_FP), synthesize a GINSN_TYPE_OTHER with the
>> appropriate destination register if no ginsn has been generated.
>>    - The SCFI machinery checks if this instruction affects SCFI correctness.
>>    - If it does, only then the insn is issued a complaint for and brought
>> to attention.
>>
>> What you suggest is take a similar approach for memory operations too.
>> I think it makes sense.  It needs some work now to accommodate this, but
>> I think we can re-evaluate after some basic handling for Z registers is
>> in place ? I plan to work on adding handling for Z registers after this
>> series is merged. (I have renamed an old testcase involving Z registers
>> to "scfi-unsupported-2.s" to keep track of the currently unsupported
>> cases to be worked on in near future, so I dont lose track of this..).
> 
> Yeah, leaving it till later sounds ok.  But I don't think this should
> depend on recognising Z loads and stores.  It should just depend on
> processing Z registers in the operand lists, and recognising that the
> low 64 bits of Z8-Z15 are the same as D8-D15.
> 

Yes it is orthogonal recognizing Z loads and stores.  I just meant that 
once we recognize Z loads and stores, the utility of such a workflow 
(i.e., do not error out on unrecognised load/stores conservatively as 
they may not be necessary for SCFI correctness at all) is reduced as 
less code blocks will trigger that.

> In other words, I imagined the set-up would be:
> 
> (1) the operand list should tell us whether a register is referenced
> 
> (2) recognising 8-byte+ loads and stores, plus support arithmetic,
>      lets us recognise instructions that would function as a save or
>      restore (and at what offset)
> 
> (3) dataflow analysis based on (2) tells us, for a given instruction,
>      which registers might have caller data
> 
> (4) A reference to possible caller data triggers a warning
>      (references detected by (1), caller data by (3))
> 
> Is that roughly how it works?
> 

Roughly yes. I need to hook a few more things in (3) for the additional 
warning.
  
Richard Sandiford July 11, 2024, 8:10 p.m. UTC | #5
Indu Bhagat <indu.bhagat@oracle.com> writes:
> On 7/11/24 06:15, Richard Sandiford wrote:
>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>> On 7/1/24 12:49, Richard Sandiford wrote:
>>>> Indu Bhagat <indu.bhagat@oracle.com> writes:
>>>>> +{
>>>>> +  enum aarch64_operand_class opnd_class;
>>>>> +  unsigned int dw2reg_num = 0;
>>>>> +
>>>>> +  opnd_class = aarch64_get_operand_class (opnd->type);
>>>>> +
>>>>> +  switch (opnd_class)
>>>>> +    {
>>>>> +    case AARCH64_OPND_CLASS_FP_REG:
>>>>> +      dw2reg_num = opnd->reg.regno + 64;
>>>>> +      break;
>>>>> +    case AARCH64_OPND_CLASS_SVE_REGLIST:
>>>>> +      dw2reg_num = opnd->reglist.first_regno + 64;
>>>>> +      break;
>>>>> +    case AARCH64_OPND_CLASS_MODIFIED_REG:
>>>>> +    case AARCH64_OPND_CLASS_INT_REG:
>>>>> +    case AARCH64_OPND_CLASS_ADDRESS:
>>>>> +      /* Use a dummy register value in case of WZR, else this will be an
>>>>> +	 incorrect dependency on REG_SP.  */
>>>>> +      if (!sp_allowed_p && opnd->reg.regno == REG_SP)
>>>>> +	dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
>>>>> +      else
>>>>> +	/* For GPRs of our interest (callee-saved regs, SP, FP, LR),
>>>>> +	   DWARF register number is the same as AArch64 register number.  */
>>>>> +	dw2reg_num = opnd->reg.regno;
>>>>> +      break;
>>>>
>>>> I think the AARCH64_OPND_CLASS_ADDRESS case should look at opnd->addr
>>>> instead.  AARCH64_OPND_CLASS_MODIFIED_REG should look at opnd->shifter.
>>>>
>>>
>>> Made the correction for AARCH64_OPND_CLASS_ADDRESS.
>>>
>>> But for AARCH64_OPND_CLASS_MODIFIED_REG, the register information is
>>> still correct in opnd->reg.regno, IIUC.  It seems to me that the only
>>> information available in the opnd->shifter is how the register is
>>> modified by additional work (shift, multiply etc.); This information is
>>> not used by SCFI:
>>>     - an add/sub with two source register and destination REG_SP/ REG_FP
>>> makes REG_SP/ REG_FP untraceable. So ignoring the shift amount etc does
>>> not hurt SCFI correctness.
>>>     - Cant think of other operations where the shift amount will affect
>>> SCFI correctness..
>>>
>>> So I am not sure of the "AARCH64_OPND_CLASS_MODIFIED_REG should look at
>>> opnd->shifter." of the review comment.
>> 
>> It's more about type correctness.  "shifter" is the data associated with
>> AARCH64_OPND_CLASS_MODIFIED_REG and "reg" is the data associated with
>> AARCH64_OPND_CLASS_INT_REG etc.  I think it's mostly a coincidence
>> that the "reg" and "shifter" alternatives of the union put the register
>> at the same byte offset from the start of the structure.
>> 
>
> The shifter struct is out of the union in struct aarch64_opnd_info.

Oops, yes, I shouldn't have relied on memory.  Sorry for the noise.

Richard
  

Patch

diff --git a/gas/config/tc-aarch64-ginsn.c b/gas/config/tc-aarch64-ginsn.c
new file mode 100644
index 00000000000..dbee8df88b1
--- /dev/null
+++ b/gas/config/tc-aarch64-ginsn.c
@@ -0,0 +1,797 @@ 
+/* tc-aarch64-ginsn.c -- Ginsn generation for the AArch64 ISA
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+/* This file contains the implementation of the ginsn creation for aarch64
+   instructions.  Most functions will read the aarch64_instruction inst
+   object, but none should need to modify it.  */
+
+#ifdef OBJ_ELF
+
+/* DWARF register number for R1.  Used as dummy value when WZR.  */
+#define GINSN_DW2_REGNUM_R1_DUMMY 1
+
+/* Return whether the given register number is a callee-saved register for
+   SCFI purposes.
+
+   Apart from the callee-saved GPRs, SCFI always tracks SP, FP and LR
+   additionally.  As for the FP/Advanced SIMD registers, v8-v15 are
+   callee-saved.  */
+
+bool
+aarch64_scfi_callee_saved_p (unsigned int dw2reg_num)
+{
+  /* PS: Ensure SCFI_MAX_REG_ID is the max DWARF register number to cover
+     all the registers here.  */
+  if (dw2reg_num == REG_SP /* x31.  */
+      || dw2reg_num == REG_FP /* x29.  */
+      || dw2reg_num == REG_LR /* x30.  */
+      || (dw2reg_num >= 19 && dw2reg_num <= 28) /* x19 - x28.  */
+      || (dw2reg_num >= 72 && dw2reg_num <= 79) /* v8 - v15.  */)
+    return true;
+
+  return false;
+}
+
+/* Get the DWARF register number for the given OPND.
+   Whether 31 is used to encode WZR or SP is specified via SP_ALLOWED_P.
+
+   The caller must decide the value of SP_ALLOWED_P based on the instruction
+   encoding.  */
+
+static unsigned int
+ginsn_dw2_regnum (aarch64_opnd_info *opnd, bool sp_allowed_p)
+{
+  enum aarch64_operand_class opnd_class;
+  unsigned int dw2reg_num = 0;
+
+  opnd_class = aarch64_get_operand_class (opnd->type);
+
+  switch (opnd_class)
+    {
+    case AARCH64_OPND_CLASS_FP_REG:
+      dw2reg_num = opnd->reg.regno + 64;
+      break;
+    case AARCH64_OPND_CLASS_SVE_REGLIST:
+      dw2reg_num = opnd->reglist.first_regno + 64;
+      break;
+    case AARCH64_OPND_CLASS_MODIFIED_REG:
+    case AARCH64_OPND_CLASS_INT_REG:
+    case AARCH64_OPND_CLASS_ADDRESS:
+      /* Use a dummy register value in case of WZR, else this will be an
+	 incorrect dependency on REG_SP.  */
+      if (!sp_allowed_p && opnd->reg.regno == REG_SP)
+	dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
+      else
+	/* For GPRs of our interest (callee-saved regs, SP, FP, LR),
+	   DWARF register number is the same as AArch64 register number.  */
+	dw2reg_num = opnd->reg.regno;
+      break;
+    case AARCH64_OPND_CLASS_SYSTEM:
+      /* For prfm etc., where a opnd->type AARCH64_OPND_PRFOP is seen.  */
+      dw2reg_num = GINSN_DW2_REGNUM_R1_DUMMY;
+      break;
+    default:
+      as_bad ("Unexpected value in ginsn_dw2_regnum");
+      break;
+    }
+
+  return dw2reg_num;
+}
+
+/* Generate ginsn for addsub instructions with immediate opnd.  */
+
+static ginsnS *
+aarch64_ginsn_addsub_imm (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn = NULL;
+  bool add_p, sub_p;
+  offsetT src_imm = 0;
+  unsigned int dst_reg, opnd_reg;
+  aarch64_opnd_info *dst, *opnd;
+  ginsnS *(*ginsn_func) (const symbolS *, bool,
+			 enum ginsn_src_type, unsigned int, offsetT,
+			 enum ginsn_src_type, unsigned int, offsetT,
+			 enum ginsn_dst_type, unsigned int, offsetT);
+
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
+  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
+  gas_assert (add_p || sub_p);
+  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
+
+  gas_assert (aarch64_num_of_operands (opcode) == 3);
+  dst = &base->operands[0];
+  opnd = &base->operands[1];
+
+  dst_reg = ginsn_dw2_regnum (dst, true);
+
+  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
+    src_imm = inst.reloc.exp.X_add_number;
+  /* For any other relocation type, e.g., in add reg, reg, symbol, skip now
+     and handle via aarch64_ginsn_unhandled () code path.  */
+  else if (inst.reloc.type != BFD_RELOC_UNUSED)
+    return ginsn;
+  /* FIXME - verify the understanding and remove assert.  */
+  else
+    gas_assert (0);
+
+  opnd_reg = ginsn_dw2_regnum (opnd, true);
+
+  ginsn = ginsn_func (insn_end_sym, true,
+		      GINSN_SRC_REG, opnd_reg, 0,
+		      GINSN_SRC_IMM, 0, src_imm,
+		      GINSN_DST_REG, dst_reg, 0);
+  ginsn_set_where (ginsn);
+
+  return ginsn;
+}
+
+/* Generate ginsn for addsub instructions with reg opnd.  */
+
+static ginsnS *
+aarch64_ginsn_addsub_reg (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn = NULL;
+  bool add_p, sub_p;
+  unsigned int dst_reg, src1_reg, src2_reg;
+  aarch64_opnd_info *dst, *src1, *src2;
+  ginsnS *(*ginsn_func) (const symbolS *, bool,
+			 enum ginsn_src_type, unsigned int, offsetT,
+			 enum ginsn_src_type, unsigned int, offsetT,
+			 enum ginsn_dst_type, unsigned int, offsetT);
+
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  add_p = aarch64_opcode_subclass_p (opcode, F_ARITH_ADD);
+  sub_p = aarch64_opcode_subclass_p (opcode, F_ARITH_SUB);
+  gas_assert (add_p || sub_p);
+  ginsn_func = add_p ? ginsn_new_add : ginsn_new_sub;
+
+  gas_assert (aarch64_num_of_operands (opcode) == 3);
+  dst = &base->operands[0];
+  src1 = &base->operands[1];
+  src2 = &base->operands[2];
+
+  dst_reg = ginsn_dw2_regnum (dst, true);
+  src1_reg = ginsn_dw2_regnum (src1, true);
+  src2_reg = ginsn_dw2_regnum (src2, false);
+
+  ginsn = ginsn_func (insn_end_sym, true,
+		      GINSN_SRC_REG, src1_reg, 0,
+		      GINSN_SRC_REG, src2_reg, 0,
+		      GINSN_DST_REG, dst_reg, 0);
+  ginsn_set_where (ginsn);
+
+  return ginsn;
+}
+
+/* Generate ginsn for the load pair and store pair instructions.  */
+
+static ginsnS *
+aarch64_ginsn_ldstp (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn = NULL;
+  ginsnS *ginsn_ind = NULL;
+  ginsnS *ginsn_mem1 = NULL;
+  ginsnS *ginsn_mem2 = NULL;
+  unsigned int opnd_reg, addr_reg;
+  offsetT offset, mem_offset;
+  unsigned int width = 8;
+  bool store_p = false;
+
+  aarch64_opnd_info *opnd1, *opnd2, *addr;
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  /* This function is for handling ldp / stp ops only.  */
+  gas_assert (opcode->iclass == ldstpair_indexed
+	      || opcode->iclass == ldstpair_off);
+  gas_assert (aarch64_num_of_operands (opcode) == 3);
+
+  opnd1 = &base->operands[0];
+  opnd2 = &base->operands[1];
+  addr = &base->operands[2];
+  store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
+
+  addr_reg = ginsn_dw2_regnum (addr, true);
+  gas_assert (!addr->addr.offset.is_reg);
+  mem_offset = addr->addr.offset.imm;
+
+  /* ldstp may load or store two 32-bit words or two 64-bit doublewords.  */
+  if (opnd1->qualifier == AARCH64_OPND_QLF_W
+      || opnd1->qualifier == AARCH64_OPND_QLF_S_S)
+    width = 4;
+
+  /* Handle address calculation.  */
+  if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
+    {
+      /* Pre-indexed store, e.g., stp x29, x30, [sp, -128]!
+	 Pre-indexed addressing is like offset addressing, except that
+	 the base pointer is updated as a result of the instruction.
+
+	 Post-indexed store, e.g., stp     x29, x30, [sp],128
+	 Post-index addressing is useful for popping off the stack.  The
+	 instruction loads the value from the location pointed at by the stack
+	 pointer, and then moves the stack pointer on to the next full location
+	 in the stack.  */
+      ginsn_ind = ginsn_new_add (insn_end_sym, false,
+				 GINSN_SRC_REG, addr_reg, 0,
+				 GINSN_SRC_IMM, 0, mem_offset,
+				 GINSN_DST_REG, addr_reg, 0);
+      ginsn_set_where (ginsn_ind);
+    }
+
+  /* Save / restore of WZR is not of interest for SCFI.  However, the address
+     processing component may have updated the stack pointer.  At least, emit
+     that ginsn and return.  PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
+     now;  Check explicitly the regno for WZR.  Also note,
+     TBD_GINSN_GEN_NOT_SCFI.  */
+  if (opnd1->reg.regno == REG_SP /* WZR.  */)
+    return ginsn_ind;
+
+  /* With post-index addressing, the value is loaded from the
+     address in the base pointer, and then the pointer is updated.
+     With pre-index addressing, the addr computation has already
+     been explicitly done.  */
+  offset = mem_offset;
+  if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
+    offset = 0;
+
+  if (opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
+    {
+      width = 16;
+      if (target_big_endian)
+	offset += 8;
+    }
+
+  opnd_reg = ginsn_dw2_regnum (opnd1, false);
+  if (store_p)
+    {
+      ginsn_mem1 = ginsn_new_store (insn_end_sym, false,
+				    GINSN_SRC_REG, opnd_reg,
+				    GINSN_DST_INDIRECT, addr_reg, offset);
+      ginsn_set_where (ginsn_mem1);
+
+      opnd_reg = ginsn_dw2_regnum (opnd2, false);
+      ginsn_mem2 = ginsn_new_store (insn_end_sym, false,
+				    GINSN_SRC_REG, opnd_reg,
+				    GINSN_DST_INDIRECT, addr_reg,
+				    offset + width);
+      ginsn_set_where (ginsn_mem2);
+    }
+  else
+    {
+      opnd_reg = ginsn_dw2_regnum (opnd1, false);
+      ginsn_mem1 = ginsn_new_load (insn_end_sym, false,
+				   GINSN_SRC_INDIRECT, addr_reg, offset,
+				   GINSN_DST_REG, opnd_reg);
+      ginsn_set_where (ginsn_mem1);
+
+      opnd_reg = ginsn_dw2_regnum (opnd2, false);
+      ginsn_mem2 = ginsn_new_load (insn_end_sym, false,
+				   GINSN_SRC_INDIRECT, addr_reg, offset + width,
+				   GINSN_DST_REG, opnd_reg);
+      ginsn_set_where (ginsn_mem2);
+    }
+
+  /* Link the list of ginsns created.  */
+  if (addr->addr.preind && addr->addr.writeback)
+    gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem1));
+
+  gas_assert (!ginsn_link_next (ginsn_mem1, ginsn_mem2));
+
+  if (addr->addr.postind && addr->addr.writeback)
+    gas_assert (!ginsn_link_next (ginsn_mem2, ginsn_ind));
+
+  /* Make note of the first instruction in the list.  */
+  ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem1;
+  return ginsn;
+}
+
+/* Generate ginsn for load and store instructions.  */
+
+static ginsnS *
+aarch64_ginsn_ldstr (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn = NULL;
+  ginsnS *ginsn_ind = NULL;
+  ginsnS *ginsn_mem = NULL;
+  unsigned int opnd_reg, addr_reg;
+  offsetT offset, mem_offset;
+  bool store_p = false;
+
+  aarch64_opnd_info *opnd1, *addr;
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  /* This function is for handling ldr, str ops only.  */
+  gas_assert (opcode->iclass == ldst_imm9 || opcode->iclass == ldst_pos);
+  gas_assert (aarch64_num_of_operands (opcode) == 2);
+
+  opnd1 = &base->operands[0];
+  addr = &base->operands[1];
+  store_p = ((opcode->flags & F_SUBCLASS) == F_LDST_STORE);
+
+  addr_reg = ginsn_dw2_regnum (addr, true);
+
+  /* STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}].
+     LDR <Xt>, [<Xn|SP>], #<simm>.  */
+  opnd_reg = ginsn_dw2_regnum (opnd1, false);
+
+  if (aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
+    mem_offset = inst.reloc.exp.X_add_number;
+  else
+    {
+      gas_assert (!addr->addr.offset.is_reg);
+      mem_offset = addr->addr.offset.imm;
+    }
+
+  /* Handle address calculation.  */
+  if ((addr->addr.preind || addr->addr.postind) && addr->addr.writeback)
+    {
+      ginsn_ind = ginsn_new_add (insn_end_sym, false,
+				 GINSN_SRC_REG, addr_reg, 0,
+				 GINSN_SRC_IMM, 0, mem_offset,
+				 GINSN_DST_REG, addr_reg, 0);
+      ginsn_set_where (ginsn_ind);
+    }
+
+  /* Save / restore of WZR is not of interest for SCFI.  However, the address
+     processing component may have updated the stack pointer.  At least, emit
+     that ginsn and return.  PS: opnd_reg will be GINSN_DW2_REGNUM_R1_DUMMY by
+     now;  Check explicitly the regno for WZR.  Also note,
+     TBD_GINSN_GEN_NOT_SCFI.  */
+  if (opnd1->reg.regno == REG_SP /* WZR.  */)
+    return ginsn_ind;
+
+  /* With post-index addressing, the value is loaded from the
+     address in the base pointer, and then the pointer is updated.
+     With pre-index addressing, the addr computation has already
+     been explicitly done.  */
+  offset = mem_offset;
+  if ((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
+    offset = 0;
+  if (target_big_endian && opnd1->qualifier == AARCH64_OPND_QLF_S_Q)
+    offset += 8;
+
+  if (store_p)
+    ginsn_mem = ginsn_new_store (insn_end_sym, false,
+				 GINSN_SRC_REG, opnd_reg,
+				 GINSN_DST_INDIRECT, addr_reg, offset);
+  else
+    ginsn_mem = ginsn_new_load (insn_end_sym, false,
+				GINSN_SRC_INDIRECT, addr_reg, offset,
+				GINSN_DST_REG, opnd_reg);
+  ginsn_set_where (ginsn_mem);
+
+  if (addr->addr.preind && addr->addr.writeback)
+    gas_assert (!ginsn_link_next (ginsn_ind, ginsn_mem));
+  else if (addr->addr.postind && addr->addr.writeback)
+    gas_assert (!ginsn_link_next (ginsn_mem, ginsn_ind));
+
+  /* Make note of the first instruction in the list.  */
+  ginsn = (addr->addr.preind && addr->addr.writeback) ? ginsn_ind : ginsn_mem;
+
+  return ginsn;
+}
+
+/* Generate ginsn for unconditional branch instructions.  */
+
+static ginsnS *
+aarch64_ginsn_branch_uncond (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn = NULL;
+  const symbolS *src_symbol = NULL;
+  enum ginsn_src_type src_type = GINSN_SRC_UNKNOWN;
+  unsigned int src_reg = 0;
+
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  if (opcode->iclass == branch_imm)
+    {
+      /* b or bl.  opcode 0x14000000 or 0x94000000.  */
+      gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_CALL26
+		  || inst.reloc.type == BFD_RELOC_AARCH64_JUMP26);
+      src_symbol = inst.reloc.exp.X_add_symbol;
+      src_type = GINSN_SRC_SYMBOL;
+    }
+  else if (aarch64_num_of_operands (opcode) >= 1)
+    {
+      gas_assert (opcode->iclass == branch_reg);
+      /* Some insns (e.g., braa, blraa etc.) may have > 1 operands.  For
+	 current SCFI implementation, it suffices however to simply pass
+	 the information about the first source.  Although, strictly speaking,
+	 (if reg) the source info is currently of no material use either.  */
+      src_type = GINSN_SRC_REG;
+      src_reg = ginsn_dw2_regnum (&base->operands[0], false);
+    }
+
+  if (aarch64_opcode_subclass_p (opcode, F_BRANCH_CALL))
+    {
+      gas_assert (src_type != GINSN_SRC_UNKNOWN);
+      ginsn = ginsn_new_call (insn_end_sym, true,
+			      src_type, src_reg, src_symbol);
+    }
+  else if (aarch64_opcode_subclass_p (opcode, F_BRANCH_RET))
+    /* TBD_GINSN_REPRESENTATION_LIMIT.  The following function to create a
+       GINSN_TYPE_RETURN does not allow src info ATM.  */
+    ginsn = ginsn_new_return (insn_end_sym, true);
+  else
+    ginsn = ginsn_new_jump (insn_end_sym, true,
+			    src_type, src_reg, src_symbol);
+
+  ginsn_set_where (ginsn);
+
+  return ginsn;
+}
+
+/* Generate ginsn for conditional branch instructions.  */
+
+static ginsnS *
+aarch64_ginsn_branch_cond (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn;
+  const symbolS *src_symbol;
+  enum ginsn_src_type src_type;
+
+  gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_BRANCH19
+	      || inst.reloc.type == BFD_RELOC_AARCH64_TSTBR14);
+
+  src_symbol = inst.reloc.exp.X_add_symbol;
+  src_type = GINSN_SRC_SYMBOL;
+  ginsn = ginsn_new_jump_cond (insn_end_sym, true, src_type, 0, src_symbol);
+  ginsn_set_where (ginsn);
+
+  return ginsn;
+}
+
+/* Generate ginsn for mov instructions.  */
+
+static ginsnS *
+aarch64_ginsn_mov (const symbolS *insn_end_sym)
+{
+  ginsnS *ginsn = NULL;
+  unsigned int src_reg = 0, dst_reg;
+  aarch64_opnd_info *src, *dst;
+  offsetT src_imm = 0;
+  enum ginsn_src_type src_type;
+
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  gas_assert (aarch64_num_of_operands (opcode) == 2);
+
+  dst = &base->operands[0];
+  src = &base->operands[1];
+
+  dst_reg = ginsn_dw2_regnum (dst, true);
+
+  /* For some mov ops, e.g., movn, movk, or movz, there may optionally be more
+     work than just a simple mov.  Skip handling these mov altogether and let
+     the aarch64_ginsn_unhandled () alert if these insns affect SCFI
+     correctness.  TBD_GINSN_GEN_NOT_SCFI.  */
+  if (src->type == AARCH64_OPND_HALF)
+    return ginsn;
+
+  if (src->type == AARCH64_OPND_IMM_MOV
+      && aarch64_gas_internal_fixup_p () && inst.reloc.exp.X_op == O_constant)
+    {
+      src_imm = inst.reloc.exp.X_add_number;
+      src_type = GINSN_SRC_IMM;
+    }
+  else
+    {
+      /* mov   x27, sp.  */
+      src_reg = ginsn_dw2_regnum (src, true);
+      src_type = GINSN_SRC_REG;
+    }
+
+  ginsn = ginsn_new_mov (insn_end_sym, false,
+			 src_type, src_reg, src_imm,
+			 GINSN_DST_REG, dst_reg, 0);
+  ginsn_set_where (ginsn);
+
+  return ginsn;
+}
+
+/* Check if an instruction is whitelisted.
+
+   An instruction is a candidate for whitelisting if not generating ginsn for
+   it, does not affect SCFI correctness.
+
+   TBD_GINSN_GEN_NOT_SCFI.  This function assumes GINSN_GEN_SCFI is in effect.
+   When other ginsn_gen_mode are added, this will need fixing.  */
+
+static bool
+aarch64_ginsn_safe_to_skip_p (void)
+{
+  bool skip_p = false;
+  aarch64_opnd_info *opnd = NULL;
+  unsigned int dw2_regnum;
+  unsigned int opnd_reg;
+  int num_opnds = 0;
+
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  /* ATM, whitelisting operations with no operands does not seem to be
+     necessary.  */
+  num_opnds = aarch64_num_of_operands (opcode);
+  if (!num_opnds)
+    return skip_p;
+
+  opnd = &base->operands[0];
+
+  switch (opcode->iclass)
+    {
+    case ldst_regoff:
+      /* It is not expected to have reg offset based ld/st ops to be used
+	 for reg save and restore operations.  Warn the user though.  */
+      opnd_reg = ginsn_dw2_regnum (opnd, false);
+      if (aarch64_scfi_callee_saved_p (opnd_reg))
+	{
+	  skip_p = true;
+	  as_warn ("SCFI: ignored probable save/restore op with reg offset");
+	}
+      break;
+
+    case dp_2src:
+      /* irg insn needs to be explicitly whitelisted.  This is because the
+	 dest is Rd_SP, but irg insn affects the tag only.  To detect irg
+	 insn, avoid an opcode-based check, however.  */
+      if (opnd->type == AARCH64_OPND_Rd_SP)
+	{
+	  dw2_regnum = ginsn_dw2_regnum (opnd, true);
+	  if (dw2_regnum == REG_SP)
+	    skip_p = true;
+	}
+      break;
+
+    default:
+      break;
+    }
+
+  return skip_p;
+}
+
+#define AARCH64_GINSN_UNHANDLED_NONE        0
+#define AARCH64_GINSN_UNHANDLED_DEST_REG    1
+#define AARCH64_GINSN_UNHANDLED_CFG         2
+#define AARCH64_GINSN_UNHANDLED_STACKOP     3
+#define AARCH64_GINSN_UNHANDLED_UNEXPECTED  4
+
+/* Check the input insn for its impact on the correctness of the synthesized
+   CFI.  Returns an error code to the caller.  */
+
+static int
+aarch64_ginsn_unhandled (void)
+{
+  int err = AARCH64_GINSN_UNHANDLED_NONE;
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+  aarch64_opnd_info *dest = &base->operands[0];
+  int num_opnds = aarch64_num_of_operands (opcode);
+  aarch64_opnd_info *addr;
+  unsigned int dw2_regnum;
+  unsigned int addr_reg;
+  aarch64_opnd_info *opnd = NULL;
+  unsigned int opnd_reg;
+  bool sp_allowed_p = false;
+
+  /* All change of flow instructions are important for SCFI.  */
+  if (opcode->iclass == condbranch
+      || opcode->iclass == compbranch
+      || opcode->iclass == testbranch
+      || opcode->iclass == branch_imm
+      || opcode->iclass == branch_reg)
+    err = AARCH64_GINSN_UNHANDLED_CFG;
+  /* Also, any memory instructions that may involve an update to the stack
+     pointer or save/restore of callee-saved registers must not be skipped.
+     Note that, some iclasses cannot be used to push or pop stack because of
+     disallowed writeback: ldst_unscaled, ldst_regoff, ldst_unpriv, ldstexcl,
+     loadlit, ldstnapair_offs.  FIXME double-check.
+     Also, these iclasses do not seem to be amenable to being used for
+     save/restore ops either.  FIXME double-check.  */
+  else if (opcode->iclass == ldstpair_off
+	   || opcode->iclass == ldstpair_indexed
+	   || opcode->iclass == ldst_imm9
+	   || opcode->iclass == ldst_imm10
+	   || opcode->iclass == ldst_pos
+  /* STR Zn are especially complicated as they do not store in the same byte
+     order for big-endian: STR Qn stores as a 128-bit integer (MSB first),
+     whereas STR Zn stores as a stream of bytes (LSB first).  FIXME Simply punt
+     on the big-endian and little-endian SVE PCS case for now.  */
+	   || opcode->iclass == sve_misc)
+    {
+      opnd = &base->operands[0];
+      addr = &base->operands[num_opnds - 1];
+      addr_reg = ginsn_dw2_regnum (addr, true);
+      opnd_reg = ginsn_dw2_regnum (opnd, false);
+      /* For all skipped memory operations, check if an update to REG_SP or
+	 REG_FP is involved.  */
+      if ((addr_reg == REG_SP || addr_reg == REG_FP)
+	  && (((addr->addr.postind || addr->addr.preind) && addr->addr.writeback)
+	      || aarch64_scfi_callee_saved_p (opnd_reg)))
+
+	err = AARCH64_GINSN_UNHANDLED_STACKOP;
+    }
+  /* Finally, irrespective of the iclass, check if the missed instructions are
+     affecting REG_SP or REG_FP.  */
+  else if (dest && (dest->type == AARCH64_OPND_Rd
+		    || dest->type == AARCH64_OPND_Rd_SP))
+    {
+      sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
+      dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
+
+      if (dw2_regnum == REG_SP || dw2_regnum == REG_FP)
+	err = AARCH64_GINSN_UNHANDLED_DEST_REG;
+    }
+
+  return err;
+}
+
+/* Generate one or more generic GAS instructions, a.k.a, ginsns for the
+   current machine instruction.
+
+   Returns the head of linked list of ginsn(s) added, if success; Returns NULL
+   if failure.
+
+   The input ginsn_gen_mode GMODE determines the set of minimal necessary
+   ginsns necessary for correctness of any passes applicable for that mode.
+   For supporting the GINSN_GEN_SCFI generation mode, following is the list of
+   machine instructions that must be translated into the corresponding ginsns
+   to ensure correctness of SCFI:
+     - All instructions affecting the two registers that could potentially
+       be used as the base register for CFA tracking.  For SCFI, the base
+       register for CFA tracking is limited to REG_SP and REG_FP only.
+     - All change of flow instructions: conditional and unconditional
+       branches, call and return from functions.
+     - All instructions that can potentially be a register save / restore
+       operations.
+     - All instructions that may update the stack pointer: pre-indexed and
+     post-indexed stack operations with writeback.
+
+   The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
+   To support other generation modes will require work on this target-specific
+   process of creation of ginsns:
+     - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
+       possible starting points.
+     - Also note that ginsn representation may need enhancements.  Specifically,
+       note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
+   */
+
+static ginsnS *
+aarch64_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode)
+{
+  int err = 0;
+  ginsnS *ginsn = NULL;
+  unsigned int dw2_regnum;
+  aarch64_opnd_info *dest = NULL;
+  bool sp_allowed_p = false;
+  aarch64_inst *base = &inst.base;
+  const aarch64_opcode *opcode = base->opcode;
+
+  /* Currently supports generation of selected ginsns, sufficient for
+     the use-case of SCFI only.  To remove this condition will require
+     work on this target-specific process of creation of ginsns.  Some
+     of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
+     examples.  */
+  if (gmode != GINSN_GEN_SCFI)
+    return ginsn;
+
+  switch (opcode->iclass)
+    {
+    case addsub_ext:
+      /* TBD_GINSN_GEN_NOT_SCFI: other insns are not of interest for SCFI.  */
+      if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
+	   || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
+	ginsn = aarch64_ginsn_addsub_reg (insn_end_sym);
+      break;
+
+    case addsub_imm:
+      if (aarch64_opcode_subclass_p (opcode, F_ARITH_MOV))
+	ginsn = aarch64_ginsn_mov (insn_end_sym);
+      else if (aarch64_opcode_subclass_p (opcode, F_ARITH_ADD)
+	       || aarch64_opcode_subclass_p (opcode, F_ARITH_SUB))
+	ginsn = aarch64_ginsn_addsub_imm (insn_end_sym);
+      break;
+
+    case movewide:
+      ginsn = aarch64_ginsn_mov (insn_end_sym);
+      break;
+
+    case ldst_imm9:
+    case ldst_pos:
+      ginsn = aarch64_ginsn_ldstr (insn_end_sym);
+      break;
+
+    case ldstpair_indexed:
+    case ldstpair_off:
+      ginsn = aarch64_ginsn_ldstp (insn_end_sym);
+      break;
+
+    case branch_imm:
+    case branch_reg:
+      ginsn = aarch64_ginsn_branch_uncond (insn_end_sym);
+      break;
+
+    case compbranch:
+      /* Although cbz/cbnz has an additional operand and are functionally
+	 distinct from conditional branches, it is fine to use the same ginsn
+	 type for both from the perspective of SCFI.  */
+    case testbranch:
+    case condbranch:
+      ginsn = aarch64_ginsn_branch_cond (insn_end_sym);
+      break;
+
+    default:
+      /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
+	 GINSN_GEN_SCFI mode.  */
+      break;
+    }
+
+  if (!ginsn && !aarch64_ginsn_safe_to_skip_p ())
+    {
+      /* For all unhandled insns, check that they no not impact SCFI
+	 correctness.  */
+      err = aarch64_ginsn_unhandled ();
+      switch (err)
+	{
+	case AARCH64_GINSN_UNHANDLED_NONE:
+	  break;
+	case AARCH64_GINSN_UNHANDLED_DEST_REG:
+	  /* Not all writes to REG_FP are harmful in context of SCFI.  Simply
+	     generate a GINSN_TYPE_OTHER with destination set to the
+	     appropriate register.  The SCFI machinery will bail out if this
+	     ginsn affects SCFI correctness.  */
+	  dest = &base->operands[0];
+	  sp_allowed_p = (dest->type == AARCH64_OPND_Rd_SP) ? true : false;
+	  dw2_regnum = ginsn_dw2_regnum (dest, sp_allowed_p);
+	  ginsn = ginsn_new_other (insn_end_sym, true,
+				   GINSN_SRC_IMM, 0,
+				   GINSN_SRC_IMM, 0,
+				   GINSN_DST_REG, dw2_regnum);
+	  ginsn_set_where (ginsn);
+	  break;
+	case AARCH64_GINSN_UNHANDLED_CFG:
+	case AARCH64_GINSN_UNHANDLED_STACKOP:
+	  as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"),
+		  opcode->opcode);
+	  break;
+	case AARCH64_GINSN_UNHANDLED_UNEXPECTED:
+	  as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
+		  opcode->opcode);
+	  break;
+	default:
+	  abort ();
+	  break;
+	}
+    }
+
+  return ginsn;
+}
+
+#endif /* OBJ_ELF.  */
+
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5d15ee9fc02..4f4dd404551 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -33,6 +33,7 @@ 
 #include "dw2gencfi.h"
 #include "sframe.h"
 #include "gen-sframe.h"
+#include "scfi.h"
 #endif
 
 #include "dw2gencfi.h"
@@ -8591,6 +8592,10 @@  dump_opcode_operands (const aarch64_opcode *opcode)
 }
 #endif /* DEBUG_AARCH64 */
 
+#ifdef OBJ_ELF
+# include "tc-aarch64-ginsn.c"
+#endif
+
 /* This is the guts of the machine-dependent assembler.  STR points to a
    machine dependent instruction.  This function is supposed to emit
    the frags/bytes it assembles to.  */
@@ -8728,6 +8733,16 @@  md_assemble (char *str)
 	      output_inst (copy);
 	    }
 
+#ifdef OBJ_ELF
+	  if (flag_synth_cfi)
+	    {
+	      ginsnS *ginsn;
+	      ginsn = aarch64_ginsn_new (symbol_temp_new_now (),
+					 frch_ginsn_gen_mode ());
+	      frch_ginsn_data_append (ginsn);
+	    }
+#endif
+
 	  /* Issue non-fatal messages if any.  */
 	  output_operand_error_report (str, true);
 	  return;
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index 1b8badad9fd..4906a6e7000 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -263,6 +263,27 @@  extern void aarch64_after_parse_args (void);
 
 #ifdef OBJ_ELF
 
+#define TARGET_USE_GINSN 1
+/* Allow GAS to synthesize DWARF CFI for hand-written asm.
+   PS: TARGET_USE_CFIPOP is a pre-condition.  */
+#define TARGET_USE_SCFI 1
+/* Identify the maximum DWARF register number of all the registers being
+   tracked for SCFI.  This is the last DWARF register number of the set
+   of SP, FP, and all callee-saved registers.  For Aarch64, this means 79
+   because FP/Advanced SIMD v8-v15 are also callee-saved registers.  */
+# define SCFI_MAX_REG_ID 79
+/* Identify the DWARF register number of the frame-pointer register.  */
+# define REG_FP 29
+/* Identify the DWARF register number of the link register.  */
+# define REG_LR 30
+/* Identify the DWARF register number of the stack-pointer register.  */
+# define REG_SP 31
+
+#define SCFI_INIT_CFA_OFFSET 0
+
+#define SCFI_CALLEE_SAVED_REG_P(dw2reg)  aarch64_scfi_callee_saved_p (dw2reg)
+extern bool aarch64_scfi_callee_saved_p (uint32_t dw2reg_num);
+
 /* Whether SFrame stack trace info is supported.  */
 extern bool aarch64_support_sframe_p (void);
 #define support_sframe_p aarch64_support_sframe_p