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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230037)(1800799021)(82310400023)(36860700010)(35042699019)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 11:37:12.4528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c9a6a75-438c-4094-a5b7-08dc91e67e2a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF0000019D.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB10760 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Hi, This patch fixes the mandatory feature bits in v9.4-a architectures, by enabling FEAT_SVE2p1 for Armv9.4-A architecture by default. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils master? Regards, Srinath. --- gas/testsuite/gas/aarch64/sve2p1-1-bad.d | 2 +- gas/testsuite/gas/aarch64/sve2p1-1.d | 2 +- gas/testsuite/gas/aarch64/sve2p1-2-bad.d | 4 ++++ gas/testsuite/gas/aarch64/sve2p1-2-bad.l | 2 ++ gas/testsuite/gas/aarch64/sve2p1-nosve2.s | 1 + include/opcode/aarch64.h | 3 ++- 6 files changed, 11 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-bad.d create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-bad.l create mode 100644 gas/testsuite/gas/aarch64/sve2p1-nosve2.s diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d b/gas/testsuite/gas/aarch64/sve2p1-1-bad.d index a2ca49ef487..c28cdc76c4c 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.d @@ -1,4 +1,4 @@ #name: Illegal test of SVE2.1 min max instructions. -#as: -march=armv9.4-a +#as: -march=armv9.3-a #source: sve2p1-1.s #error_output: sve2p1-1-bad.l diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d index b93920cd02b..f562985b569 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d @@ -1,5 +1,5 @@ #name: Test of SVE2.1 instructions -#as: -march=armv9.4-a+sve2p1 +#as: -march=armv9.4-a #objdump: -dr [^:]+: file format .* diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-bad.d b/gas/testsuite/gas/aarch64/sve2p1-2-bad.d new file mode 100644 index 00000000000..4d58f4b0bd6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2-bad.d @@ -0,0 +1,4 @@ +#name: Illegal test of SVE2.1 instructions. +#as: -march=armv9.4-a+nosve2 +#source: sve2p1-nosve2.s +#error_output: sve2p1-2-bad.l diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-bad.l b/gas/testsuite/gas/aarch64/sve2p1-2-bad.l new file mode 100644 index 00000000000..1e16026f47c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-2-bad.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `addqv v0.16b,p0,z16.b' diff --git a/gas/testsuite/gas/aarch64/sve2p1-nosve2.s b/gas/testsuite/gas/aarch64/sve2p1-nosve2.s new file mode 100644 index 00000000000..7f457ea26e4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2p1-nosve2.s @@ -0,0 +1 @@ +addqv v0.16b, p0, z16.b diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 8a21611e3ff..7ae30bb456c 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -327,7 +327,8 @@ enum aarch64_feature_bit { #define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X) #define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X) #define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X) -#define AARCH64_ARCH_V9_4A_FEATURES(X) AARCH64_ARCH_V8_9A_FEATURES (X) +#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \ + | AARCH64_FEATBIT (X, SVE2p1)) /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \