diff mbox series

[committed] RISC-V: Updated gas/NEWS and gas/doc/c-riscv.texi for vendor extensions.

Message ID 20240618072508.31403-1-nelson@rivosinc.com
State New
Headers
Series [committed] RISC-V: Updated gas/NEWS and gas/doc/c-riscv.texi for vendor extensions. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm warning Patch is already merged
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 warning Patch is already merged

Commit Message

Nelson Chu June 18, 2024, 7:25 a.m. UTC 
  gas/
	* NEWS: Updated for XCvMem, XCvBi, XCvElw, XSfCease.
	* doc/c-riscv.texi: Minor typo for XCv* extensions.
---
 gas/NEWS             |  5 +++++
 gas/doc/c-riscv.texi | 20 ++++++++++----------
 2 files changed, 15 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 5fb4160b53e..096400d5842 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -31,6 +31,11 @@ 
 
 * Add support for RISC-V Smcsrind/Sscsrind extension with version 1.0.
 
+* Add support for RISC-V CORE-V extensions (XCvMem, XCvBi, XCvElw) with
+  version 1.0.
+
+* Add support for RISC-V SiFive cease extension (XSfCease) with version 1.0.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index e579eeb58c0..ebff7a6acd4 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -740,28 +740,28 @@  extensions supported and provides the location of their
 publicly-released documentation:
 
 @table @r
-@item Xcvmac
-The Xcvmac extension provides instructions for multiply-accumulate operations.
+@item XCvMac
+The XCvMac extension provides instructions for multiply-accumulate operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
-@item Xcvalu
-The Xcvalu extension provides instructions for general ALU operations.
+@item XCvAlu
+The XCvAlu extension provides instructions for general ALU operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
-@item Xcvelw
-The Xcvelw extension provides instructions for event load word operations.
+@item XCvElw
+The XCvElw extension provides instructions for event load word operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
-@item Xcvbi
-The Xcvbi extension provides instructions for branch immediate operations.
+@item XCvBi
+The XCvBi extension provides instructions for branch immediate operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
-@item Xcvmem
-The Xcvmem extension provides instructions for post inc load/store operations.
+@item XCvMem
+The XCvMem extension provides instructions for post inc load/store operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}