diff mbox series

[v4] RISC-V: Add SiFive cease extension v1.0

Message ID 20240618064904.2876390-1-hau.hsu@sifive.com
State New
Headers
Series [v4] RISC-V: Add SiFive cease extension v1.0 |

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Commit Message

Hau Hsu June 18, 2024, 6:49 a.m. UTC 
  Add SiFive cease extension.
This aligns LLVM:
* https://llvm.org/docs/RISCVUsage.html
* https://github.com/llvm/llvm-project/pull/83896

bfd/ChangeLog:

    * bfd/elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'.
    (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
    (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.

gas/ChangeLog:

    * gas/testsuite/gas/riscv/march-help.l: Add 'xsfcease' to the list of supported -march extensions.
    * gas/testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
    * gas/testsuite/gas/riscv/sifive-insns.s: Add assembly and disassembly test for 'sf.cease'.

include/ChangeLog:

    * include/opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask for 'sf.cease'.
    * include/opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'.

opcodes/ChangeLog:

    * opcodes/riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
---
 bfd/elfxx-riscv.c                      | 5 +++++
 gas/doc/c-riscv.texi                   | 5 +++++
 gas/testsuite/gas/riscv/march-help.l   | 1 +
 gas/testsuite/gas/riscv/sifive-insns.d | 1 +
 gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++
 include/opcode/riscv-opc.h             | 3 +++
 include/opcode/riscv.h                 | 1 +
 opcodes/riscv-opc.c                    | 3 +++
 8 files changed, 25 insertions(+)

Comments

Nelson Chu June 18, 2024, 7:27 a.m. UTC | #1 
Committed with minor updates, since you forgot to update the changelog for
gas/doc/c-riscv-texi.

Thanks
Nelson

On Tue, Jun 18, 2024 at 2:50 PM Hau Hsu <hau.hsu@sifive.com> wrote:

> Add SiFive cease extension.
> This aligns LLVM:
> * https://llvm.org/docs/RISCVUsage.html
> * https://github.com/llvm/llvm-project/pull/83896
>
> bfd/ChangeLog:
>
>     * bfd/elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for
> 'xsfcease'.
>     (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
>     (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.
>
> gas/ChangeLog:
>
>     * gas/testsuite/gas/riscv/march-help.l: Add 'xsfcease' to the list of
> supported -march extensions.
>     * gas/testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
>     * gas/testsuite/gas/riscv/sifive-insns.s: Add assembly and disassembly
> test for 'sf.cease'.
>
> include/ChangeLog:
>
>     * include/opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define
> match and mask for 'sf.cease'.
>     * include/opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction
> class for 'xsfcease'.
>
> opcodes/ChangeLog:
>
>     * opcodes/riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
> ---
>  bfd/elfxx-riscv.c                      | 5 +++++
>  gas/doc/c-riscv.texi                   | 5 +++++
>  gas/testsuite/gas/riscv/march-help.l   | 1 +
>  gas/testsuite/gas/riscv/sifive-insns.d | 1 +
>  gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++
>  include/opcode/riscv-opc.h             | 3 +++
>  include/opcode/riscv.h                 | 1 +
>  opcodes/riscv-opc.c                    | 3 +++
>  8 files changed, 25 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 297d565285c..4943ec79d92 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1484,6 +1484,7 @@ static struct riscv_supported_ext
> riscv_supported_vendor_x_ext[] =
>    {"xtheadzvamo",      ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {"xsfvcp",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0},
> +  {"xsfcease",         ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>    {NULL, 0, 0, 0, 0}
>  };
>
> @@ -2732,6 +2733,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
>        return riscv_subset_supports (rps, "xventanacondops");
>      case INSN_CLASS_XSFVCP:
>        return riscv_subset_supports (rps, "xsfvcp");
> +    case INSN_CLASS_XSFCEASE:
> +      return riscv_subset_supports (rps, "xsfcease");
>      default:
>        rps->error_handler
>          (_("internal: unreachable INSN_CLASS_*"));
> @@ -2998,6 +3001,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
>        return "xtheadvector";
>      case INSN_CLASS_XTHEADZVAMO:
>        return "xtheadzvamo";
> +    case INSN_CLASS_XSFCEASE:
> +      return "xsfcease";
>      default:
>        rps->error_handler
>          (_("internal: unreachable INSN_CLASS_*"));
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 61bb7bcdadc..e579eeb58c0 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -850,4 +850,9 @@ VCIX as a low-latency, high-throughput interface to a
> coprocessor.
>
>  It is documented in @url{
> https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf
> }.
>
> +@item XSfCease
> +XSfCease provides an instruction to instigates power-down sequence.
> +
> +It is documented in @url{
> https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
> }.
> +
>  @end table
> diff --git a/gas/testsuite/gas/riscv/march-help.l
> b/gas/testsuite/gas/riscv/march-help.l
> index d2b98383e80..b7f5f763690 100644
> --- a/gas/testsuite/gas/riscv/march-help.l
> +++ b/gas/testsuite/gas/riscv/march-help.l
> @@ -129,3 +129,4 @@ All available -march extensions for RISC-V:
>         xtheadzvamo                             1.0
>         xventanacondops                         1.0
>         xsfvcp                                  1.0
> +       xsfcease                                1.0
> diff --git a/gas/testsuite/gas/riscv/sifive-insns.d
> b/gas/testsuite/gas/riscv/sifive-insns.d
> index f7d63d1bce0..610f62588b3 100644
> --- a/gas/testsuite/gas/riscv/sifive-insns.d
> +++ b/gas/testsuite/gas/riscv/sifive-insns.d
> @@ -35,3 +35,4 @@ Disassembly of section .text:
>  [      ]+[0-9a-f]+:[   ]+fc25c05b[     ]+sf.vc.v.xvw[  ]+0x3,v0,v2,a1
>  [      ]+[0-9a-f]+:[   ]+fc27b05b[     ]+sf.vc.v.ivw[  ]+0x3,v0,v2,15
>  [      ]+[0-9a-f]+:[   ]+fc25d05b[     ]+sf.vc.v.fvw[  ]+0x1,v0,v2,fa1
> +[      ]+[0-9a-f]+:[   ]+30500073[     ]+sf.cease
> diff --git a/gas/testsuite/gas/riscv/sifive-insns.s
> b/gas/testsuite/gas/riscv/sifive-insns.s
> index d593692c5c0..cdf90c1b3ba 100644
> --- a/gas/testsuite/gas/riscv/sifive-insns.s
> +++ b/gas/testsuite/gas/riscv/sifive-insns.s
> @@ -31,3 +31,9 @@
>         sf.vc.v.ivw 0x3, v0, v2, 15
>         sf.vc.v.fvw 0x1, v0, v2, fa1
>         .option pop
> +
> +       # xscease
> +       .option push
> +       .option arch, +xsfcease1p0
> +       sf.cease
> +       .option pop
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 511895eca2b..04712cb6cf7 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -3148,6 +3148,9 @@
>  #define MASK_SF_VC_FVW 0xfa00707f
>  #define MATCH_SF_VC_V_FVW 0xf800505b
>  #define MASK_SF_VC_V_FVW 0xfa00707f
> +/* Vendor-specific (SiFive) cease instruction.  */
> +#define MATCH_SF_CEASE 0x30500073
> +#define MASK_SF_CEASE 0xffffffff
>  /* Unprivileged Counter/Timers CSR addresses.  */
>  #define CSR_CYCLE 0xc00
>  #define CSR_TIME 0xc01
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 33df56d13af..e3870473aaa 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -514,6 +514,7 @@ enum riscv_insn_class
>    INSN_CLASS_XTHEADZVAMO,
>    INSN_CLASS_XVENTANACONDOPS,
>    INSN_CLASS_XSFVCP,
> +  INSN_CLASS_XSFCEASE,
>  };
>
>  /* This structure holds information for a particular instruction.  */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index ff08bd595c0..96732148c33 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -3087,6 +3087,9 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW,
> MASK_SF_VC_FVW, match_opcode, 0 },
>  {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW,
> MASK_SF_VC_V_FVW, match_opcode, 0 },
>
> +/* Vendor-specific (SiFive) cease instruction.  */
> +{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE,
> match_opcode, 0 },
> +
>  /* Terminate the list.  */
>  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>  };
> --
> 2.31.1
>
>
Hau Hsu June 18, 2024, 9:18 a.m. UTC | #2 
Oh sorry. I didn't know there is also a changelog for that.
Thanks!


Hau Hsu




> On Jun 18, 2024, at 3:27 PM, Nelson Chu <nelson@rivosinc.com> wrote:
> 
> Committed with minor updates, since you forgot to update the changelog for gas/doc/c-riscv-texi.
> 
> Thanks
> Nelson
> 
> On Tue, Jun 18, 2024 at 2:50 PM Hau Hsu <hau.hsu@sifive.com <mailto:hau.hsu@sifive.com>> wrote:
>> Add SiFive cease extension.
>> This aligns LLVM:
>> * https://llvm.org/docs/RISCVUsage.html
>> * https://github.com/llvm/llvm-project/pull/83896
>> 
>> bfd/ChangeLog:
>> 
>>     * bfd/elfxx-riscv.c (riscv_supported_vendor_x_ext): Add support for 'xsfcease'.
>>     (riscv_multi_subset_supports): Handle INSN_CLASS_XSFCEASE.
>>     (riscv_multi_subset_supports_ext): Handle INSN_CLASS_XSFCEASE.
>> 
>> gas/ChangeLog:
>> 
>>     * gas/testsuite/gas/riscv/march-help.l: Add 'xsfcease' to the list of supported -march extensions.
>>     * gas/testsuite/gas/riscv/sifive-insns.d: Add test case for 'sf.cease'.
>>     * gas/testsuite/gas/riscv/sifive-insns.s: Add assembly and disassembly test for 'sf.cease'.
>> 
>> include/ChangeLog:
>> 
>>     * include/opcode/riscv-opc.h (MATCH_SF_CEASE, MASK_SF_CEASE): Define match and mask for 'sf.cease'.
>>     * include/opcode/riscv.h (INSN_CLASS_XSFCEASE): Add new instruction class for 'xsfcease'.
>> 
>> opcodes/ChangeLog:
>> 
>>     * opcodes/riscv-opc.c (riscv_opcodes): Add opcode entry for 'sf.cease'.
>> ---
>>  bfd/elfxx-riscv.c                      | 5 +++++
>>  gas/doc/c-riscv.texi                   | 5 +++++
>>  gas/testsuite/gas/riscv/march-help.l   | 1 +
>>  gas/testsuite/gas/riscv/sifive-insns.d | 1 +
>>  gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++
>>  include/opcode/riscv-opc.h             | 3 +++
>>  include/opcode/riscv.h                 | 1 +
>>  opcodes/riscv-opc.c                    | 3 +++
>>  8 files changed, 25 insertions(+)
>> 
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index 297d565285c..4943ec79d92 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1484,6 +1484,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
>>    {"xtheadzvamo",      ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>>    {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>>    {"xsfvcp",           ISA_SPEC_CLASS_DRAFT,   1, 0, 0},
>> +  {"xsfcease",         ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>>    {NULL, 0, 0, 0, 0}
>>  };
>> 
>> @@ -2732,6 +2733,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>>        return riscv_subset_supports (rps, "xventanacondops");
>>      case INSN_CLASS_XSFVCP:
>>        return riscv_subset_supports (rps, "xsfvcp");
>> +    case INSN_CLASS_XSFCEASE:
>> +      return riscv_subset_supports (rps, "xsfcease");
>>      default:
>>        rps->error_handler
>>          (_("internal: unreachable INSN_CLASS_*"));
>> @@ -2998,6 +3001,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
>>        return "xtheadvector";
>>      case INSN_CLASS_XTHEADZVAMO:
>>        return "xtheadzvamo";
>> +    case INSN_CLASS_XSFCEASE:
>> +      return "xsfcease";
>>      default:
>>        rps->error_handler
>>          (_("internal: unreachable INSN_CLASS_*"));
>> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
>> index 61bb7bcdadc..e579eeb58c0 100644
>> --- a/gas/doc/c-riscv.texi
>> +++ b/gas/doc/c-riscv.texi
>> @@ -850,4 +850,9 @@ VCIX as a low-latency, high-throughput interface to a coprocessor.
>> 
>>  It is documented in @url{https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf}.
>> 
>> +@item XSfCease
>> +XSfCease provides an instruction to instigates power-down sequence.
>> +
>> +It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}.
>> +
>>  @end table
>> diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
>> index d2b98383e80..b7f5f763690 100644
>> --- a/gas/testsuite/gas/riscv/march-help.l
>> +++ b/gas/testsuite/gas/riscv/march-help.l
>> @@ -129,3 +129,4 @@ All available -march extensions for RISC-V:
>>         xtheadzvamo                             1.0
>>         xventanacondops                         1.0
>>         xsfvcp                                  1.0
>> +       xsfcease                                1.0
>> diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d
>> index f7d63d1bce0..610f62588b3 100644
>> --- a/gas/testsuite/gas/riscv/sifive-insns.d
>> +++ b/gas/testsuite/gas/riscv/sifive-insns.d
>> @@ -35,3 +35,4 @@ Disassembly of section .text:
>>  [      ]+[0-9a-f]+:[   ]+fc25c05b[     ]+sf.vc.v.xvw[  ]+0x3,v0,v2,a1
>>  [      ]+[0-9a-f]+:[   ]+fc27b05b[     ]+sf.vc.v.ivw[  ]+0x3,v0,v2,15
>>  [      ]+[0-9a-f]+:[   ]+fc25d05b[     ]+sf.vc.v.fvw[  ]+0x1,v0,v2,fa1
>> +[      ]+[0-9a-f]+:[   ]+30500073[     ]+sf.cease
>> diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
>> index d593692c5c0..cdf90c1b3ba 100644
>> --- a/gas/testsuite/gas/riscv/sifive-insns.s
>> +++ b/gas/testsuite/gas/riscv/sifive-insns.s
>> @@ -31,3 +31,9 @@
>>         sf.vc.v.ivw 0x3, v0, v2, 15
>>         sf.vc.v.fvw 0x1, v0, v2, fa1
>>         .option pop
>> +
>> +       # xscease
>> +       .option push
>> +       .option arch, +xsfcease1p0
>> +       sf.cease
>> +       .option pop
>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> index 511895eca2b..04712cb6cf7 100644
>> --- a/include/opcode/riscv-opc.h
>> +++ b/include/opcode/riscv-opc.h
>> @@ -3148,6 +3148,9 @@
>>  #define MASK_SF_VC_FVW 0xfa00707f
>>  #define MATCH_SF_VC_V_FVW 0xf800505b
>>  #define MASK_SF_VC_V_FVW 0xfa00707f
>> +/* Vendor-specific (SiFive) cease instruction.  */
>> +#define MATCH_SF_CEASE 0x30500073
>> +#define MASK_SF_CEASE 0xffffffff
>>  /* Unprivileged Counter/Timers CSR addresses.  */
>>  #define CSR_CYCLE 0xc00
>>  #define CSR_TIME 0xc01
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index 33df56d13af..e3870473aaa 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -514,6 +514,7 @@ enum riscv_insn_class
>>    INSN_CLASS_XTHEADZVAMO,
>>    INSN_CLASS_XVENTANACONDOPS,
>>    INSN_CLASS_XSFVCP,
>> +  INSN_CLASS_XSFCEASE,
>>  };
>> 
>>  /* This structure holds information for a particular instruction.  */
>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> index ff08bd595c0..96732148c33 100644
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -3087,6 +3087,9 @@ const struct riscv_opcode riscv_opcodes[] =
>>  {"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
>>  {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
>> 
>> +/* Vendor-specific (SiFive) cease instruction.  */
>> +{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },
>> +
>>  /* Terminate the list.  */
>>  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>>  };
>> -- 
>> 2.31.1
>>
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 297d565285c..4943ec79d92 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1484,6 +1484,7 @@  static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadzvamo",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xsfvcp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0},
+  {"xsfcease",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2732,6 +2733,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xventanacondops");
     case INSN_CLASS_XSFVCP:
       return riscv_subset_supports (rps, "xsfvcp");
+    case INSN_CLASS_XSFCEASE:
+      return riscv_subset_supports (rps, "xsfcease");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
@@ -2998,6 +3001,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadvector";
     case INSN_CLASS_XTHEADZVAMO:
       return "xtheadzvamo";
+    case INSN_CLASS_XSFCEASE:
+      return "xsfcease";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 61bb7bcdadc..e579eeb58c0 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -850,4 +850,9 @@  VCIX as a low-latency, high-throughput interface to a coprocessor.
 
 It is documented in @url{https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf}.
 
+@item XSfCease
+XSfCease provides an instruction to instigates power-down sequence.
+
+It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}.
+
 @end table
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index d2b98383e80..b7f5f763690 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -129,3 +129,4 @@  All available -march extensions for RISC-V:
 	xtheadzvamo                             1.0
 	xventanacondops                         1.0
 	xsfvcp                                  1.0
+	xsfcease                                1.0
diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d
index f7d63d1bce0..610f62588b3 100644
--- a/gas/testsuite/gas/riscv/sifive-insns.d
+++ b/gas/testsuite/gas/riscv/sifive-insns.d
@@ -35,3 +35,4 @@  Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+fc25c05b[ 	]+sf.vc.v.xvw[ 	]+0x3,v0,v2,a1
 [ 	]+[0-9a-f]+:[ 	]+fc27b05b[ 	]+sf.vc.v.ivw[ 	]+0x3,v0,v2,15
 [ 	]+[0-9a-f]+:[ 	]+fc25d05b[ 	]+sf.vc.v.fvw[ 	]+0x1,v0,v2,fa1
+[ 	]+[0-9a-f]+:[ 	]+30500073[ 	]+sf.cease
diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
index d593692c5c0..cdf90c1b3ba 100644
--- a/gas/testsuite/gas/riscv/sifive-insns.s
+++ b/gas/testsuite/gas/riscv/sifive-insns.s
@@ -31,3 +31,9 @@ 
 	sf.vc.v.ivw 0x3, v0, v2, 15
 	sf.vc.v.fvw 0x1, v0, v2, fa1
 	.option pop
+
+	# xscease
+	.option push
+	.option arch, +xsfcease1p0
+	sf.cease
+	.option pop
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 511895eca2b..04712cb6cf7 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3148,6 +3148,9 @@ 
 #define MASK_SF_VC_FVW 0xfa00707f
 #define MATCH_SF_VC_V_FVW 0xf800505b
 #define MASK_SF_VC_V_FVW 0xfa00707f
+/* Vendor-specific (SiFive) cease instruction.  */
+#define MATCH_SF_CEASE 0x30500073
+#define MASK_SF_CEASE 0xffffffff
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 33df56d13af..e3870473aaa 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -514,6 +514,7 @@  enum riscv_insn_class
   INSN_CLASS_XTHEADZVAMO,
   INSN_CLASS_XVENTANACONDOPS,
   INSN_CLASS_XSFVCP,
+  INSN_CLASS_XSFCEASE,
 };
 
 /* This structure holds information for a particular instruction.  */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ff08bd595c0..96732148c33 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3087,6 +3087,9 @@  const struct riscv_opcode riscv_opcodes[] =
 {"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
 {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
 
+/* Vendor-specific (SiFive) cease instruction.  */
+{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };