diff mbox series

[1/2,v2] Support APX CCMP and CTEST

Message ID 20240614110846.1928726-1-lili.cui@intel.com
State New
Headers
Series [1/2,v2] Support APX CCMP and CTEST |

Commit Message

Cui, Lili June 14, 2024, 11:08 a.m. UTC 
  Changes in 1/3 V2
1. Refine function check_Scc_OszcOperations.
2. Report bad for illegal commas.
3. Move check_Scc_OszcOperations forward in parse_insn.
4. Support pseudo-prefix case.
5. Clean up ins->vex.v in the right place.
6. Add more test cases.

Thanks,
Lili.


CCMP and CTEST are two new sets of instructions for conditional CMP
and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST
in the instruction mnemonic, e.g.:

ccmp<cc> { dfv=sf , cf , of } %eax, %ecx

also add

{evex} cmp/test %eax, %ecx

as an alias for ccmpt.

For the encoder part, add function check_Scc_OszcOperation to parse
'{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode,
and adjust base_opcode to its normal meaning in install_template.

For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags
suffixes.

gas/ChangeLog:

        * config/tc-i386.c (OSZC_CF): New.
        (OSZC_ZF): Ditto.
        (OSZC_SF): Ditto.
        (OSZC_OF): Ditto.
        (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice.
        (check_Scc_OszcOperations): Handle SCC OSZC flags.
        (install_template): Add scc and oszc_flags.
        (build_apx_evex_prefix): Encode SCC and oszc flags bits.
        (parse_insn): Handle check_Scc_OszcOperations.
        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case.
        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
        * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto.
        * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto.

opcodes/ChangeLog:

        * i386-dis-evex-reg.h: Add ccmp and ctest.
        * i386-dis-evex.h: Ditto.
        * i386-dis.c (struct instr_info): add scc.
        (struct dis386): Add new micro 'NE','SC' and'DF'.
        (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn.
        (putop): Handle %NE, %SC and %DF.
        * i386-opc.h (SCC): New.
        * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test.
        * i386-mnem.h: Regenerated.
        * i386-tbl.h: Ditto.
---
 gas/config/tc-i386.c                          | 148 +++++++++++-
 .../gas/i386/x86-64-apx-ccmp-ctest-intel.d    | 222 ++++++++++++++++++
 .../gas/i386/x86-64-apx-ccmp-ctest-inval.l    |  17 ++
 .../gas/i386/x86-64-apx-ccmp-ctest-inval.s    |  20 ++
 .../gas/i386/x86-64-apx-ccmp-ctest.d          | 222 ++++++++++++++++++
 .../gas/i386/x86-64-apx-ccmp-ctest.s          | 218 +++++++++++++++++
 .../gas/i386/x86-64-apx-evex-promoted-bad.d   |  22 +-
 .../gas/i386/x86-64-apx-evex-promoted-bad.s   |  12 +-
 gas/testsuite/gas/i386/x86-64.exp             |   3 +
 opcodes/i386-dis-evex-reg.h                   |  11 +-
 opcodes/i386-dis-evex.h                       |  12 +-
 opcodes/i386-dis.c                            |  92 ++++++--
 opcodes/i386-opc.h                            |   2 +
 opcodes/i386-opc.tbl                          |  19 ++
 14 files changed, 978 insertions(+), 42 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.s

Comments

Jan Beulich June 17, 2024, 1:13 p.m. UTC | #1 
On 14.06.2024 13:08, Cui, Lili wrote:
> @@ -1929,6 +1939,111 @@ static INLINE bool need_evex_encoding (const insn_template *t)
>  #define CPU_FLAGS_PERFECT_MATCH \
>    (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
>  
> +static INLINE bool set_oszc_flags (unsigned int oszc_shift)
> +{
> +  if (i.oszc_flags & oszc_shift)
> +    {
> +      as_bad (_("same oszc flag used twice"));
> +      return false;
> +    }
> +  i.oszc_flags |= oszc_shift;
> +  return true;
> +}
> +
> +/* Handle SCC OSZC flags.  */
> +
> +static int
> +check_Scc_OszcOperations (const char *l)
> +{
> +  const char *suffix_string = l;
> +
> +  while (is_space_char (*suffix_string))
> +    suffix_string++;

As mentioned in a earlier reply, I'd prefer if these were - consistent
with what we have elsewhere - if(), not while(). But I won't insist.

> +  /* If {oszc flags} is absent, just return.  */
> +  if (*suffix_string != '{')
> +    return 0;
> +
> +  /* Skip '{'.  */
> +  suffix_string++;
> +
> +  /* Parse 'dfv='.  */
> +  while (is_space_char (*suffix_string))
> +    suffix_string++;
> +
> +  if (strncasecmp (suffix_string, "dfv", 3) == 0)
> +    suffix_string += 3;
> +  else
> +    {
> +      as_bad (_("Unrecognized pseudo-suffix"));

Please can diagnostics start without capital letters (unless it's some
form of acronym)? See elsewhere, including what you have right here in
set_oszc_flags().

> +      return -1;
> +    }
> +
> +  while (is_space_char (*suffix_string))
> +    suffix_string++;
> +
> +  if (*suffix_string == '=')
> +    suffix_string++;
> +  else
> +    {
> +      as_bad (_("Unrecognized pseudo-suffix"));
> +      return -1;
> +    }
> +
> +  /* Parse 'of, sf, zf, cf}'.  */
> +  while (*suffix_string)
> +    {
> +      while (is_space_char (*suffix_string))
> +	suffix_string++;
> +
> +      /* Return for '{dfv=}'.  */
> +      if (*suffix_string == '}')
> +	return ++suffix_string - l;

Such an increment is pretty pointless, and hopefully the compiler will
translate it to

	return suffix_string + 1 - l;

anyway. Better to also write it like this right away.

> +      if (strncasecmp (suffix_string, "of", 2) == 0)
> +	{
> +	  if (!set_oszc_flags (OSZC_OF))
> +	    return -1;
> +	}
> +      else if (strncasecmp (suffix_string, "sf", 2) == 0)
> +	{
> +	  if (!set_oszc_flags (OSZC_SF))
> +	    return -1;
> +	}
> +      else if (strncasecmp (suffix_string, "zf", 2) == 0)
> +	{
> +	  if (!set_oszc_flags (OSZC_ZF))
> +	    return -1;
> +	}
> +      else if (strncasecmp (suffix_string, "cf", 2) == 0)
> +	{
> +	  if (!set_oszc_flags (OSZC_CF))
> +	    return -1;
> +	}
> +      else
> +	{
> +	  as_bad (_("Unrecognized oszc flags or illegal `,' in pseudo-suffix"));
> +	  return -1;
> +	}
> +
> +      suffix_string += 2;
> +
> +      while (is_space_char (*suffix_string))
> +	suffix_string++;
> +
> +      if (*suffix_string == '}')
> +	return ++suffix_string - l;
> +
> +      if (*suffix_string != ',')
> +	break;
> +
> +      suffix_string ++;

Please omit the stray / inconsistent blank.

> +    }
> +
> +  as_bad (_("Illegal `}' or `,' in pseudo-suffix"));

When you come here, isn't it that you _did not_ find the expected } or ,?
IOW s/Illegal/missing"?

> @@ -7453,6 +7598,7 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only)
>  	    }
>  	}
>      }
> +
>    /* Any other comma loses.  */
>    if (*l == ',')
>      {

Stray / leftover change?

> @@ -10398,6 +10427,23 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
>  		*ins->obufp++ = *q;
>  	      break;
>  	    }
> +	  else if (l == 1 && last[0] == 'S')
> +	    {
> +	      /* Add scc suffix.  */
> +	      oappend (ins, scc_suffix[ins->vex.scc]);
> +
> +	      /* For SCC insns, the ND bit is required to be set to 0.  */
> +	      if (ins->vex.nd)
> +		oappend (ins, "(bad)");
> +
> +	      /* These bits have been consumed and should be cleared or restored
> +		 to default values.  */
> +	      ins->vex.v = 1;
> +	      ins->vex.nf = false;
> +	      ins->vex.mask_register_specifier = 0;

Unlike here ...

> @@ -10532,6 +10582,18 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
>  		  evex_printed = true;
>  		}
>  	    }
> +	  else if (l == 1 && last[0] == 'D')
> +	    {
> +	      /* Get oszc flags value from register_specifier.  */
> +	      int oszc_value = ~ins->vex.register_specifier & 0xf;
> +
> +	      /* Add {dfv=of, sf, zf, cf} flags.  */
> +	      oappend (ins, oszc_flags[oszc_value]);
> +
> +	      /* These bits have been consumed and should be cleared or restored
> +		 to default values.  */
> +	      ins->vex.register_specifier = 0;

... it now only "cleared" anymore here.

All adjustment requests are largely cosmetic, so with them carried out
feel free to commit.

Jan
Cui, Lili June 18, 2024, 2:57 a.m. UTC | #2 
> On 14.06.2024 13:08, Cui, Lili wrote:
> > @@ -1929,6 +1939,111 @@ static INLINE bool need_evex_encoding (const
> > insn_template *t)  #define CPU_FLAGS_PERFECT_MATCH \
> >    (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
> >
> > +static INLINE bool set_oszc_flags (unsigned int oszc_shift) {
> > +  if (i.oszc_flags & oszc_shift)
> > +    {
> > +      as_bad (_("same oszc flag used twice"));
> > +      return false;
> > +    }
> > +  i.oszc_flags |= oszc_shift;
> > +  return true;
> > +}
> > +
> > +/* Handle SCC OSZC flags.  */
> > +
> > +static int
> > +check_Scc_OszcOperations (const char *l) {
> > +  const char *suffix_string = l;
> > +
> > +  while (is_space_char (*suffix_string))
> > +    suffix_string++;
> 
> As mentioned in a earlier reply, I'd prefer if these were - consistent with what we
> have elsewhere - if(), not while(). But I won't insist.
> 

I prefer to use while (), thanks.

> > +  /* If {oszc flags} is absent, just return.  */  if (*suffix_string
> > + != '{')
> > +    return 0;
> > +
> > +  /* Skip '{'.  */
> > +  suffix_string++;
> > +
> > +  /* Parse 'dfv='.  */
> > +  while (is_space_char (*suffix_string))
> > +    suffix_string++;
> > +
> > +  if (strncasecmp (suffix_string, "dfv", 3) == 0)
> > +    suffix_string += 3;
> > +  else
> > +    {
> > +      as_bad (_("Unrecognized pseudo-suffix"));
> 
> Please can diagnostics start without capital letters (unless it's some form of
> acronym)? See elsewhere, including what you have right here in set_oszc_flags().
> 

Done.

> > +      return -1;
> > +    }
> > +
> > +  while (is_space_char (*suffix_string))
> > +    suffix_string++;
> > +
> > +  if (*suffix_string == '=')
> > +    suffix_string++;
> > +  else
> > +    {
> > +      as_bad (_("Unrecognized pseudo-suffix"));
> > +      return -1;
> > +    }
> > +
> > +  /* Parse 'of, sf, zf, cf}'.  */
> > +  while (*suffix_string)
> > +    {
> > +      while (is_space_char (*suffix_string))
> > +	suffix_string++;
> > +
> > +      /* Return for '{dfv=}'.  */
> > +      if (*suffix_string == '}')
> > +	return ++suffix_string - l;
> 
> Such an increment is pretty pointless, and hopefully the compiler will translate it
> to
> 
> 	return suffix_string + 1 - l;
> 
> anyway. Better to also write it like this right away.
>

Done.
 
> > +      if (strncasecmp (suffix_string, "of", 2) == 0)
> > +	{
> > +	  if (!set_oszc_flags (OSZC_OF))
> > +	    return -1;
> > +	}
> > +      else if (strncasecmp (suffix_string, "sf", 2) == 0)
> > +	{
> > +	  if (!set_oszc_flags (OSZC_SF))
> > +	    return -1;
> > +	}
> > +      else if (strncasecmp (suffix_string, "zf", 2) == 0)
> > +	{
> > +	  if (!set_oszc_flags (OSZC_ZF))
> > +	    return -1;
> > +	}
> > +      else if (strncasecmp (suffix_string, "cf", 2) == 0)
> > +	{
> > +	  if (!set_oszc_flags (OSZC_CF))
> > +	    return -1;
> > +	}
> > +      else
> > +	{
> > +	  as_bad (_("Unrecognized oszc flags or illegal `,' in pseudo-suffix"));
> > +	  return -1;
> > +	}
> > +
> > +      suffix_string += 2;
> > +
> > +      while (is_space_char (*suffix_string))
> > +	suffix_string++;
> > +
> > +      if (*suffix_string == '}')
> > +	return ++suffix_string - l;
> > +
> > +      if (*suffix_string != ',')
> > +	break;
> > +
> > +      suffix_string ++;
> 
> Please omit the stray / inconsistent blank.
> 

Done.

> > +    }
> > +
> > +  as_bad (_("Illegal `}' or `,' in pseudo-suffix"));
> 
> When you come here, isn't it that you _did not_ find the expected } or ,?
> IOW s/Illegal/missing"?
> 

Done.

> > @@ -7453,6 +7598,7 @@ parse_insn (const char *line, char *mnemonic, bool
> prefix_only)
> >  	    }
> >  	}
> >      }
> > +
> >    /* Any other comma loses.  */
> >    if (*l == ',')
> >      {
> 
> Stray / leftover change?
> 

Done.

> > @@ -10398,6 +10427,23 @@ putop (instr_info *ins, const char *in_template,
> int sizeflag)
> >  		*ins->obufp++ = *q;
> >  	      break;
> >  	    }
> > +	  else if (l == 1 && last[0] == 'S')
> > +	    {
> > +	      /* Add scc suffix.  */
> > +	      oappend (ins, scc_suffix[ins->vex.scc]);
> > +
> > +	      /* For SCC insns, the ND bit is required to be set to 0.  */
> > +	      if (ins->vex.nd)
> > +		oappend (ins, "(bad)");
> > +
> > +	      /* These bits have been consumed and should be cleared or restored
> > +		 to default values.  */
> > +	      ins->vex.v = 1;
> > +	      ins->vex.nf = false;
> > +	      ins->vex.mask_register_specifier = 0;
> 
> Unlike here ...
> 
> > @@ -10532,6 +10582,18 @@ putop (instr_info *ins, const char *in_template,
> int sizeflag)
> >  		  evex_printed = true;
> >  		}
> >  	    }
> > +	  else if (l == 1 && last[0] == 'D')
> > +	    {
> > +	      /* Get oszc flags value from register_specifier.  */
> > +	      int oszc_value = ~ins->vex.register_specifier & 0xf;
> > +
> > +	      /* Add {dfv=of, sf, zf, cf} flags.  */
> > +	      oappend (ins, oszc_flags[oszc_value]);
> > +
> > +	      /* These bits have been consumed and should be cleared or restored
> > +		 to default values.  */
> > +	      ins->vex.register_specifier = 0;
> 
> ... it now only "cleared" anymore here.
> 

Done.

> All adjustment requests are largely cosmetic, so with them carried out feel free
> to commit.
> 
Committed.

Thanks,
Lili.
Jan Beulich June 18, 2024, 11:33 a.m. UTC | #3 
On 14.06.2024 13:08, Cui, Lili wrote:
> @@ -341,10 +342,28 @@ cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8
>  cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
>  cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +cmp, 0x380a, APX_F, D|W|CheckOperandSize|EVexMap4|Scc|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +cmp, 0x830a/7, APX_F, Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +cmp, 0x800a/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +
> +<scc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
> +         s:8, ns:9, t:a, f:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
> +
> +ccmp<scc>, 0x380<scc:opc>, APX_F, D|W|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +ccmp<scc>, 0x830<scc:opc>/7, APX_F, Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +ccmp<scc>, 0x800<scc:opc>/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  
>  test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
>  test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +test, 0x840a, 0, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +
> +ctest<scc>, 0x840<scc:opc>, APX_F, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +ctest<scc>, 0xf60<scc:opc>/0, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +ctest<scc>, 0xf60<scc:opc>/1, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

Spotting this only now: What's this last line for? This template is impossible
to come into use, unless I'm missing something. I understand there is this
secondary encoding (also for the legacy-encoded counterpart), but something
that's impossible to be used better wouldn't be there. The more that in the
resulting table we're talking of almost 30 extra entries.

Jan
Cui, Lili June 19, 2024, 2:43 a.m. UTC | #4 
> On 14.06.2024 13:08, Cui, Lili wrote:
> > @@ -341,10 +342,28 @@ cmp, 0x38, 0,
> > D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64,
> Reg8
> > cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S,
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex }  cmp, 0x3c, 0, W|No_sSuf, {
> > Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }  cmp,
> 0x80/7, 0,
> > W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +cmp, 0x380a, APX_F,
> D|W|CheckOperandSize|EVexMap4|Scc|Modrm|No_sSuf,
> > +{ Reg8|Reg16|Reg32|Reg64,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } cmp, 0x830a/7,
> APX_F,
> > +Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S,
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex } cmp, 0x800a/7, APX_F,
> > +W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +
> > +<scc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5,
> be:6, na:6, nbe:7, a:7, +
> > +         s:8, ns:9, t:a, f:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e,
> > +nle:f, g:f>
> > +
> > +ccmp<scc>, 0x380<scc:opc>, APX_F,
> > +D|W|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +} ccmp<scc>, 0x830<scc:opc>/7, APX_F,
> > +Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S,
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex } ccmp<scc>,
> > +0x800<scc:opc>/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +}
> >
> >  test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S,
> > Acc|Byte|Word|Dword|Qword }  test, 0xf6/0, 0,
> > W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +test, 0x840a, 0,
> D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +} test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +}
> > +
> > +ctest<scc>, 0x840<scc:opc>, APX_F,
> > +D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +} ctest<scc>, 0xf60<scc:opc>/0, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf,
> > +{ Imm8|Imm16|Imm32|Imm32S,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } ctest<scc>,
> > +0xf60<scc:opc>/1, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, {
> > +Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +}
> 
> Spotting this only now: What's this last line for? This template is impossible to
> come into use, unless I'm missing something. I understand there is this
> secondary encoding (also for the legacy-encoded counterpart), but something
> that's impossible to be used better wouldn't be there. The more that in the
> resulting table we're talking of almost 30 extra entries.
> 
Ok, thanks, I will create a patch to remove the second one.

Lili.
diff mbox series

Patch

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index e0c69640e01..04460552d48 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -416,6 +416,16 @@  struct _i386_insn
     /* Compressed disp8*N attribute.  */
     unsigned int memshift;
 
+    /* SCC = EVEX.[SC3,SC2,SC1,SC0].  */
+    unsigned int scc;
+
+    /* Store 4 bits of EVEX.[OF,SF,ZF,CF].  */
+#define OSZC_CF 1
+#define OSZC_ZF 2
+#define OSZC_SF 4
+#define OSZC_OF 8
+    unsigned int oszc_flags;
+
     /* Prefer load or store in encoding.  */
     enum
       {
@@ -1929,6 +1939,111 @@  static INLINE bool need_evex_encoding (const insn_template *t)
 #define CPU_FLAGS_PERFECT_MATCH \
   (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
 
+static INLINE bool set_oszc_flags (unsigned int oszc_shift)
+{
+  if (i.oszc_flags & oszc_shift)
+    {
+      as_bad (_("same oszc flag used twice"));
+      return false;
+    }
+  i.oszc_flags |= oszc_shift;
+  return true;
+}
+
+/* Handle SCC OSZC flags.  */
+
+static int
+check_Scc_OszcOperations (const char *l)
+{
+  const char *suffix_string = l;
+
+  while (is_space_char (*suffix_string))
+    suffix_string++;
+
+  /* If {oszc flags} is absent, just return.  */
+  if (*suffix_string != '{')
+    return 0;
+
+  /* Skip '{'.  */
+  suffix_string++;
+
+  /* Parse 'dfv='.  */
+  while (is_space_char (*suffix_string))
+    suffix_string++;
+
+  if (strncasecmp (suffix_string, "dfv", 3) == 0)
+    suffix_string += 3;
+  else
+    {
+      as_bad (_("Unrecognized pseudo-suffix"));
+      return -1;
+    }
+
+  while (is_space_char (*suffix_string))
+    suffix_string++;
+
+  if (*suffix_string == '=')
+    suffix_string++;
+  else
+    {
+      as_bad (_("Unrecognized pseudo-suffix"));
+      return -1;
+    }
+
+  /* Parse 'of, sf, zf, cf}'.  */
+  while (*suffix_string)
+    {
+      while (is_space_char (*suffix_string))
+	suffix_string++;
+
+      /* Return for '{dfv=}'.  */
+      if (*suffix_string == '}')
+	return ++suffix_string - l;
+
+      if (strncasecmp (suffix_string, "of", 2) == 0)
+	{
+	  if (!set_oszc_flags (OSZC_OF))
+	    return -1;
+	}
+      else if (strncasecmp (suffix_string, "sf", 2) == 0)
+	{
+	  if (!set_oszc_flags (OSZC_SF))
+	    return -1;
+	}
+      else if (strncasecmp (suffix_string, "zf", 2) == 0)
+	{
+	  if (!set_oszc_flags (OSZC_ZF))
+	    return -1;
+	}
+      else if (strncasecmp (suffix_string, "cf", 2) == 0)
+	{
+	  if (!set_oszc_flags (OSZC_CF))
+	    return -1;
+	}
+      else
+	{
+	  as_bad (_("Unrecognized oszc flags or illegal `,' in pseudo-suffix"));
+	  return -1;
+	}
+
+      suffix_string += 2;
+
+      while (is_space_char (*suffix_string))
+	suffix_string++;
+
+      if (*suffix_string == '}')
+	return ++suffix_string - l;
+
+      if (*suffix_string != ',')
+	break;
+
+      suffix_string ++;
+    }
+
+  as_bad (_("Illegal `}' or `,' in pseudo-suffix"));
+  return -1;
+}
+
 /* Return CPU flags match bits. */
 
 static int
@@ -3793,10 +3908,19 @@  install_template (const insn_template *t)
 	}
     }
 
+  /* For CCMP and CTEST the template has EVEX.SCC in base_opcode. Move it out of
+     there, to then adjust base_opcode to obtain its normal meaning.  */
+  if (i.tm.opcode_modifier.operandconstraint == SCC)
+    {
+      /* Get EVEX.SCC value from the lower 4 bits of base_opcode.  */
+      i.scc = i.tm.base_opcode & 0xf;
+      i.tm.base_opcode >>= 8;
+    }
+
   /* Note that for pseudo prefixes this produces a length of 1. But for them
      the length isn't interesting at all.  */
   for (l = 1; l < 4; ++l)
-    if (!(t->base_opcode >> (8 * l)))
+    if (!(i.tm.base_opcode >> (8 * l)))
       break;
 
   i.opcode_length = l;
@@ -4290,6 +4414,18 @@  build_apx_evex_prefix (void)
       || i.tm.opcode_modifier.operandconstraint == ZERO_UPPER)
     i.vex.bytes[3] |= 0x10;
 
+  /* Encode SCC and oszc flags bits.  */
+  if (i.tm.opcode_modifier.operandconstraint == SCC)
+    {
+      /* The default value of vvvv is 1111 and needs to be cleared.  */
+      i.vex.bytes[2] &= ~0x78;
+      i.vex.bytes[2] |= (i.oszc_flags << 3);
+      /* ND and aaa bits shold be 0.  */
+      know (!(i.vex.bytes[3] & 0x17));
+      /* The default value of V' is 1 and needs to be cleared.  */
+      i.vex.bytes[3] = (i.vex.bytes[3] & ~0x08) | i.scc;
+    }
+
   /* Encode the NF bit.  */
   if (i.has_nf)
     i.vex.bytes[3] |= 0x04;
@@ -7428,6 +7564,15 @@  parse_insn (const char *line, char *mnemonic, bool prefix_only)
 	}
     }
 
+  /* Handle SCC OSZC flgs.  */
+  if (current_templates.start->opcode_modifier.operandconstraint == SCC)
+    {
+      int length = check_Scc_OszcOperations (l);
+      if (length < 0)
+	return NULL;
+      l += length;
+    }
+
   if (current_templates.start->opcode_modifier.jump == JUMP
       || current_templates.start->opcode_modifier.jump == JUMP_BYTE)
     {
@@ -7453,6 +7598,7 @@  parse_insn (const char *line, char *mnemonic, bool prefix_only)
 	    }
 	}
     }
+
   /* Any other comma loses.  */
   if (*l == ',')
     {
diff --git a/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d
new file mode 100644
index 00000000000..c9ab3e959bf
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d
@@ -0,0 +1,222 @@ 
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 APX_F CCMP and CTEST insns (Intel disassembly)
+#source: x86-64-apx-ccmp-ctest.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 0d 02 39 f8[ 	]+ccmpb \{dfv=cf\} ax,r15w
+[ 	]*[a-f0-9]+:[ 	]*62 54 0c 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=cf\} r15d,DWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4d 02 83 ff 7b[ 	]+ccmpb \{dfv=of, cf\} r15w,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 80 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, cf\} BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 6d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 ec 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 fc 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, zf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 74 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, zf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 f4 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, zf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 e4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 64 02 3a 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf\} r8b,BYTE PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 5c 02 38 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, zf, cf\} BYTE PTR \[r8\+rax\*4\+0x123\],r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 55 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, zf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 54 02 38 c2[ 	]+ccmpb \{dfv=of, zf\} dl,r8b
+[ 	]*[a-f0-9]+:[ 	]*62 74 44 02 39 fa[ 	]+ccmpb \{dfv=of\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 45 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of\} r15w,WORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 80 f8 7b[ 	]+ccmpb \{dfv=sf, cf\} r8b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 2c 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 ac 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\} r15,QWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 3c 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf, cf\} r15d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 3d 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf, cf\} r15w,WORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 34 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf\} r15d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 34 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 d4 a4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=sf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 39 ff[ 	]+ccmpb \{dfv=sf\} r15,r15
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf\} r15,QWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 83 ff 7b[ 	]+ccmpb \{dfv=zf, cf\} r15,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 1d 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 94 02 83 ff 7b[ 	]+ccmpb \{dfv=zf\} r15,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 15 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=zf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 15 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 05 02 83 ff 7b[ 	]+ccmpb \{dfv=\} r15w,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 04 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 04 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=\} r15d,DWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 83 f8 7b[ 	]+ccmpo \{dfv=of\} r16,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 83 f9 7b[ 	]+ccmpno \{dfv=of\} r17,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 83 fa 7b[ 	]+ccmpb \{dfv=of\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 83 fb 7b[ 	]+ccmpae \{dfv=of\} r19,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 83 fc 7b[ 	]+ccmpe \{dfv=of\} r20,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 83 fd 7b[ 	]+ccmpne \{dfv=of\} r21,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 83 fe 7b[ 	]+ccmpbe \{dfv=of\} r22,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 83 ff 7b[ 	]+ccmpa \{dfv=of\} r23,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 83 f8 7b[ 	]+ccmps \{dfv=of\} r24,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 83 f9 7b[ 	]+ccmpns \{dfv=of\} r25,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a 83 fa 7b[ 	]+ccmpt \{dfv=of\} r26,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b 83 fb 7b[ 	]+ccmpf \{dfv=of\} r27,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c 83 fc 7b[ 	]+ccmpl \{dfv=of\} r28,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d 83 fd 7b[ 	]+ccmpge \{dfv=of\} r29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e 83 fe 7b[ 	]+ccmple \{dfv=of\} r30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f 83 ff 7b[ 	]+ccmpg \{dfv=of\} r31,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=cf\} r15,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 0d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 f6 84 80 23 01 00 00 7b[ 	]+ctestb \{dfv=of, cf\} BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 cc 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 ec 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=of, sf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=of, sf, zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 75 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=of, sf, zf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 64 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=of, sf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 65 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, sf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=of, zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 5d 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 54 02 f6 84 80 23 01 00 00 7b[ 	]+ctestb \{dfv=of, zf\} BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 d4 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 84 84 80 23 01 00 00[ 	]+ctestb \{dfv=of\} BYTE PTR \[r8\+rax\*4\+0x123\],r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=sf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 2c 02 85 fa[ 	]+ctestb \{dfv=sf, cf\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 3c 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=sf, zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 74 3c 02 84 c2[ 	]+ctestb \{dfv=sf, zf, cf\} dl,r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 35 02 f7 c7 7b 00[ 	]+ctestb \{dfv=sf, zf\} r15w,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 b4 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=sf, zf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 24 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=sf\} r15d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 25 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=sf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 f6 c0 7b[ 	]+ctestb \{dfv=zf, cf\} r8b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=zf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 14 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=zf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 94 02 85 ff[ 	]+ctestb \{dfv=zf\} r15,r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 84 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 05 02 85 f8[ 	]+ctestb \{dfv=\} ax,r15w
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 f7 c0 7b 00 00 00[ 	]+ctesto \{dfv=of\} r16,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 f7 c1 7b 00 00 00[ 	]+ctestno \{dfv=of\} r17,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 f7 c2 7b 00 00 00[ 	]+ctestb \{dfv=of\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 f7 c3 7b 00 00 00[ 	]+ctestae \{dfv=of\} r19,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 f7 c4 7b 00 00 00[ 	]+cteste \{dfv=of\} r20,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 f7 c5 7b 00 00 00[ 	]+ctestne \{dfv=of\} r21,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 f7 c6 7b 00 00 00[ 	]+ctestbe \{dfv=of\} r22,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 f7 c7 7b 00 00 00[ 	]+ctesta \{dfv=of\} r23,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 f7 c0 7b 00 00 00[ 	]+ctests \{dfv=of\} r24,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 f7 c1 7b 00 00 00[ 	]+ctestns \{dfv=of\} r25,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=of\} r26,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b f7 c3 7b 00 00 00[ 	]+ctestf \{dfv=of\} r27,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c f7 c4 7b 00 00 00[ 	]+ctestl \{dfv=of\} r28,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d f7 c5 7b 00 00 00[ 	]+ctestge \{dfv=of\} r29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e f7 c6 7b 00 00 00[ 	]+ctestle \{dfv=of\} r30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} r31,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} r31,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 39 fa[ 	]+ccmpt \{dfv=\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a 83 fa 7b[ 	]+ccmpt \{dfv=\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a 80 fa 7b[ 	]+ccmpt \{dfv=\} r18b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 85 fa[ 	]+ctestt \{dfv=\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a f6 c2 7b[ 	]+ctestt \{dfv=\} r18b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 0d 02 39 f8[ 	]+ccmpb \{dfv=cf\} ax,r15w
+[ 	]*[a-f0-9]+:[ 	]*62 54 0c 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=cf\} r15d,DWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4d 02 83 ff 7b[ 	]+ccmpb \{dfv=of, cf\} r15w,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 80 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, cf\} BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 6d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 ec 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 fc 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, zf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 74 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf, zf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 f4 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, zf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 e4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, sf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 64 02 3a 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf\} r8b,BYTE PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 5c 02 38 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, zf, cf\} BYTE PTR \[r8\+rax\*4\+0x123\],r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 55 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=of, zf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 54 02 38 c2[ 	]+ccmpb \{dfv=of, zf\} dl,r8b
+[ 	]*[a-f0-9]+:[ 	]*62 74 44 02 39 fa[ 	]+ccmpb \{dfv=of\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 45 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of\} r15w,WORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 80 f8 7b[ 	]+ccmpb \{dfv=sf, cf\} r8b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 2c 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 ac 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\} r15,QWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 3c 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf, cf\} r15d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 3d 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf, cf\} r15w,WORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 34 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf\} r15d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 34 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 d4 a4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=sf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 39 ff[ 	]+ccmpb \{dfv=sf\} r15,r15
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf\} r15,QWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 83 ff 7b[ 	]+ccmpb \{dfv=zf, cf\} r15,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 1d 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 94 02 83 ff 7b[ 	]+ccmpb \{dfv=zf\} r15,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 15 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=zf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 15 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 05 02 83 ff 7b[ 	]+ccmpb \{dfv=\} r15w,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 04 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpb \{dfv=\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 04 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=\} r15d,DWORD PTR \[r8\+rax\*4\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 83 f8 7b[ 	]+ccmpo \{dfv=of\} r16,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 83 f9 7b[ 	]+ccmpno \{dfv=of\} r17,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 83 fa 7b[ 	]+ccmpb \{dfv=of\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 83 fb 7b[ 	]+ccmpae \{dfv=of\} r19,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 83 fc 7b[ 	]+ccmpe \{dfv=of\} r20,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 83 fd 7b[ 	]+ccmpne \{dfv=of\} r21,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 83 fe 7b[ 	]+ccmpbe \{dfv=of\} r22,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 83 ff 7b[ 	]+ccmpa \{dfv=of\} r23,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 83 f8 7b[ 	]+ccmps \{dfv=of\} r24,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 83 f9 7b[ 	]+ccmpns \{dfv=of\} r25,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a 83 fa 7b[ 	]+ccmpt \{dfv=of\} r26,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b 83 fb 7b[ 	]+ccmpf \{dfv=of\} r27,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c 83 fc 7b[ 	]+ccmpl \{dfv=of\} r28,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d 83 fd 7b[ 	]+ccmpge \{dfv=of\} r29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e 83 fe 7b[ 	]+ccmple \{dfv=of\} r30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f 83 ff 7b[ 	]+ccmpg \{dfv=of\} r31,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=cf\} r15,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 0d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 f6 84 80 23 01 00 00 7b[ 	]+ctestb \{dfv=of, cf\} BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 cc 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 ec 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=of, sf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=of, sf, zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 75 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=of, sf, zf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 64 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=of, sf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 65 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, sf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=of, zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 5d 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf, cf\} WORD PTR \[r8\+rax\*4\+0x123\],r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 54 02 f6 84 80 23 01 00 00 7b[ 	]+ctestb \{dfv=of, zf\} BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 d4 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf\} QWORD PTR \[r8\+rax\*4\+0x123\],r15
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 84 84 80 23 01 00 00[ 	]+ctestb \{dfv=of\} BYTE PTR \[r8\+rax\*4\+0x123\],r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=sf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 2c 02 85 fa[ 	]+ctestb \{dfv=sf, cf\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 3c 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=sf, zf, cf\} DWORD PTR \[r8\+rax\*4\+0x123\],r15d
+[ 	]*[a-f0-9]+:[ 	]*62 74 3c 02 84 c2[ 	]+ctestb \{dfv=sf, zf, cf\} dl,r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 35 02 f7 c7 7b 00[ 	]+ctestb \{dfv=sf, zf\} r15w,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 b4 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=sf, zf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 24 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=sf\} r15d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 25 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestb \{dfv=sf\} WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 f6 c0 7b[ 	]+ctestb \{dfv=zf, cf\} r8b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=zf, cf\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 14 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=zf\} DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 54 94 02 85 ff[ 	]+ctestb \{dfv=zf\} r15,r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 84 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestb \{dfv=\} QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 05 02 85 f8[ 	]+ctestb \{dfv=\} ax,r15w
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 f7 c0 7b 00 00 00[ 	]+ctesto \{dfv=of\} r16,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 f7 c1 7b 00 00 00[ 	]+ctestno \{dfv=of\} r17,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 f7 c2 7b 00 00 00[ 	]+ctestb \{dfv=of\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 f7 c3 7b 00 00 00[ 	]+ctestae \{dfv=of\} r19,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 f7 c4 7b 00 00 00[ 	]+cteste \{dfv=of\} r20,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 f7 c5 7b 00 00 00[ 	]+ctestne \{dfv=of\} r21,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 f7 c6 7b 00 00 00[ 	]+ctestbe \{dfv=of\} r22,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 f7 c7 7b 00 00 00[ 	]+ctesta \{dfv=of\} r23,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 f7 c0 7b 00 00 00[ 	]+ctests \{dfv=of\} r24,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 f7 c1 7b 00 00 00[ 	]+ctestns \{dfv=of\} r25,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=of\} r26,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b f7 c3 7b 00 00 00[ 	]+ctestf \{dfv=of\} r27,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c f7 c4 7b 00 00 00[ 	]+ctestl \{dfv=of\} r28,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d f7 c5 7b 00 00 00[ 	]+ctestge \{dfv=of\} r29,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e f7 c6 7b 00 00 00[ 	]+ctestle \{dfv=of\} r30,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} r31,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} r31,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 39 fa[ 	]+ccmpt \{dfv=\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a 83 fa 7b[ 	]+ccmpt \{dfv=\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a 80 fa 7b[ 	]+ccmpt \{dfv=\} r18b,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 85 fa[ 	]+ctestt \{dfv=\} edx,r15d
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=\} r18,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a f6 c2 7b[ 	]+ctestt \{dfv=\} r18b,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l
new file mode 100644
index 00000000000..84c3c984fae
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l
@@ -0,0 +1,17 @@ 
+.* Assembler messages:
+.*:[0-9]+: Error: Unrecognized oszc flags or illegal `,' in pseudo-suffix
+.*:[0-9]+: Error: Unrecognized oszc flags or illegal `,' in pseudo-suffix
+.*:[0-9]+: Error: Illegal `}' or `,' in pseudo-suffix
+.*:[0-9]+: Error: Illegal `}' or `,' in pseudo-suffix
+.*:[0-9]+: Error: same oszc flag used twice
+.*:[0-9]+: Error: Unrecognized pseudo-suffix
+.*:[0-9]+: Error: Unrecognized oszc flags or illegal `,' in pseudo-suffix
+.*:[0-9]+: Error: Unrecognized oszc flags or illegal `,' in pseudo-suffix
+.*:[0-9]+: Error: Unrecognized oszc flags or illegal `,' in pseudo-suffix
+.*:[0-9]+: Error: no such instruction.*
+.*:[0-9]+: Error: no such instruction.*
+.*:[0-9]+: Error: no such instruction.*
+.*:[0-9]+: Error: no such instruction.*
+.*:[0-9]+: Error: no such instruction.*
+.*:[0-9]+: Error: no such instruction.*
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s
new file mode 100644
index 00000000000..fd1be34a960
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s
@@ -0,0 +1,20 @@ 
+# Check APX_F ccmp ctest instructions with illegal instructions.
+
+	.text
+	ccmpb {dfv=ct} $0x7b,%r18
+	ctestb {dfv=sae} $0x7b,%r18
+	ccmpb {dfv=of $0x7b,%r18
+	ccmpb {dfv=of
+	ccmpb {dfv=cf, cf, of, of} $0x7b,%r18
+	ccmpb {dfv dfv=cf} $0x7b,%r18
+	ccmpb {dfv=cf, ,cf} $0x7b,%r18
+	ccmpb {dfv=cf,,} $0x7b,%r18
+	ccmpb {dfv=,cf} $0x7b,%r18
+	/* SCC insns don't support p/pe and np/po cc.  */
+	ccmpp {dfv=cf} %r15w,%ax
+	ccmppe {dfv=cf} %r15w,%ax
+	ctestnp {dfv=cf} %r15w,%ax
+	ctestpo {dfv=cf} %r15w,%ax
+	/* Normal CC insns don't support t and f.  */
+	sett %r8b
+	setf %r8b
diff --git a/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.d b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.d
new file mode 100644
index 00000000000..0f100f06e74
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.d
@@ -0,0 +1,222 @@ 
+#as:
+#objdump: -dw
+#name: x86_64 APX_F CCMP and CTEST insns
+#source: x86-64-apx-ccmp-ctest.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 0d 02 39 f8[ 	]+ccmpb \{dfv=cf\} %r15w,%ax
+[ 	]*[a-f0-9]+:[ 	]*62 54 0c 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=cf\}\s+0x123\(%r8,%rax,4\),%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4d 02 83 ff 7b[ 	]+ccmpb \{dfv=of, cf\}\s+\$0x7b,%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 80 bc 80 23 01 00 00 7b[ 	]+ccmpbb \{dfv=of, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 6d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=of, sf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 ec 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, cf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=of, sf, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 fc 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=of, sf, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 74 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=of, sf, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 f4 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, zf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 e4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=of, sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 64 02 3a 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf\}\s+0x123\(%r8,%rax,4\),%r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=of, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 5c 02 38 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, zf, cf\} %r8b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 55 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=of, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 54 02 38 c2[ 	]+ccmpb \{dfv=of, zf\} %r8b,%dl
+[ 	]*[a-f0-9]+:[ 	]*62 74 44 02 39 fa[ 	]+ccmpb \{dfv=of\} %r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 54 45 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of\}\s+0x123\(%r8,%rax,4\),%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 80 f8 7b[ 	]+ccmpb \{dfv=sf, cf\}\s+\$0x7b,%r8b
+[ 	]*[a-f0-9]+:[ 	]*62 54 2c 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 ac 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\}\s+0x123\(%r8,%rax,4\),%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 3c 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf, cf\}\s+\$0x7b,%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 3d 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf, cf\}\s+0x123\(%r8,%rax,4\),%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 34 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf\}\s+\$0x7b,%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 34 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 a4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 39 ff[ 	]+ccmpb \{dfv=sf\} %r15,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf\}\s+0x123\(%r8,%rax,4\),%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 83 ff 7b[ 	]+ccmpb \{dfv=zf, cf\}\s+\$0x7b,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 1d 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf, cf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 94 02 83 ff 7b[ 	]+ccmpb \{dfv=zf\}\s+\$0x7b,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 15 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 15 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 05 02 83 ff 7b[ 	]+ccmpb \{dfv=\}\s+\$0x7b,%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 04 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 04 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=\}\s+0x123\(%r8,%rax,4\),%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 83 f8 7b[ 	]+ccmpo \{dfv=of\} \$0x7b,%r16
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 83 f9 7b[ 	]+ccmpno \{dfv=of\} \$0x7b,%r17
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 83 fa 7b[ 	]+ccmpb \{dfv=of\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 83 fb 7b[ 	]+ccmpae \{dfv=of\} \$0x7b,%r19
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 83 fc 7b[ 	]+ccmpe \{dfv=of\} \$0x7b,%r20
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 83 fd 7b[ 	]+ccmpne \{dfv=of\} \$0x7b,%r21
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 83 fe 7b[ 	]+ccmpbe \{dfv=of\} \$0x7b,%r22
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 83 ff 7b[ 	]+ccmpa \{dfv=of\} \$0x7b,%r23
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 83 f8 7b[ 	]+ccmps \{dfv=of\} \$0x7b,%r24
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 83 f9 7b[ 	]+ccmpns \{dfv=of\} \$0x7b,%r25
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a 83 fa 7b[ 	]+ccmpt \{dfv=of\} \$0x7b,%r26
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b 83 fb 7b[ 	]+ccmpf \{dfv=of\} \$0x7b,%r27
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c 83 fc 7b[ 	]+ccmpl \{dfv=of\} \$0x7b,%r28
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d 83 fd 7b[ 	]+ccmpge \{dfv=of\} \$0x7b,%r29
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e 83 fe 7b[ 	]+ccmple \{dfv=of\} \$0x7b,%r30
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f 83 ff 7b[ 	]+ccmpg \{dfv=of\} \$0x7b,%r31
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=cf\}\s+\$0x7b,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 0d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 f6 84 80 23 01 00 00 7b[ 	]+ctestbb \{dfv=of, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 cc 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, cf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 ec 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=of, sf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=of, sf, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 75 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=of, sf, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 64 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=of, sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 65 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, sf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=of, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 5d 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf, cf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 54 02 f6 84 80 23 01 00 00 7b[ 	]+ctestbb \{dfv=of, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 d4 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 84 84 80 23 01 00 00[ 	]+ctestb \{dfv=of\} %r8b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=sf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 2c 02 85 fa[ 	]+ctestb \{dfv=sf, cf\} %r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 54 3c 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=sf, zf, cf\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 3c 02 84 c2[ 	]+ctestb \{dfv=sf, zf, cf\} %r8b,%dl
+[ 	]*[a-f0-9]+:[ 	]*62 d4 35 02 f7 c7 7b 00[ 	]+ctestb \{dfv=sf, zf\}\s+\$0x7b,%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 b4 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=sf, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 24 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=sf\}\s+\$0x7b,%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 d4 25 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 f6 c0 7b[ 	]+ctestb \{dfv=zf, cf\}\s+\$0x7b,%r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 14 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 94 02 85 ff[ 	]+ctestb \{dfv=zf\} %r15,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 84 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 05 02 85 f8[ 	]+ctestb \{dfv=\} %r15w,%ax
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 f7 c0 7b 00 00 00[ 	]+ctesto \{dfv=of\} \$0x7b,%r16
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 f7 c1 7b 00 00 00[ 	]+ctestno \{dfv=of\} \$0x7b,%r17
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 f7 c2 7b 00 00 00[ 	]+ctestb \{dfv=of\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 f7 c3 7b 00 00 00[ 	]+ctestae \{dfv=of\} \$0x7b,%r19
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 f7 c4 7b 00 00 00[ 	]+cteste \{dfv=of\} \$0x7b,%r20
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 f7 c5 7b 00 00 00[ 	]+ctestne \{dfv=of\} \$0x7b,%r21
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 f7 c6 7b 00 00 00[ 	]+ctestbe \{dfv=of\} \$0x7b,%r22
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 f7 c7 7b 00 00 00[ 	]+ctesta \{dfv=of\} \$0x7b,%r23
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 f7 c0 7b 00 00 00[ 	]+ctests \{dfv=of\} \$0x7b,%r24
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 f7 c1 7b 00 00 00[ 	]+ctestns \{dfv=of\} \$0x7b,%r25
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=of\} \$0x7b,%r26
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b f7 c3 7b 00 00 00[ 	]+ctestf \{dfv=of\} \$0x7b,%r27
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c f7 c4 7b 00 00 00[ 	]+ctestl \{dfv=of\} \$0x7b,%r28
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d f7 c5 7b 00 00 00[ 	]+ctestge \{dfv=of\} \$0x7b,%r29
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e f7 c6 7b 00 00 00[ 	]+ctestle \{dfv=of\} \$0x7b,%r30
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} \$0x7b,%r31
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} \$0x7b,%r31
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 39 fa[ 	]+ccmpt \{dfv=\} %r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a 83 fa 7b[ 	]+ccmpt \{dfv=\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a 80 fa 7b[ 	]+ccmpt \{dfv=\} \$0x7b,%r18b
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 85 fa[ 	]+ctestt \{dfv=\} \%r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a f6 c2 7b[ 	]+ctestt \{dfv=\} \$0x7b,%r18b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 0d 02 39 f8[ 	]+ccmpb \{dfv=cf\} %r15w,%ax
+[ 	]*[a-f0-9]+:[ 	]*62 54 0c 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=cf\}\s+0x123\(%r8,%rax,4\),%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4d 02 83 ff 7b[ 	]+ccmpb \{dfv=of, cf\}\s+\$0x7b,%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 80 bc 80 23 01 00 00 7b[ 	]+ccmpbb \{dfv=of, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 6d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=of, sf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 ec 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, cf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7d 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=of, sf, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 fc 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=of, sf, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 74 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=of, sf, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 f4 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf, zf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 e4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=of, sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 64 02 3a 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, sf\}\s+0x123\(%r8,%rax,4\),%r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=of, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 5c 02 38 84 80 23 01 00 00[ 	]+ccmpb \{dfv=of, zf, cf\} %r8b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 55 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=of, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 54 02 38 c2[ 	]+ccmpb \{dfv=of, zf\} %r8b,%dl
+[ 	]*[a-f0-9]+:[ 	]*62 74 44 02 39 fa[ 	]+ccmpb \{dfv=of\} %r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 54 45 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=of\}\s+0x123\(%r8,%rax,4\),%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 80 f8 7b[ 	]+ccmpb \{dfv=sf, cf\}\s+\$0x7b,%r8b
+[ 	]*[a-f0-9]+:[ 	]*62 54 2c 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 ac 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, cf\}\s+0x123\(%r8,%rax,4\),%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 3c 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf, cf\}\s+\$0x7b,%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 3d 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf, cf\}\s+0x123\(%r8,%rax,4\),%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 34 02 83 ff 7b[ 	]+ccmpb \{dfv=sf, zf\}\s+\$0x7b,%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 54 34 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf, zf\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 a4 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbq \{dfv=sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 39 ff[ 	]+ccmpb \{dfv=sf\} %r15,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 54 a4 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=sf\}\s+0x123\(%r8,%rax,4\),%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 83 ff 7b[ 	]+ccmpb \{dfv=zf, cf\}\s+\$0x7b,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 1d 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf, cf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 94 02 83 ff 7b[ 	]+ccmpb \{dfv=zf\}\s+\$0x7b,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 15 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbw \{dfv=zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 15 02 39 bc 80 23 01 00 00[ 	]+ccmpb \{dfv=zf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 05 02 83 ff 7b[ 	]+ccmpb \{dfv=\}\s+\$0x7b,%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 04 02 83 bc 80 23 01 00 00 7b[ 	]+ccmpbl \{dfv=\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 04 02 3b bc 80 23 01 00 00[ 	]+ccmpb \{dfv=\}\s+0x123\(%r8,%rax,4\),%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 83 f8 7b[ 	]+ccmpo \{dfv=of\} \$0x7b,%r16
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 83 f9 7b[ 	]+ccmpno \{dfv=of\} \$0x7b,%r17
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 83 fa 7b[ 	]+ccmpb \{dfv=of\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 83 fb 7b[ 	]+ccmpae \{dfv=of\} \$0x7b,%r19
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 83 fc 7b[ 	]+ccmpe \{dfv=of\} \$0x7b,%r20
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 83 fd 7b[ 	]+ccmpne \{dfv=of\} \$0x7b,%r21
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 83 fe 7b[ 	]+ccmpbe \{dfv=of\} \$0x7b,%r22
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 83 ff 7b[ 	]+ccmpa \{dfv=of\} \$0x7b,%r23
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 83 f8 7b[ 	]+ccmps \{dfv=of\} \$0x7b,%r24
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 83 f9 7b[ 	]+ccmpns \{dfv=of\} \$0x7b,%r25
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a 83 fa 7b[ 	]+ccmpt \{dfv=of\} \$0x7b,%r26
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b 83 fb 7b[ 	]+ccmpf \{dfv=of\} \$0x7b,%r27
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c 83 fc 7b[ 	]+ccmpl \{dfv=of\} \$0x7b,%r28
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d 83 fd 7b[ 	]+ccmpge \{dfv=of\} \$0x7b,%r29
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e 83 fe 7b[ 	]+ccmple \{dfv=of\} \$0x7b,%r30
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f 83 ff 7b[ 	]+ccmpg \{dfv=of\} \$0x7b,%r31
+[ 	]*[a-f0-9]+:[ 	]*62 d4 8c 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=cf\}\s+\$0x7b,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 0d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 4c 02 f6 84 80 23 01 00 00 7b[ 	]+ctestbb \{dfv=of, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 cc 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, cf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 ec 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=of, sf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 7c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=of, sf, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 75 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=of, sf, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 64 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=of, sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 65 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, sf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 5d 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=of, zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 5d 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf, cf\} %r15w,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 54 02 f6 84 80 23 01 00 00 7b[ 	]+ctestbb \{dfv=of, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 d4 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of, zf\} %r15,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=of\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 44 02 84 84 80 23 01 00 00[ 	]+ctestb \{dfv=of\} %r8b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 2c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=sf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 2c 02 85 fa[ 	]+ctestb \{dfv=sf, cf\} %r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 54 3c 02 85 bc 80 23 01 00 00[ 	]+ctestb \{dfv=sf, zf, cf\} %r15d,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 3c 02 84 c2[ 	]+ctestb \{dfv=sf, zf, cf\} %r8b,%dl
+[ 	]*[a-f0-9]+:[ 	]*62 d4 35 02 f7 c7 7b 00[ 	]+ctestb \{dfv=sf, zf\}\s+\$0x7b,%r15w
+[ 	]*[a-f0-9]+:[ 	]*62 d4 b4 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=sf, zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 24 02 f7 c7 7b 00 00 00[ 	]+ctestb \{dfv=sf\}\s+\$0x7b,%r15d
+[ 	]*[a-f0-9]+:[ 	]*62 d4 25 02 f7 84 80 23 01 00 00 7b 00[ 	]+ctestbw \{dfv=sf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 1c 02 f6 c0 7b[ 	]+ctestb \{dfv=zf, cf\}\s+\$0x7b,%r8b
+[ 	]*[a-f0-9]+:[ 	]*62 d4 9c 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=zf, cf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 d4 14 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbl \{dfv=zf\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 54 94 02 85 ff[ 	]+ctestb \{dfv=zf\} %r15,%r15
+[ 	]*[a-f0-9]+:[ 	]*62 d4 84 02 f7 84 80 23 01 00 00 7b 00 00 00[ 	]+ctestbq \{dfv=\}\s+\$0x7b,0x123\(%r8,%rax,4\)
+[ 	]*[a-f0-9]+:[ 	]*62 74 05 02 85 f8[ 	]+ctestb \{dfv=\} %r15w,%ax
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 00 f7 c0 7b 00 00 00[ 	]+ctesto \{dfv=of\} \$0x7b,%r16
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 01 f7 c1 7b 00 00 00[ 	]+ctestno \{dfv=of\} \$0x7b,%r17
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 02 f7 c2 7b 00 00 00[ 	]+ctestb \{dfv=of\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 03 f7 c3 7b 00 00 00[ 	]+ctestae \{dfv=of\} \$0x7b,%r19
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 04 f7 c4 7b 00 00 00[ 	]+cteste \{dfv=of\} \$0x7b,%r20
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 05 f7 c5 7b 00 00 00[ 	]+ctestne \{dfv=of\} \$0x7b,%r21
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 06 f7 c6 7b 00 00 00[ 	]+ctestbe \{dfv=of\} \$0x7b,%r22
+[ 	]*[a-f0-9]+:[ 	]*62 fc c4 07 f7 c7 7b 00 00 00[ 	]+ctesta \{dfv=of\} \$0x7b,%r23
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 08 f7 c0 7b 00 00 00[ 	]+ctests \{dfv=of\} \$0x7b,%r24
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 09 f7 c1 7b 00 00 00[ 	]+ctestns \{dfv=of\} \$0x7b,%r25
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=of\} \$0x7b,%r26
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0b f7 c3 7b 00 00 00[ 	]+ctestf \{dfv=of\} \$0x7b,%r27
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0c f7 c4 7b 00 00 00[ 	]+ctestl \{dfv=of\} \$0x7b,%r28
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0d f7 c5 7b 00 00 00[ 	]+ctestge \{dfv=of\} \$0x7b,%r29
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0e f7 c6 7b 00 00 00[ 	]+ctestle \{dfv=of\} \$0x7b,%r30
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} \$0x7b,%r31
+[ 	]*[a-f0-9]+:[ 	]*62 dc c4 0f f7 c7 7b 00 00 00[ 	]+ctestg \{dfv=of\} \$0x7b,%r31
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 39 fa[ 	]+ccmpt \{dfv=\} %r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a 83 fa 7b[ 	]+ccmpt \{dfv=\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a 80 fa 7b[ 	]+ccmpt \{dfv=\} \$0x7b,%r18b
+[ 	]*[a-f0-9]+:[ 	]*62 74 04 0a 85 fa[ 	]+ctestt \{dfv=\} \%r15d,%edx
+[ 	]*[a-f0-9]+:[ 	]*62 fc 84 0a f7 c2 7b 00 00 00[ 	]+ctestt \{dfv=\} \$0x7b,%r18
+[ 	]*[a-f0-9]+:[ 	]*62 fc 04 0a f6 c2 7b[ 	]+ctestt \{dfv=\} \$0x7b,%r18b
diff --git a/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.s b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.s
new file mode 100644
index 00000000000..66bf224c5bd
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-ccmp-ctest.s
@@ -0,0 +1,218 @@ 
+# Check 64bit APX_F CCMP and CTEST instructions
+
+ .text
+_start:
+	ccmpbq   {dfv=cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=cf} %r15w,%ax
+	ccmpb    {dfv=cf} 0x123(%r8,%rax,4),%r15d
+	ccmpb    {dfv=of, cf} $0x7b,%r15w
+	ccmpbb   {dfv=of, cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpbw   {dfv=of, sf, cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=of, sf, cf} %r15,0x123(%r8,%rax,4)
+	ccmpbw   {dfv=of, sf, zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpbq   {dfv=of, sf, zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpbl   {dfv=of, sf, zf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=of, sf, zf} %r15,0x123(%r8,%rax,4)
+	ccmpbq   {dfv=of, sf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=of, sf} 0x123(%r8,%rax,4),%r8b
+	ccmpbl   {dfv=of, zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=of, zf, cf} %r8b,0x123(%r8,%rax,4)
+	ccmpbw   {dfv=of, zf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=of, zf} %r8b,%dl
+	ccmpb    {dfv=of} %r15d,%edx
+	ccmpb    {dfv=of} 0x123(%r8,%rax,4),%r15w
+	ccmpb    {dfv=sf, cf} $0x7b,%r8b
+	ccmpb    {dfv=sf, cf} %r15d,0x123(%r8,%rax,4)
+	ccmpb    {dfv=sf, cf} 0x123(%r8,%rax,4),%r15
+	ccmpb    {dfv=sf, zf, cf} $0x7b,%r15d
+	ccmpb    {dfv=sf, zf, cf} 0x123(%r8,%rax,4),%r15w
+	ccmpb    {dfv=sf, zf} $0x7b,%r15d
+	ccmpb    {dfv=sf, zf} %r15d,0x123(%r8,%rax,4)
+	ccmpbq   {dfv=sf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=sf} %r15,%r15
+	ccmpb    {dfv=sf} 0x123(%r8,%rax,4),%r15
+	ccmpb    {dfv=zf, cf} $0x7b,%r15
+	ccmpbl   {dfv=zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=zf, cf} %r15w,0x123(%r8,%rax,4)
+	ccmpb    {dfv=zf} $0x7b,%r15
+	ccmpbw   {dfv=zf} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=zf} %r15w,0x123(%r8,%rax,4)
+	ccmpb    {dfv=} $0x7b,%r15w
+	ccmpbl   {dfv=} $0x7b,0x123(%r8,%rax,4)
+	ccmpb    {dfv=} 0x123(%r8,%rax,4),%r15d
+	ccmpo    {dfv=of} $0x7b,%r16
+	ccmpno   {dfv=of} $0x7b,%r17
+	ccmpb    {dfv=of} $0x7b,%r18
+	ccmpae   {dfv=of} $0x7b,%r19
+	ccmpe    {dfv=of} $0x7b,%r20
+	ccmpne   {dfv=of} $0x7b,%r21
+	ccmpbe   {dfv=of} $0x7b,%r22
+	ccmpa    {dfv=of} $0x7b,%r23
+	ccmps    {dfv=of} $0x7b,%r24
+	ccmpns   {dfv=of} $0x7b,%r25
+	ccmpt    {dfv=of} $0x7b,%r26
+	ccmpf    {dfv=of} $0x7b,%r27
+	ccmpl    {dfv=of} $0x7b,%r28
+	ccmpge   {dfv=of} $0x7b,%r29
+	ccmple   {dfv=of} $0x7b,%r30
+	ccmpg    {dfv=of} $0x7b,%r31
+	ctestb   {dfv=cf} $0x7b,%r15
+	ctestbw  {dfv=cf} $0x7b,0x123(%r8,%rax,4)
+	ctestbb  {dfv=of, cf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=of, cf} %r15,0x123(%r8,%rax,4)
+	ctestbq  {dfv=of, sf, cf} $0x7b,0x123(%r8,%rax,4)
+	ctestbl  {dfv=of, sf, zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ctestbw  {dfv=of, sf, zf} $0x7b,0x123(%r8,%rax,4)
+	ctestbl  {dfv=of, sf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=of, sf} %r15w,0x123(%r8,%rax,4)
+	ctestbw  {dfv=of, zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=of, zf, cf} %r15w,0x123(%r8,%rax,4)
+	ctestbb  {dfv=of, zf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=of, zf} %r15,0x123(%r8,%rax,4)
+	ctestb   {dfv=of} %r15d,0x123(%r8,%rax,4)
+	ctestb   {dfv=of} %r8b,0x123(%r8,%rax,4)
+	ctestbl  {dfv=sf, cf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=sf, cf} %r15d,%edx
+	ctestb   {dfv=sf, zf, cf} %r15d,0x123(%r8,%rax,4)
+	ctestb   {dfv=sf, zf, cf} %r8b,%dl
+	ctestb   {dfv=sf, zf} $0x7b,%r15w
+	ctestbq  {dfv=sf, zf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=sf} $0x7b,%r15d
+	ctestbw  {dfv=sf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=zf, cf} $0x7b,%r8b
+	ctestbq  {dfv=zf, cf} $0x7b,0x123(%r8,%rax,4)
+	ctestbl  {dfv=zf} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=zf} %r15,%r15
+	ctestbq  {dfv=} $0x7b,0x123(%r8,%rax,4)
+	ctestb   {dfv=} %r15w,%ax
+	ctesto   {dfv=of} $0x7b,%r16
+	ctestno  {dfv=of} $0x7b,%r17
+	ctestb   {dfv=of} $0x7b,%r18
+	ctestnb  {dfv=of} $0x7b,%r19
+	ctestz   {dfv=of} $0x7b,%r20
+	ctestnz  {dfv=of} $0x7b,%r21
+	ctestbe  {dfv=of} $0x7b,%r22
+	ctestnbe {dfv=of} $0x7b,%r23
+	ctests   {dfv=of} $0x7b,%r24
+	ctestns  {dfv=of} $0x7b,%r25
+	ctestt   {dfv=of} $0x7b,%r26
+	ctestf   {dfv=of} $0x7b,%r27
+	ctestl   {dfv=of} $0x7b,%r28
+	ctestnl  {dfv=of} $0x7b,%r29
+	ctestle  {dfv=of} $0x7b,%r30
+	ctestnle {dfv=of} $0x7b,%r31
+	CTESTNLE {DFV=OF} $0x7b,%r31
+	{evex} cmp %r15d,%edx
+	{evex} cmp $0x7b,%r18
+	{evex} cmp $0x7b,%r18b
+	{evex} test %r15d,%edx
+	{evex} test $0x7b,%r18
+	{evex} test $0x7b,%r18b
+
+	.intel_syntax noprefix
+	ccmpb    {dfv=cf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=cf} ax,r15w
+	ccmpb    {dfv=cf} r15d,DWORD PTR [r8+rax*4+0x123]
+	ccmpb    {dfv=of, cf} r15w,0x7b
+	ccmpb    {dfv=of, cf} BYTE PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, sf, cf} WORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, sf, cf} QWORD PTR [r8+rax*4+0x123],r15
+	ccmpb    {dfv=of, sf, zf, cf} WORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, sf, zf, cf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, sf, zf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, sf, zf} QWORD PTR [r8+rax*4+0x123],r15
+	ccmpb    {dfv=of, sf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, sf} r8b,BYTE PTR [r8+rax*4+0x123]
+	ccmpb    {dfv=of, zf, cf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, zf, cf} BYTE PTR [r8+rax*4+0x123],r8b
+	ccmpb    {dfv=of, zf} WORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=of, zf} dl,r8b
+	ccmpb    {dfv=of} edx,r15d
+	ccmpb    {dfv=of} r15w,WORD PTR [r8+rax*4+0x123]
+	ccmpb    {dfv=sf, cf} r8b,0x7b
+	ccmpb    {dfv=sf, cf} DWORD PTR [r8+rax*4+0x123],r15d
+	ccmpb    {dfv=sf, cf} r15,QWORD PTR [r8+rax*4+0x123]
+	ccmpb    {dfv=sf, zf, cf} r15d,0x7b
+	ccmpb    {dfv=sf, zf, cf} r15w,WORD PTR [r8+rax*4+0x123]
+	ccmpb    {dfv=sf, zf} r15d,0x7b
+	ccmpb    {dfv=sf, zf} DWORD PTR [r8+rax*4+0x123],r15d
+	ccmpb    {dfv=sf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=sf} r15,r15
+	ccmpb    {dfv=sf} r15,QWORD PTR [r8+rax*4+0x123]
+	ccmpb    {dfv=zf, cf} r15,0x7b
+	ccmpb    {dfv=zf, cf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=zf, cf} WORD PTR [r8+rax*4+0x123],r15w
+	ccmpb    {dfv=zf} r15,0x7b
+	ccmpb    {dfv=zf} WORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=zf} WORD PTR [r8+rax*4+0x123],r15w
+	ccmpb    {dfv=} r15w,0x7b
+	ccmpb    {dfv=} DWORD PTR [r8+rax*4+0x123],0x7b
+	ccmpb    {dfv=} r15d,DWORD PTR [r8+rax*4+0x123]
+	ccmpo    {dfv=of} r16,0x7b
+	ccmpno   {dfv=of} r17,0x7b
+	ccmpb    {dfv=of} r18,0x7b
+	ccmpae   {dfv=of} r19,0x7b
+	ccmpe    {dfv=of} r20,0x7b
+	ccmpne   {dfv=of} r21,0x7b
+	ccmpbe   {dfv=of} r22,0x7b
+	ccmpa    {dfv=of} r23,0x7b
+	ccmps    {dfv=of} r24,0x7b
+	ccmpns   {dfv=of} r25,0x7b
+	ccmpt    {dfv=of} r26,0x7b
+	ccmpf    {dfv=of} r27,0x7b
+	ccmpl    {dfv=of} r28,0x7b
+	ccmpge   {dfv=of} r29,0x7b
+	ccmple   {dfv=of} r30,0x7b
+	ccmpg    {dfv=of} r31,0x7b
+	ctestb   {dfv=cf} r15,0x7b
+	ctestb   {dfv=cf} WORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, cf} BYTE PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, cf} QWORD PTR [r8+rax*4+0x123],r15
+	ctestb   {dfv=of, sf, cf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, sf, zf, cf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, sf, zf} WORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, sf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, sf} WORD PTR [r8+rax*4+0x123],r15w
+	ctestb   {dfv=of, zf, cf} WORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, zf, cf} WORD PTR [r8+rax*4+0x123],r15w
+	ctestb   {dfv=of, zf} BYTE PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=of, zf} QWORD PTR [r8+rax*4+0x123],r15
+	ctestb   {dfv=of} DWORD PTR [r8+rax*4+0x123],r15d
+	ctestb   {dfv=of} BYTE PTR [r8+rax*4+0x123],r8b
+	ctestb   {dfv=sf, cf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=sf, cf} edx,r15d
+	ctestb   {dfv=sf, zf, cf} DWORD PTR [r8+rax*4+0x123],r15d
+	ctestb   {dfv=sf, zf, cf} dl,r8b
+	ctestb   {dfv=sf, zf} r15w,0x7b
+	ctestb   {dfv=sf, zf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=sf} r15d,0x7b
+	ctestb   {dfv=sf} WORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=zf, cf} r8b,0x7b
+	ctestb   {dfv=zf, cf} QWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=zf} DWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=zf} r15,r15
+	ctestb   {dfv=} QWORD PTR [r8+rax*4+0x123],0x7b
+	ctestb   {dfv=} ax,r15w
+	ctesto   {dfv=of} r16,0x7b
+	ctestno  {dfv=of} r17,0x7b
+	ctestb   {dfv=of} r18,0x7b
+	ctestnb  {dfv=of} r19,0x7b
+	ctestz   {dfv=of} r20,0x7b
+	ctestnz  {dfv=of} r21,0x7b
+	ctestbe  {dfv=of} r22,0x7b
+	ctestnbe {dfv=of} r23,0x7b
+	ctests   {dfv=of} r24,0x7b
+	ctestns  {dfv=of} r25,0x7b
+	ctestt   {dfv=of} r26,0x7b
+	ctestf   {dfv=of} r27,0x7b
+	ctestl   {dfv=of} r28,0x7b
+	ctestnl  {dfv=of} r29,0x7b
+	ctestle  {dfv=of} r30,0x7b
+	ctestnle {dfv=of} r31,0x7b
+        CTESTNLE {DFV=OF} r31,0x7b
+	{evex} cmp  edx, r15d
+	{evex} cmp  r18, 0x7b
+	{evex} cmp  r18b, 0x7b
+	{evex} test  edx, r15d
+	{evex} test  r18, 0x7b
+	{evex} test  r18b, 0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
index 6330367194c..7c2efb08d71 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
@@ -15,13 +15,13 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:[ 	]+62 e2 f9 41 91 84[ 	]+vpgatherqq \(bad\),%zmm16\{%k1\}
 [ 	]*[a-f0-9]+:[ 	]+cd ff[ 	]+int    \$0xff
 [ 	]*[a-f0-9]+:[ 	]+62 fd 7d 08 60[ 	]+\(bad\)
+[ 	]*[a-f0-9]+:[ 	]+c7[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+62 fc 7d 09 60[ 	]+\(bad\).*
 [ 	]*[a-f0-9]+:[ 	]+c7[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+62 fc 7d[ 	]+\(bad\).*
-[ 	]*[a-f0-9]+:[ 	]+09 60 c7[ 	]+or     %esp,-0x39\(%rax\)
-[ 	]*[a-f0-9]+:[ 	]+62 fc 7d[ 	]+\(bad\).*
-[ 	]*[a-f0-9]+:[ 	]+28 60 c7[ 	]+.*
-[ 	]*[a-f0-9]+:[ 	]+62 fc 7d[ 	]+\(bad\).*
-[ 	]*[a-f0-9]+:[ 	]+8b 60 c7[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+62 fc 7d 28 60[ 	]+\(bad\).*
+[ 	]*[a-f0-9]+:[ 	]+c7[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+62 fc 7d 8b 60[ 	]+\(bad\).*
+[ 	]*[a-f0-9]+:[ 	]+c7[ 	]+.*
 [ 	]*[a-f0-9]+:[ 	]+62 f2 fc 09 f5[ 	]+\(bad\).*
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
 [ 	]*[a-f0-9]+:[ 	]+62 f2 fc 28 f5[ 	]+\(bad\)
@@ -30,15 +30,15 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
 [ 	]*[a-f0-9]+:[ 	]+62 f2 fc 18 f5[ 	]+\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
-[ 	]*[a-f0-9]+:[ 	]+62 f4 e4[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+08 ff[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+62 f4 e4 08 ff[ 	]+\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+04 08[ 	]+.*
-[ 	]*[a-f0-9]+:[ 	]+62 f4 3c[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+08 8f c0 ff ff ff[ 	]+or.*
+[ 	]*[a-f0-9]+:[ 	]+62 f4 3c 08 8f[ 	]+\(bad\)
+[ 	]*[a-f0-9]+:[ 	]+c7[ 	]+.*
 [ 	]*[a-f0-9]+:[ 	]+62 74 7c 18 8f c0[ 	]+pop2   %rax,\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+62 d4 24 18 8f[ 	]+\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+c3[ 	]+.*
 [ 	]*[a-f0-9]+:[ 	]+62 fc 7d 0c 60 c7[ 	]+movbe  \{bad-nf\},%r23w,%ax
 [ 	]*[a-f0-9]+:[ 	]+62 fc 79 08 60[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+c2[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+c7[ 	 ]+.*
+[ 	]*[a-f0-9]+:[ 	]+62 d4 fc 18 38 d7[ 	]+ccmps\(bad\) \{dfv=of, sf, zf, cf\} %dl,%r15b
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
index cbf34515bab..959e4e1fb43 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
@@ -41,9 +41,8 @@  _start:
 	#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
 	.byte 0x62, 0xf4, 0xe4, 0x08, 0xff, 0x04, 0x08
 
-	# pop2 %rax, %r8 set EVEX.ND=0.
-	.byte 0x62, 0xf4, 0x3c, 0x08, 0x8f, 0xc0
-	.byte 0xff, 0xff, 0xff
+	# pop2 %rdi, %r8 set EVEX.ND=0.
+	.byte 0x62, 0xf4, 0x3c, 0x08, 0x8f, 0xc7
 
 	# pop2 %rax, %r8 set EVEX.vvvv = 1111.
 	.insn EVEX.L0.M4.W0 0x8f,  %rax, {rn-sae},%r8
@@ -54,5 +53,8 @@  _start:
 	#EVEX_MAP4 movbe %r18w,%ax set EVEX.nf = 1.
 	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k4}
 
-	# EVEX_MAP4 movbe %r18w,%ax set EVEX.P[10] = 0.
-	.byte 0x62, 0xfc, 0x79, 0x08, 0x60, 0xc2
+	# EVEX_MAP4 movbe %r23w,%ax set EVEX.P[10] = 0.
+	.byte 0x62, 0xfc, 0x79, 0x08, 0x60, 0xc7
+
+	# ccmps {dfv=of,sf,zf,cf} %r15, %rdx set EVEX.ND = 1.
+	.insn EVEX.L0.M4.W1 0x38, %r15, {rn-sae},%rdx
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 8ac7aca1fec..a8d49cefe8c 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -353,6 +353,9 @@  run_dump_test "x86-64-avx512dq-rcigrne"
 run_dump_test "x86-64-apx-push2pop2"
 run_dump_test "x86-64-apx-push2pop2-intel"
 run_list_test "x86-64-apx-push2pop2-inval"
+run_dump_test "x86-64-apx-ccmp-ctest"
+run_dump_test "x86-64-apx-ccmp-ctest-intel"
+run_list_test "x86-64-apx-ccmp-ctest-inval"
 run_dump_test "x86-64-apx-pushp-popp"
 run_dump_test "x86-64-apx-pushp-popp-intel"
 run_list_test "x86-64-apx-pushp-popp-inval"
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h
index 7408295f8e5..eda0e824aef 100644
--- a/opcodes/i386-dis-evex-reg.h
+++ b/opcodes/i386-dis-evex-reg.h
@@ -58,6 +58,7 @@ 
     { "%NFandA",	{ VexGb, Eb, Ib }, NO_PREFIX },
     { "%NFsubA",	{ VexGb, Eb, Ib }, NO_PREFIX },
     { "%NFxorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NEccmp%SCA%DF",	{ Eb, Ib }, NO_PREFIX },
   },
   /* REG_EVEX_MAP4_81 */
   {
@@ -68,6 +69,7 @@ 
     { "%NFandQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
     { "%NFsubQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
     { "%NFxorQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NEccmp%SCQ%DF",	{ Ev, Iv }, PREFIX_NP_OR_DATA },
   },
   /* REG_EVEX_MAP4_83 */
   {
@@ -78,6 +80,7 @@ 
     { "%NFandQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
     { "%NFsubQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
     { "%NFxorQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
+    { "%NEccmp%SCQ%DF",	{ Ev, sIb }, PREFIX_NP_OR_DATA },
   },
   /* REG_EVEX_MAP4_8F */
   {
@@ -85,8 +88,8 @@ 
   },
   /* REG_EVEX_MAP4_F6 */
   {
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "%NEctest%SCA%DF",  { Eb, Ib }, NO_PREFIX },
+    { "%NEctest%SCA%DF",  { Eb, Ib }, NO_PREFIX },
     { "notA",	{ VexGb, Eb }, NO_PREFIX },
     { "%NFnegA",	{ VexGb, Eb }, NO_PREFIX },
     { "%NFmulA",	{ Eb }, NO_PREFIX },
@@ -96,8 +99,8 @@ 
   },
   /* REG_EVEX_MAP4_F7 */
   {
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "%NEctest%SCQ%DF",  { Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NEctest%SCQ%DF",  { Ev, Iv }, PREFIX_NP_OR_DATA },
     { "notQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
     { "%NFnegQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
     { "%NFmulQ",	{ Ev }, PREFIX_NP_OR_DATA },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index a3d3fbe204d..77c2ee772d1 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -938,10 +938,10 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 38 */
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "%NEccmp%SCB%DF",		{ Eb, Gb }, 0 },
+    { "%NEccmp%SCS%DF",		{ Ev, Gv }, PREFIX_NP_OR_DATA },
+    { "%NEccmp%SCB%DF",		{ Gb, EbS }, 0 },
+    { "%NEccmp%SCS%DF",		{ Gv, EvS }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -1023,8 +1023,8 @@  static const struct dis386 evex_table[][256] = {
     { REG_TABLE (REG_EVEX_MAP4_81) },
     { Bad_Opcode },
     { REG_TABLE (REG_EVEX_MAP4_83) },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "%NEctest%SCB%DF",	      { Eb, Gb }, NO_PREFIX },
+    { "%NEctest%SCS%DF",	      { Ev, Gv }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 88 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 5e9e53c4939..24c33047001 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -219,6 +219,7 @@  struct instr_info
     int length;
     int prefix;
     int mask_register_specifier;
+    int scc;
     int ll;
     bool w;
     bool evex;
@@ -1804,7 +1805,10 @@  struct dis386 {
 	   instruction.
    "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
 	   pseudo prefix when instructions without NF, EGPR and VVVV,
+   "NE" => don't print "{evex} " pseudo prefix for some special instructions
+	   in MAP4.
    "ZU" => print 'zu' if EVEX.ZU=1.
+   "SC" => print suffix SCC for SCC insns
    "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
    "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
@@ -1814,6 +1818,7 @@  struct dis386 {
    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
    "DQ" => print 'd' or 'q' depending on the VEX.W bit
+   "DF" => print default flag value for SCC insns
    "BW" => print 'b' or 'w' depending on the VEX.W bit
    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
 	   an operand size prefix, or suffix_always is true.  print
@@ -9047,6 +9052,7 @@  get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
 
       ins->vex.v = *ins->codep & 0x8;
       ins->vex.mask_register_specifier = *ins->codep & 0x7;
+      ins->vex.scc = *ins->codep & 0xf;
       ins->vex.zeroing = *ins->codep & 0x80;
       /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
 	 when it's an evex_default one.  */
@@ -9064,22 +9070,8 @@  get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
 	  ins->rex2 &= ~REX_R;
 	}
 
-      /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
-	 all bits of EVEX.vvvv and EVEX.V' must be 1.  */
-      if (ins->evex_type == evex_from_legacy && !ins->vex.nd
-	  && (ins->vex.register_specifier || !ins->vex.v))
-	return &bad_opcode;
-
       ins->need_vex = 4;
 
-      /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
-	 lower 2 bits of EVEX.aaa must be 0.  */
-      if (ins->evex_type == evex_from_legacy
-	  && ((ins->vex.mask_register_specifier & 0x3) != 0
-	      || ins->vex.ll != 0
-	      || ins->vex.zeroing != 0))
-	return &bad_opcode;
-
       ins->codep++;
       vindex = *ins->codep++;
       ins->condition_code = vindex & 0xf;
@@ -9186,7 +9178,7 @@  i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
   va_list ap;
   enum disassembler_style curr_style = style;
   const char *start, *curr;
-  char staging_area[40];
+  char staging_area[50];
 
   va_start (ap, fmt);
   /* In particular print_insn()'s processing of op_txt[] can hand rather long
@@ -9630,7 +9622,32 @@  print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
 	    ? dis_jsr : dis_branch;
       }
   }
+  /* The purpose of placing the check here is to wait for the EVEX prefix for
+     conditional CMP and TEST to be consumed and cleared, and then make a
+     unified judgment. Because they are both in map4, we can not distinguish
+     EVEX prefix for conditional CMP and TEST from others during the
+     EVEX prefix stage of parsing.  */
+  if (ins.evex_type == evex_from_legacy)
+    {
+      /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
+	 all bits of EVEX.vvvv and EVEX.V' must be 1.  */
+      if (!ins.vex.nd && (ins.vex.register_specifier || !ins.vex.v))
+	{
+	  i386_dis_printf (info, dis_style_text, "(bad)");
+	  ret = ins.end_codep - priv.the_buffer;
+	  goto out;
+	}
 
+      /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
+	 lower 2 bits of EVEX.aaa must be 0.  */
+      if ((ins.vex.mask_register_specifier & 0x3) != 0
+	  || ins.vex.ll != 0 || ins.vex.zeroing != 0)
+	{
+	  i386_dis_printf (info, dis_style_text, "(bad)");
+	  ret = ins.end_codep - priv.the_buffer;
+	  goto out;
+	}
+    }
   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
      are all 0s in inverted form.  */
   if (ins.need_vex && ins.vex.register_specifier != 0)
@@ -10216,6 +10233,18 @@  static const char *const fgrps[][8] = {
   },
 };
 
+static const char *const oszc_flags[16] = {
+  " {dfv=}", " {dfv=cf}", " {dfv=zf}", " {dfv=zf, cf}", " {dfv=sf}",
+  " {dfv=sf, cf}", " {dfv=sf, zf}", " {dfv=sf, zf, cf}", " {dfv=of}",
+  " {dfv=of, cf}", " {dfv=of, zf}", " {dfv=of, zf, cf}", " {dfv=of, sf}",
+  " {dfv=of, sf, cf}", " {dfv=of, sf, zf}", " {dfv=of, sf, zf, cf}"
+};
+
+static const char *const scc_suffix[16] = {
+  "o", "no", "b", "ae", "e", "ne", "be", "a", "s", "ns", "t", "f",
+  "l", "ge", "le", "g"
+};
+
 static void
 swap_operand (instr_info *ins)
 {
@@ -10398,6 +10427,23 @@  putop (instr_info *ins, const char *in_template, int sizeflag)
 		*ins->obufp++ = *q;
 	      break;
 	    }
+	  else if (l == 1 && last[0] == 'S')
+	    {
+	      /* Add scc suffix.  */
+	      oappend (ins, scc_suffix[ins->vex.scc]);
+
+	      /* For SCC insns, the ND bit is required to be set to 0.  */
+	      if (ins->vex.nd)
+		oappend (ins, "(bad)");
+
+	      /* These bits have been consumed and should be cleared or restored
+		 to default values.  */
+	      ins->vex.v = 1;
+	      ins->vex.nf = false;
+	      ins->vex.mask_register_specifier = 0;
+	      break;
+	    }
+
 	  if (l)
 	    abort ();
 	  if (ins->intel_syntax && !alt)
@@ -10477,6 +10523,10 @@  putop (instr_info *ins, const char *in_template, int sizeflag)
 		  *ins->obufp++ = '}';
 		  *ins->obufp++ = ' ';
 		  break;
+		case 'N':
+		  /* Skip printing {evex} for some special instructions in MAP4.  */
+		  evex_printed = true;
+		  break;
 		case 'M':
 		  if (ins->modrm.mod != 3 && !(ins->rex2 & 7))
 		    oappend (ins, "{evex} ");
@@ -10532,6 +10582,18 @@  putop (instr_info *ins, const char *in_template, int sizeflag)
 		  evex_printed = true;
 		}
 	    }
+	  else if (l == 1 && last[0] == 'D')
+	    {
+	      /* Get oszc flags value from register_specifier.  */
+	      int oszc_value = ~ins->vex.register_specifier & 0xf;
+
+	      /* Add {dfv=of, sf, zf, cf} flags.  */
+	      oappend (ins, oszc_flags[oszc_value]);
+
+	      /* These bits have been consumed and should be cleared or restored
+		 to default values.  */
+	      ins->vex.register_specifier = 0;
+	    }
 	  else
 	    abort ();
 	  break;
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 38b8e64e755..7400428eb24 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -581,6 +581,8 @@  enum
 #define IMPLICIT_STACK_OP 9
   /* Instruction zeroes upper part of register.  */
 #define ZERO_UPPER 10
+  /* Instruction support SCC.  */
+#define SCC 11
   OperandConstraint,
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index c9106800155..e365f063142 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -86,6 +86,7 @@ 
 #define Ugh               OperandConstraint=UGH
 #define ImplicitStackOp   OperandConstraint=IMPLICIT_STACK_OP
 #define ZU                OperandConstraint=ZERO_UPPER
+#define Scc               OperandConstraint=SCC
 
 #define ATTSyntax         Dialect=ATT_SYNTAX
 #define ATTMnemonic       Dialect=ATT_MNEMONIC
@@ -341,10 +342,28 @@  cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8
 cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+cmp, 0x380a, APX_F, D|W|CheckOperandSize|EVexMap4|Scc|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+cmp, 0x830a/7, APX_F, Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+cmp, 0x800a/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
+<scc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
+         s:8, ns:9, t:a, f:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
+
+ccmp<scc>, 0x380<scc:opc>, APX_F, D|W|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ccmp<scc>, 0x830<scc:opc>/7, APX_F, Modrm|EVexMap4|Scc|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ccmp<scc>, 0x800<scc:opc>/7, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0x840a, 0, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0xf60a/0, 0, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
+ctest<scc>, 0x840<scc:opc>, APX_F, D|W|C|CheckOperandSize|Modrm|EVexMap4|Scc|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ctest<scc>, 0xf60<scc:opc>/0, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ctest<scc>, 0xf60<scc:opc>/1, APX_F, W|Modrm|EVexMap4|Scc|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
+<scc>
 
 <incdec:opc, inc:0, dec:1>