From patchwork Thu Jun 6 09:32:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 91613 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D30CE38F91C3 for ; Thu, 6 Jun 2024 09:27:20 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from zg8tmja2lje4os43os4xodqa.icoremail.net (zg8tmja2lje4os43os4xodqa.icoremail.net [206.189.79.184]) by sourceware.org (Postfix) with ESMTP id 154DA38FC338 for ; Thu, 6 Jun 2024 09:26:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 154DA38FC338 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 154DA38FC338 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=206.189.79.184 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717666002; cv=none; b=uT3nv2QOoK3kI7wM9ZLLRD32UeQTUCXnaT/sefOxW+nhRjYZt+EqjfclxGh9g6HszooNH6IgtgDIXZuWcTH7UUOwoGdZKR51Simq+nXMK63WatTEIsAOeQbNjeEHk1RsVRJwH4BrrHDOd2lr4HebAYpDTa1CZ1JqQIGGzLVVs64= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717666002; c=relaxed/simple; bh=aaccZrqQqH/5lSgAAOWc4bhNIFpO7If2yOCkx/YIW0Y=; h=From:To:Subject:Date:Message-Id; b=i9e+sFXJPTxN1ClaDb5aJ5zC5uv474dB7piV8sUxJ3X9f9XjtDCCb7XmiL/UJYZd00wTLXeIkRmWl3rvXeM+2WU8c6XTZxdEV61jDDXLDtd1VHhQhy/38VuFGgxoJZ/v7ltYiuDKh3hMiJvb5Ubfug157CvITQajihxjQU92rDk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.38]) by app2 (Coremail) with SMTP id TQJkCgCXqbs1gGFmP6YOAA--.40110S5; Thu, 06 Jun 2024 17:24:06 +0800 (CST) From: Xiao Zeng To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, nelson@rivosinc.com, zhengyu@eswincomputing.com, Xiao Zeng Subject: [PATCH 1/2] RISC-V: Add support for Zimop extension Date: Thu, 6 Jun 2024 17:32:37 +0800 Message-Id: <20240606093238.45579-2-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240606093238.45579-1-zengxiao@eswincomputing.com> References: <20240606093238.45579-1-zengxiao@eswincomputing.com> X-CM-TRANSID: TQJkCgCXqbs1gGFmP6YOAA--.40110S5 X-Coremail-Antispam: 1UD129KBjvAXoWftF4furyDWrWxGr1fZFW3GFg_yoW8Zw1UGo WjywsxA3sava929r45Was7XFy8AasIga4UJ3WrX34xW3Z7Jr13Gr1fW3W0vrWUGFyIq3W8 Gwn7Jr4DXFnxCF4Un29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYA7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r18M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbzBT7UUUUU== X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org This implements the Zimop (May-Be-Operations) extension, as of version 1.0. View detailed information in: bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zimop.d: New test. * testsuite/gas/riscv/zimop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_MOP_R_0): Define. (MASK_MOP_R_0): Ditto. (MATCH_MOP_R_1): Ditto. (MASK_MOP_R_1): Ditto. (MATCH_MOP_R_2): Ditto. (MASK_MOP_R_2): Ditto. (MATCH_MOP_R_3): Ditto. (MASK_MOP_R_3): Ditto. (MATCH_MOP_R_4): Ditto. (MASK_MOP_R_4): Ditto. (MATCH_MOP_R_5): Ditto. (MASK_MOP_R_5): Ditto. (MATCH_MOP_R_6): Ditto. (MASK_MOP_R_6): Ditto. (MATCH_MOP_R_7): Ditto. (MASK_MOP_R_7): Ditto. (MATCH_MOP_R_8): Ditto. (MASK_MOP_R_8): Ditto. (MATCH_MOP_R_9): Ditto. (MASK_MOP_R_9): Ditto. (MATCH_MOP_R_10): Ditto. (MASK_MOP_R_10): Ditto. (MATCH_MOP_R_11): Ditto. (MASK_MOP_R_11): Ditto. (MATCH_MOP_R_12): Ditto. (MASK_MOP_R_12): Ditto. (MATCH_MOP_R_13): Ditto. (MASK_MOP_R_13): Ditto. (MATCH_MOP_R_14): Ditto. (MASK_MOP_R_14): Ditto. (MATCH_MOP_R_15): Ditto. (MASK_MOP_R_15): Ditto. (MATCH_MOP_R_16): Ditto. (MASK_MOP_R_16): Ditto. (MATCH_MOP_R_17): Ditto. (MASK_MOP_R_17): Ditto. (MATCH_MOP_R_18): Ditto. (MASK_MOP_R_18): Ditto. (MATCH_MOP_R_19): Ditto. (MASK_MOP_R_19): Ditto. (MATCH_MOP_R_20): Ditto. (MASK_MOP_R_20): Ditto. (MATCH_MOP_R_21): Ditto. (MASK_MOP_R_21): Ditto. (MATCH_MOP_R_22): Ditto. (MASK_MOP_R_22): Ditto. (MATCH_MOP_R_23): Ditto. (MASK_MOP_R_23): Ditto. (MATCH_MOP_R_24): Ditto. (MASK_MOP_R_24): Ditto. (MATCH_MOP_R_25): Ditto. (MASK_MOP_R_25): Ditto. (MATCH_MOP_R_26): Ditto. (MASK_MOP_R_26): Ditto. (MATCH_MOP_R_27): Ditto. (MASK_MOP_R_27): Ditto. (MATCH_MOP_R_28): Ditto. (MASK_MOP_R_28): Ditto. (MATCH_MOP_R_29): Ditto. (MASK_MOP_R_29): Ditto. (MATCH_MOP_R_30): Ditto. (MASK_MOP_R_30): Ditto. (MATCH_MOP_R_31): Ditto. (MASK_MOP_R_31): Ditto. (MATCH_MOP_RR_0): Ditto. (MASK_MOP_RR_0): Ditto. (MATCH_MOP_RR_1): Ditto. (MASK_MOP_RR_1): Ditto. (MATCH_MOP_RR_2): Ditto. (MASK_MOP_RR_2): Ditto. (MATCH_MOP_RR_3): Ditto. (MASK_MOP_RR_3): Ditto. (MATCH_MOP_RR_4): Ditto. (MASK_MOP_RR_4): Ditto. (MATCH_MOP_RR_5): Ditto. (MASK_MOP_RR_5): Ditto. (MATCH_MOP_RR_6): Ditto. (MASK_MOP_RR_6): Ditto. (MATCH_MOP_RR_7): Ditto. (MASK_MOP_RR_7): Ditto. (DECLARE_INSN): New declarations for Zimop. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zimop instructions. --- bfd/elfxx-riscv.c | 5 ++ gas/NEWS | 2 + gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zimop.d | 48 +++++++++++ gas/testsuite/gas/riscv/zimop.s | 43 ++++++++++ include/opcode/riscv-opc.h | 122 +++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 42 +++++++++ 8 files changed, 264 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zimop.d create mode 100644 gas/testsuite/gas/riscv/zimop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 1fe7e5d3df2..87b88513f5c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1358,6 +1358,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2533,6 +2534,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zca"))); case INSN_CLASS_ZIHINTPAUSE: return riscv_subset_supports (rps, "zihintpause"); + case INSN_CLASS_ZIMOP: + return riscv_subset_supports (rps, "zimop"); case INSN_CLASS_M: return riscv_subset_supports (rps, "m"); case INSN_CLASS_ZMMUL: @@ -2773,6 +2776,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("c' or `zca"); case INSN_CLASS_ZIHINTPAUSE: return "zihintpause"; + case INSN_CLASS_ZIMOP: + return "zimop"; case INSN_CLASS_M: return "m"; case INSN_CLASS_ZMMUL: diff --git a/gas/NEWS b/gas/NEWS index 145ce413bff..e6c1507349f 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -19,6 +19,8 @@ * Remove support for RISC-V privileged spec 1.9.1, but linker can still recognize it in case of linking old objects. +* Add support for RISC-V Zimop extension with version 1.0. + * Add support for RISC-V Zcmp extension with version 1.0. * Add support for RISC-V Zfbfmin extension with version 1.0. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index dd82752cd30..dace28179b8 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -20,6 +20,7 @@ All available -march extensions for RISC-V: zihintntl 1.0 zihintpause 2.0 zihpm 2.0 + zimop 1.0 zmmul 1.0 zaamo 1.0 zabha 1.0 diff --git a/gas/testsuite/gas/riscv/zimop.d b/gas/testsuite/gas/riscv/zimop.d new file mode 100644 index 00000000000..becb72ca650 --- /dev/null +++ b/gas/testsuite/gas/riscv/zimop.d @@ -0,0 +1,48 @@ +#as: -march=rv64i_zimop +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+81c5c573[ ]+mop.r.0[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+81d5c573[ ]+mop.r.1[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+81e5c573[ ]+mop.r.2[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+81f5c573[ ]+mop.r.3[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85c5c573[ ]+mop.r.4[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85d5c573[ ]+mop.r.5[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85e5c573[ ]+mop.r.6[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+85f5c573[ ]+mop.r.7[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89c5c573[ ]+mop.r.8[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89d5c573[ ]+mop.r.9[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89e5c573[ ]+mop.r.10[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+89f5c573[ ]+mop.r.11[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8dc5c573[ ]+mop.r.12[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8dd5c573[ ]+mop.r.13[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8de5c573[ ]+mop.r.14[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+8df5c573[ ]+mop.r.15[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1c5c573[ ]+mop.r.16[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1d5c573[ ]+mop.r.17[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1e5c573[ ]+mop.r.18[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c1f5c573[ ]+mop.r.19[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5c5c573[ ]+mop.r.20[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5d5c573[ ]+mop.r.21[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5e5c573[ ]+mop.r.22[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c5f5c573[ ]+mop.r.23[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9c5c573[ ]+mop.r.24[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9d5c573[ ]+mop.r.25[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9e5c573[ ]+mop.r.26[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+c9f5c573[ ]+mop.r.27[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cdc5c573[ ]+mop.r.28[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cdd5c573[ ]+mop.r.29[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cde5c573[ ]+mop.r.30[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+cdf5c573[ ]+mop.r.31[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+82c5c573[ ]+mop.rr.0[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+86c5c573[ ]+mop.rr.1[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+8ac5c573[ ]+mop.rr.2[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+8ec5c573[ ]+mop.rr.3[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+c2c5c573[ ]+mop.rr.4[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+c6c5c573[ ]+mop.rr.5[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+cac5c573[ ]+mop.rr.6[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+cec5c573[ ]+mop.rr.7[ ]+a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/zimop.s b/gas/testsuite/gas/riscv/zimop.s new file mode 100644 index 00000000000..d244c1fb0fb --- /dev/null +++ b/gas/testsuite/gas/riscv/zimop.s @@ -0,0 +1,43 @@ +target: + # mop.r.n + mop.r.0 a0, a1 + mop.r.1 a0, a1 + mop.r.2 a0, a1 + mop.r.3 a0, a1 + mop.r.4 a0, a1 + mop.r.5 a0, a1 + mop.r.6 a0, a1 + mop.r.7 a0, a1 + mop.r.8 a0, a1 + mop.r.9 a0, a1 + mop.r.10 a0, a1 + mop.r.11 a0, a1 + mop.r.12 a0, a1 + mop.r.13 a0, a1 + mop.r.14 a0, a1 + mop.r.15 a0, a1 + mop.r.16 a0, a1 + mop.r.17 a0, a1 + mop.r.18 a0, a1 + mop.r.19 a0, a1 + mop.r.20 a0, a1 + mop.r.21 a0, a1 + mop.r.22 a0, a1 + mop.r.23 a0, a1 + mop.r.24 a0, a1 + mop.r.25 a0, a1 + mop.r.26 a0, a1 + mop.r.27 a0, a1 + mop.r.28 a0, a1 + mop.r.29 a0, a1 + mop.r.30 a0, a1 + mop.r.31 a0, a1 + # mop.rr.n + mop.rr.0 a0, a1, a2 + mop.rr.1 a0, a1, a2 + mop.rr.2 a0, a1, a2 + mop.rr.3 a0, a1, a2 + mop.rr.4 a0, a1, a2 + mop.rr.5 a0, a1, a2 + mop.rr.6 a0, a1, a2 + mop.rr.7 a0, a1, a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e8c08e800c6..8ba95399430 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2360,6 +2360,87 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff +/* Zimop instructions. */ +#define MATCH_MOP_R_0 0x81c04073 +#define MASK_MOP_R_0 0xfff0707f +#define MATCH_MOP_R_1 0x81d04073 +#define MASK_MOP_R_1 0xfff0707f +#define MATCH_MOP_R_2 0x81e04073 +#define MASK_MOP_R_2 0xfff0707f +#define MATCH_MOP_R_3 0x81f04073 +#define MASK_MOP_R_3 0xfff0707f +#define MATCH_MOP_R_4 0x85c04073 +#define MASK_MOP_R_4 0xfff0707f +#define MATCH_MOP_R_5 0x85d04073 +#define MASK_MOP_R_5 0xfff0707f +#define MATCH_MOP_R_6 0x85e04073 +#define MASK_MOP_R_6 0xfff0707f +#define MATCH_MOP_R_7 0x85f04073 +#define MASK_MOP_R_7 0xfff0707f +#define MATCH_MOP_R_8 0x89c04073 +#define MASK_MOP_R_8 0xfff0707f +#define MATCH_MOP_R_9 0x89d04073 +#define MASK_MOP_R_9 0xfff0707f +#define MATCH_MOP_R_10 0x89e04073 +#define MASK_MOP_R_10 0xfff0707f +#define MATCH_MOP_R_11 0x89f04073 +#define MASK_MOP_R_11 0xfff0707f +#define MATCH_MOP_R_12 0x8dc04073 +#define MASK_MOP_R_12 0xfff0707f +#define MATCH_MOP_R_13 0x8dd04073 +#define MASK_MOP_R_13 0xfff0707f +#define MATCH_MOP_R_14 0x8de04073 +#define MASK_MOP_R_14 0xfff0707f +#define MATCH_MOP_R_15 0x8df04073 +#define MASK_MOP_R_15 0xfff0707f +#define MATCH_MOP_R_16 0xc1c04073 +#define MASK_MOP_R_16 0xfff0707f +#define MATCH_MOP_R_17 0xc1d04073 +#define MASK_MOP_R_17 0xfff0707f +#define MATCH_MOP_R_18 0xc1e04073 +#define MASK_MOP_R_18 0xfff0707f +#define MATCH_MOP_R_19 0xc1f04073 +#define MASK_MOP_R_19 0xfff0707f +#define MATCH_MOP_R_20 0xc5c04073 +#define MASK_MOP_R_20 0xfff0707f +#define MATCH_MOP_R_21 0xc5d04073 +#define MASK_MOP_R_21 0xfff0707f +#define MATCH_MOP_R_22 0xc5e04073 +#define MASK_MOP_R_22 0xfff0707f +#define MATCH_MOP_R_23 0xc5f04073 +#define MASK_MOP_R_23 0xfff0707f +#define MATCH_MOP_R_24 0xc9c04073 +#define MASK_MOP_R_24 0xfff0707f +#define MATCH_MOP_R_25 0xc9d04073 +#define MASK_MOP_R_25 0xfff0707f +#define MATCH_MOP_R_26 0xc9e04073 +#define MASK_MOP_R_26 0xfff0707f +#define MATCH_MOP_R_27 0xc9f04073 +#define MASK_MOP_R_27 0xfff0707f +#define MATCH_MOP_R_28 0xcdc04073 +#define MASK_MOP_R_28 0xfff0707f +#define MATCH_MOP_R_29 0xcdd04073 +#define MASK_MOP_R_29 0xfff0707f +#define MATCH_MOP_R_30 0xcde04073 +#define MASK_MOP_R_30 0xfff0707f +#define MATCH_MOP_R_31 0xcdf04073 +#define MASK_MOP_R_31 0xfff0707f +#define MATCH_MOP_RR_0 0x82004073 +#define MASK_MOP_RR_0 0xfe00707f +#define MATCH_MOP_RR_1 0x86004073 +#define MASK_MOP_RR_1 0xfe00707f +#define MATCH_MOP_RR_2 0x8a004073 +#define MASK_MOP_RR_2 0xfe00707f +#define MATCH_MOP_RR_3 0x8e004073 +#define MASK_MOP_RR_3 0xfe00707f +#define MATCH_MOP_RR_4 0xc2004073 +#define MASK_MOP_RR_4 0xfe00707f +#define MATCH_MOP_RR_5 0xc6004073 +#define MASK_MOP_RR_5 0xfe00707f +#define MATCH_MOP_RR_6 0xca004073 +#define MASK_MOP_RR_6 0xfe00707f +#define MATCH_MOP_RR_7 0xce004073 +#define MASK_MOP_RR_7 0xfe00707f /* Zawrs instructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff @@ -3981,6 +4062,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) +/* Zimop instructions. */ +DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0) +DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1) +DECLARE_INSN(MOP_R_2, MATCH_MOP_R_2, MASK_MOP_R_2) +DECLARE_INSN(MOP_R_3, MATCH_MOP_R_3, MASK_MOP_R_3) +DECLARE_INSN(MOP_R_4, MATCH_MOP_R_4, MASK_MOP_R_4) +DECLARE_INSN(MOP_R_5, MATCH_MOP_R_5, MASK_MOP_R_5) +DECLARE_INSN(MOP_R_6, MATCH_MOP_R_6, MASK_MOP_R_6) +DECLARE_INSN(MOP_R_7, MATCH_MOP_R_7, MASK_MOP_R_7) +DECLARE_INSN(MOP_R_8, MATCH_MOP_R_8, MASK_MOP_R_8) +DECLARE_INSN(MOP_R_9, MATCH_MOP_R_9, MASK_MOP_R_9) +DECLARE_INSN(MOP_R_10, MATCH_MOP_R_10, MASK_MOP_R_10) +DECLARE_INSN(MOP_R_11, MATCH_MOP_R_11, MASK_MOP_R_11) +DECLARE_INSN(MOP_R_12, MATCH_MOP_R_12, MASK_MOP_R_12) +DECLARE_INSN(MOP_R_13, MATCH_MOP_R_13, MASK_MOP_R_13) +DECLARE_INSN(MOP_R_14, MATCH_MOP_R_14, MASK_MOP_R_14) +DECLARE_INSN(MOP_R_15, MATCH_MOP_R_15, MASK_MOP_R_15) +DECLARE_INSN(MOP_R_16, MATCH_MOP_R_16, MASK_MOP_R_16) +DECLARE_INSN(MOP_R_17, MATCH_MOP_R_17, MASK_MOP_R_17) +DECLARE_INSN(MOP_R_18, MATCH_MOP_R_18, MASK_MOP_R_18) +DECLARE_INSN(MOP_R_19, MATCH_MOP_R_19, MASK_MOP_R_19) +DECLARE_INSN(MOP_R_20, MATCH_MOP_R_20, MASK_MOP_R_20) +DECLARE_INSN(MOP_R_21, MATCH_MOP_R_21, MASK_MOP_R_21) +DECLARE_INSN(MOP_R_22, MATCH_MOP_R_22, MASK_MOP_R_22) +DECLARE_INSN(MOP_R_23, MATCH_MOP_R_23, MASK_MOP_R_23) +DECLARE_INSN(MOP_R_24, MATCH_MOP_R_24, MASK_MOP_R_24) +DECLARE_INSN(MOP_R_25, MATCH_MOP_R_25, MASK_MOP_R_25) +DECLARE_INSN(MOP_R_26, MATCH_MOP_R_26, MASK_MOP_R_26) +DECLARE_INSN(MOP_R_27, MATCH_MOP_R_27, MASK_MOP_R_27) +DECLARE_INSN(MOP_R_28, MATCH_MOP_R_28, MASK_MOP_R_28) +DECLARE_INSN(MOP_R_29, MATCH_MOP_R_29, MASK_MOP_R_29) +DECLARE_INSN(MOP_R_30, MATCH_MOP_R_30, MASK_MOP_R_30) +DECLARE_INSN(MOP_R_31, MATCH_MOP_R_31, MASK_MOP_R_31) +DECLARE_INSN(MOP_RR_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) +DECLARE_INSN(MOP_RR_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) +DECLARE_INSN(MOP_RR_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) +DECLARE_INSN(MOP_RR_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) +DECLARE_INSN(MOP_RR_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) +DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) +DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) +DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 33df56d13af..2b2ed0dbce8 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -437,6 +437,7 @@ enum riscv_insn_class INSN_CLASS_ZIHINTNTL, INSN_CLASS_ZIHINTNTL_AND_C, INSN_CLASS_ZIHINTPAUSE, + INSN_CLASS_ZIMOP, INSN_CLASS_ZMMUL, INSN_CLASS_ZAAMO, INSN_CLASS_ZALRSC, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index ff08bd595c0..45269e095a6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1090,6 +1090,48 @@ const struct riscv_opcode riscv_opcodes[] = {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, +/* Zimop instructions. */ +{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, +{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, +{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, +{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, +{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, +{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, +{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, +{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, +{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, +{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, +{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, +{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, +{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, +{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, +{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, +{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, +{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, +{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, +{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, +{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, +{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, +{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, +{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, +{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, +{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, +{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, +{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, +{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, +{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, +{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, +{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, +{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, +{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, +{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, +{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, +{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, +{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, +{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, +{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, +{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, + /* Zawrs instructions. */ {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },