From patchwork Wed Jun 5 01:36:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 91517 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 98E02391C7F6 for ; Wed, 5 Jun 2024 01:31:02 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from zg8tmtu5ljy1ljeznc42.icoremail.net (zg8tmtu5ljy1ljeznc42.icoremail.net [159.65.134.6]) by sourceware.org (Postfix) with ESMTP id 6F6633A72103 for ; Wed, 5 Jun 2024 01:30:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6F6633A72103 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6F6633A72103 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.65.134.6 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717551035; cv=none; b=n1AnJh28XNohl/PPyfTUo2d1PZ8aTIDx8wbq5aQksBgcfzXbmuerMOoD3brQiN6A8l6SECKMnoHUc7jhgn8D7cDK1qU3xmLp6bbND245wjxpQMiVVkTNtElbGPjpt7FSchZVIrUgMTzGXuNwdhlHQMVe4XXqC4ZBx6+mEsSR1rY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717551035; c=relaxed/simple; bh=2KzHJMbTgkp4AasEmBkOWqA+PRePFgrm42LbVFYjnC8=; h=From:To:Subject:Date:Message-Id; b=vejQWvys5YH1/O0L3P1U6Ma4Qv5ov3zvT6amwjfwk+OiwtmTxfWVJ95w4RPriQDJGxCXngMRrBZ+tRUv9Nx0XgXXCBqS2LSf4E2iS0ubD72CH8JscEghQDnWpER1h4BlZI5AR+kyCM4nEVRmsycTW6bMZf+6YhJsl31KmC/Y4to= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.38]) by app1 (Coremail) with SMTP id TAJkCgBX+OQPv19m6F0OAA--.37881S6; Wed, 05 Jun 2024 09:27:48 +0800 (CST) From: Xiao Zeng To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, nelson@rivosinc.com, zhengyu@eswincomputing.com, Xiao Zeng Subject: [PING] [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension Date: Wed, 5 Jun 2024 09:36:12 +0800 Message-Id: <20240605013613.78830-3-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605013613.78830-1-zengxiao@eswincomputing.com> References: <20240605013613.78830-1-zengxiao@eswincomputing.com> X-CM-TRANSID: TAJkCgBX+OQPv19m6F0OAA--.37881S6 X-Coremail-Antispam: 1UD129KBjvJXoWxKryfur15Cr48tr4kZr4ktFb_yoWfuFy8pa 1ku3Z2krZ5JFnrtrs3KF1UKF42vws2grn09rWS9w4fAw4fGrWDtFnrt3s3AF48XF47Kw1a 9a1ayrWrZrWDA3JanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU873vUUUUU X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5, RCVD_IN_VALIDITY_RPBL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org This implements the Zvfbfmin extension, as of version 1.0. View detailed information in: Depending on different usage scenarios, the Zvfbfmin extension may depend on 'V' or 'Zve32f'. This patch only implements dependencies in scenario of Embedded Processor. In scenario of Application Processor, it is necessary to explicitly indicate the dependent 'V' extension. For relevant information in gcc, please refer to: bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zvfbfmin-rv32.d: New test. * testsuite/gas/riscv/zvfbfmin-rv32.s: New test. * testsuite/gas/riscv/zvfbfmin-rv64.d: New test. * testsuite/gas/riscv/zvfbfmin-rv64.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. (MASK_VFNCVTBF16_F_F_W): Ditto. (MATCH_VFWCVTBF16_F_F_V): Ditto. (MASK_VFWCVTBF16_F_F_V): Ditto. (DECLARE_INSN): New declarations for Zvfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZVFBFMIN opcodes/ChangeLog: * riscv-opc.c: Add Zvfbfmin instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/NEWS | 2 ++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zvfbfmin-rv32.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvfbfmin-rv32.s | 7 +++++++ gas/testsuite/gas/riscv/zvfbfmin-rv64.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvfbfmin-rv64.s | 7 +++++++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 10 files changed, 60 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.d create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.s create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.d create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index d9709a232e6..3d303f02b58 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, {"zabha", "a", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, {"zvfh", "zvfhmin", check_implicit_always}, {"zvfh", "zfhmin", check_implicit_always}, {"zvfhmin", "zve32f", check_implicit_always}, @@ -1394,6 +1395,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2644,6 +2646,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVFBFMIN: + return riscv_subset_supports (rps, "zvfbfmin"); case INSN_CLASS_ZVKB: return riscv_subset_supports (rps, "zvkb"); case INSN_CLASS_ZVKG: @@ -2908,6 +2912,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVFBFMIN: + return "zvfbfmin"; case INSN_CLASS_ZVKB: return _("zvkb"); case INSN_CLASS_ZVKG: diff --git a/gas/NEWS b/gas/NEWS index b88c54fc5c3..2c75966d0ce 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for RISC-V Zvfbfmin extension with version 1.0. + * Add support for RISC-V Zfbfmin extension with version 1.0. * In x86 Intel syntax undue mnemonic suffixes are now warned about. This is diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 9deaa841622..1a2ac1eaa08 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -59,6 +59,7 @@ All available -march extensions for RISC-V: zvbb 1.0 zvbc 1.0 zvfh 1.0 + zvfbfmin 1.0 zvfhmin 1.0 zvkb 1.0 zvkg 1.0 diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.d b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d new file mode 100644 index 00000000000..b52e19d30be --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d @@ -0,0 +1,12 @@ +#as: -march=rv32i_zvfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.s b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s new file mode 100644 index 00000000000..9a4493d84d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s @@ -0,0 +1,7 @@ +target: + # vfncvtbf16.f.f.w + vfncvtbf16.f.f.w v4, v8 + vfncvtbf16.f.f.w v4, v8, v0.t + # vfwcvtbf16.f.f.v + vfwcvtbf16.f.f.v v4, v8 + vfwcvtbf16.f.f.v v4, v8, v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.d b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d new file mode 100644 index 00000000000..ce973812fe1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d @@ -0,0 +1,12 @@ +#as: -march=rv64iv_zvfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.s b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s new file mode 100644 index 00000000000..9a4493d84d1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s @@ -0,0 +1,7 @@ +target: + # vfncvtbf16.f.f.w + vfncvtbf16.f.f.w v4, v8 + vfncvtbf16.f.f.w v4, v8, v0.t + # vfwcvtbf16.f.f.v + vfwcvtbf16.f.f.v v4, v8 + vfwcvtbf16.f.f.v v4, v8, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 26d60bc585e..32b971fb2b3 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2370,6 +2370,11 @@ #define MASK_FCVT_BF16_S 0xfff0007f #define MATCH_FCVT_S_BF16 0x40600053 #define MASK_FCVT_S_BF16 0xfff0007f +/* Zvfbfmin intructions. */ +#define MATCH_VFNCVTBF16_F_F_W 0x480e9057 +#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f +#define MATCH_VFWCVTBF16_F_F_V 0x48069057 +#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f /* Vendor-specific (CORE-V) Xcvmac instructions. */ #define MATCH_CV_MAC 0x9000302b #define MASK_CV_MAC 0xfe00707f @@ -3920,6 +3925,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) /* Zfbfmin instructions. */ DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) +/* Zvfbfmin instructions. */ +DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) +DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) /* Zvbb/Zvkb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 0e58dbe3d03..4d21b6c3926 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -471,6 +471,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVFBFMIN, INSN_CLASS_ZVKB, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 9f99aa6c792..0a470aee7cc 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2041,6 +2041,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0}, {"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0}, +/* Zvfbfmin instructions. */ +{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, +{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, + /* Zvkg instructions. */ {"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0}, {"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},