From patchwork Tue May 28 14:45:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saurabh Jha X-Patchwork-Id: 91023 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9728A384AB4C for ; Tue, 28 May 2024 14:48:11 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2056.outbound.protection.outlook.com [40.107.22.56]) by sourceware.org (Postfix) with ESMTPS id 5955538654A4 for ; Tue, 28 May 2024 14:47:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5955538654A4 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5955538654A4 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.22.56 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1716907657; cv=pass; b=AbxzwQpAqWWFbheb9YsrRn63Ivl+j0qvc33KQdiZfS/0l8wobSB6rDzXbsh7+rm8gY8Eiu7XrSK1NjiV9dKTlMaFBMMOgHJfa4BjYho9oE4V9dyYOzftIHsos2nCrQrhqekLO/TDwLJFYIBkPD1NKlMXcAPl4WdY6qUDh9RLZf0= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1716907657; c=relaxed/simple; bh=4BFye4p9IZa0keV3rq2Hnwb1C+q7u+DDB+8OHNNHbDM=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=wxOfJCVZLIMYSwgD/GklTP2XCF9WkP6mxylzsduRZhfp/puxDYUQ2A4CZ70+zal9Pc1R4cqS+Sg3ne24UB6Gzdid343h+KSVk8taFsLrfoU0KtGbcTCT0Q3ixruRZZxT9DdVXogDDuO1fpqVF5tCw+DOjrhTNCD9A8MUIBFswAw= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=fZXdsITKiUqrj0drWovgBfs7g4HsFPEFd1w4ITZgZKmbnICMW5xO9COgR9hFncPKfXRyIAnYKT/KaC/XT6ET8xlFFreEFogf6/ZbYu9H/8xVFuZEmEs2Xl2IFGaqf0lZTHiqPzujgalDlSLE89wupePiGZu4gl4jltC5bkeMxPccgbJodhREH8uSDGMmlK0pjh4HDTs8a2+vuGJ982Oq3vH1YFCozeW4cD820O+r9glQuLdw92CdvRzfrgSd7KqZt05n225tGLgdbR2MRVHsz6xLJpPE/uAbm1O+tyne/zSAU2aAX8MT4onrgJ1H/350ShMvkJ9bChLchayc8FlhhQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dHS9OmBiKnfgRAroZrphTtxr/waFugf+PjiDFfTv7mM=; b=RJqS9NHn2i9IALs+1QOthswynCLWbCuNkP8c+Gk+IIz8Rmiw9pDwRYGRPeoTJbkMBas9TMO0x2G5yup2H/HV/k6bcfkKtBUYvIffadJU87Ys8aLuBdv5t/j1iA7Dtmi1oMCVQdkxPgxghCG+hnkYKVUiTdUCOmYDEAXtbmb3Awkl9wCc0MXzRu/U10xNGda11k0tA8QaaGxs8/EpnhU99Ib4sGwrgAXRENjBuClYuc9ciZrQ7jXoiQ9AByx3oS33uWQUBvQbEhnwKeKPTcs7h6dLf/fgmDdL+AYxaifo4LxvYJ3OJgx0pNJ2R6RfOlFyIl7xxoT2ascDZj8F63IFxA== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dHS9OmBiKnfgRAroZrphTtxr/waFugf+PjiDFfTv7mM=; b=GpehN1PV10vzQckupCvh9s89MYZS4nRcazQO0qUD1wnXVPZHKMocnngby0NPL++x7UZqL98eBRSrBMoEYUhpwUc1mMN863wdHtJf3iADNgWAIMNbY55S+1yzo+qx4D/Or9HwtgHuaPyX0GLXo5PBoKz2gMlVbqMAGfuTMceNcxk= Received: from AS9PR04CA0071.eurprd04.prod.outlook.com (2603:10a6:20b:48b::20) by AS8PR08MB6264.eurprd08.prod.outlook.com (2603:10a6:20b:29a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30; Tue, 28 May 2024 14:47:26 +0000 Received: from AMS1EPF00000047.eurprd04.prod.outlook.com (2603:10a6:20b:48b:cafe::df) by AS9PR04CA0071.outlook.office365.com (2603:10a6:20b:48b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29 via Frontend Transport; Tue, 28 May 2024 14:47:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AMS1EPF00000047.mail.protection.outlook.com (10.167.16.135) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.7633.15 via Frontend Transport; Tue, 28 May 2024 14:47:26 +0000 Received: ("Tessian outbound 57d5075de207:v327"); Tue, 28 May 2024 14:47:26 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: fa4ae11092642948 X-CR-MTA-TID: 64aa7808 Received: from b86f3a8bceeb.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 7FFB7311-4F09-4B8D-B451-B5B20B18ABAA.1; Tue, 28 May 2024 14:47:19 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id b86f3a8bceeb.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 28 May 2024 14:47:19 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Saq1UkExg/bf67Tb5QWl+Ni1jfKiMsVJrLlI2P7uiAhxMDNJGJ6LStZ6lowgOOpPMYseGNZriRZy+fJwqHuEfELPjDmFaWGvicVHe2SWXA8HclOQqCMfcULnMStas86Dj94cBkioLL0B61VqOSrLjNYep0TSUwnCVetXIgG7nVGDzHI63svgZCHPZAHEqHGhTs/rrXmaGutDjR12n3ATfkx3lTwL7OA57/b1n0Kse2Me3HBwl2rTqHA8p6LYit0NbDM0XS4TkJALgG5dIeJAKyl5v7wSdyRWoTI5vpBxjPGWjOq9nDO5bxhULTBacu7hEeNWTGzB+IE5859DnJc4JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dHS9OmBiKnfgRAroZrphTtxr/waFugf+PjiDFfTv7mM=; b=NGECrT6wYGjiihwfBjbSVypkLVyR83XQX6svlDqa1emvSOk8ziYckW7EZm2fP4DDSAH0PZMrVpReDC+i5KfFXODxZNb8t0lLEA5AjWUlEDPyCjJJsZhkj8SmwD0AdwlDSXC3N/jFiyiT5mlFDo+hG6K1jOJUA+ba2U3tZQcF5oIcUQpJQquKhkDvA5khbjuow+LWsnUwIW/2B7IwWV8CKEg88GtP2y+f45Njcxrsai2AG4QOKTxwxaZq/hHf7PM9HhGHc8PGBS6QH6tGEhA5sJDm3xm1DzcQvDVpYaZW7V8HDuw+XtnxGvz2w+Xc/YR7811eoHWNAaPBS3SO1oiL/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dHS9OmBiKnfgRAroZrphTtxr/waFugf+PjiDFfTv7mM=; b=GpehN1PV10vzQckupCvh9s89MYZS4nRcazQO0qUD1wnXVPZHKMocnngby0NPL++x7UZqL98eBRSrBMoEYUhpwUc1mMN863wdHtJf3iADNgWAIMNbY55S+1yzo+qx4D/Or9HwtgHuaPyX0GLXo5PBoKz2gMlVbqMAGfuTMceNcxk= Received: from DUZPR01CA0043.eurprd01.prod.exchangelabs.com (2603:10a6:10:468::6) by DB3PR08MB8940.eurprd08.prod.outlook.com (2603:10a6:10:431::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29; Tue, 28 May 2024 14:47:14 +0000 Received: from DB1PEPF000509E8.eurprd03.prod.outlook.com (2603:10a6:10:468:cafe::fd) by DUZPR01CA0043.outlook.office365.com (2603:10a6:10:468::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30 via Frontend Transport; Tue, 28 May 2024 14:47:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DB1PEPF000509E8.mail.protection.outlook.com (10.167.242.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7633.15 via Frontend Transport; Tue, 28 May 2024 14:47:14 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 28 May 2024 14:47:11 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 28 May 2024 14:47:11 +0000 Received: from e130340.cambridge.arm.com (10.2.80.47) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 28 May 2024 14:47:11 +0000 From: To: CC: , Saurabh Jha Subject: [PATCH v7 3/4] gas, aarch64: Add SVE2 lut extension Date: Tue, 28 May 2024 15:45:52 +0100 Message-ID: <20240528144553.2994250-3-saurabh.jha@arm.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240528144553.2994250-1-saurabh.jha@arm.com> References: <20240528144553.2994250-1-saurabh.jha@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DB1PEPF000509E8:EE_|DB3PR08MB8940:EE_|AMS1EPF00000047:EE_|AS8PR08MB6264:EE_ X-MS-Office365-Filtering-Correlation-Id: 3697d95d-c5b5-45e9-4e38-08dc7f2517af x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230031|1800799015|82310400017|36860700004|376005; X-Microsoft-Antispam-Message-Info-Original: iXQzOo0F68LC7RKqG+Fwo9NnhbviFIU+gb8+4Ssg3weGbaVxaBmU/6RAbjfkqTx9SgDtfKbAnmn7us7x725bmQSpJG4IaV6Kz4FkkOX7M0U/osWLpbcqLUZ91aXia/T0FgZ6Ig8ilDDJKksVKboGZbANY0xaK4PiceMBAMVq5lwsJKm4jFI3qfeW6RLgVIzyTOURHR3d5VHAyGnwzEyR3VUhiY0r4kx2ojBeJD4k5woscCKRbdPM8XZlXggsEzyWAXzBOEizypNw9LBfpD1hC9wmKXsmb5cfmw6p5Zn3ZgWoZXSlj6mTZLMPw0jLrdSA9LnbTaEnQTUV5sBZ5sZHBtm9pHdeHUkvjDsETWI6yDEvvTG9oRZO3rfPfEOKGedz7b/XfhTwSXagkYE4LZ8oE9O4knq316srjjrMx49NLKzZ1D2kdT1KWtRP1FBGWzPtMqnaWobzm++fsL7SgayhDBAXQzNE8IB8fCvL9NPPsF9VxqAmw1U+CmgF123VQ5wL4xys+KoH66yRXfg7qaZ/jwIKBFZl6YQCxFvuN4gs6Ps9tgyDxXbWLiagu5r3Vao6zA1zeaGoAk9LYB7TutTFAbYXgxpCJqpMiYppAUvvCTNb6Wv8CeBFMZFCYSfc/NXHW79KhFTB5V/u8UX6fqtw6zb8MEpCZq0US5MrMHdMAQw4ExSA4Q/KarxIo6Vv4ObCio6H+/og/qTlsjePVPijdYWS9hK80NRFkIGpJHJLE+DxdntODML5r/IzX/jiFoP7Tq4N3EfcNwiAIunU4/qKwKHaKNPV92+gDmQ7pUhvpwZwUM8g2e/B9SLOSeRpcGqa6s8oT1gUClMgGmpYHkgrs3yB9AQ8gVOozzZxT9r1jWjUcrmG6FDWqpt9jEu+R0wrZM7ThOi5GCd303qLcLs+5vR84mzsBp0C2zSpFDEDMup6wxmSEBt95VB5vM0/4v0dHHWGi6T9laBOSECSwMwJMmacJHrSPf88UbcoOV2ZGdehXH4uniHO01CL5Fhfx3LtNjMpAg53If9beqqpBFHB3wJweirfvCCG94Xl+U/PrDlZLHxsEFHi5XOXvLV5lijgcWOS3nb3mKV4zu012Iim+IICiljA6LUut58d7tAkTMP++ZA1xEs9sgo46TxKlv0OdbBvRllWK8lvEv3SD0n9uAeu/Khv+nIcbVed82h6ZDt4FGO5PF47F0xfHoEbQ7q7Khq8/gdYfAJdSh5uuKOapMStsX7xD2g4UO1D+/KeACLnMydLaMYtpB3rIFFdWeUHiV7fxka+1pnitsWRctdMDzLDPBgkPCMBReym6c5JIZzGC7+x2vdOp5k5FHgf/JAbboPf8LD8HqX++TshiVdjhw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(82310400017)(36860700004)(376005); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR08MB8940 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS1EPF00000047.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 4deabf3d-b839-4635-30c1-08dc7f25104a X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|376005|35042699013|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: =?utf-8?q?ShXdWr0VCxPmW8tQwHxEj+p8u7rzff1?= =?utf-8?q?nEfkE3bf8EebYi9tdujxw26TnffaQTNtFS+R+l1dml9mzZCBu6G2++jwtksVS40YL?= =?utf-8?q?452KLFqnJXHIB1+AVrj9fPCoenktylT6ThqKpZ9YtM2QUPoAl0grlVz09nO2wSVuQ?= =?utf-8?q?j18mpZbDJU8il7EvBR7+uTAmO9HrTWnIDImJca9aO1Rcpr7OLOC8XPGKXxMhPmkFw?= =?utf-8?q?cQMaOY2DVyPX6aGbpKdpgURU7SH+spNu57TwOjHAmDYD0Q2GV3qyx0bL2rbMtDPf4?= =?utf-8?q?ry9moDOSR4Qfkjn17YoY0zPx7TuEOSTlLnv3eHvOTKjtZgE69E9fDq0HP2gyOHQlK?= =?utf-8?q?DrX1D5djHhJl2A4aPRC6wZRT2Dt31FSG8MC7tTjm3B2sEZK4dE5XIfIhhS+jIJMD5?= =?utf-8?q?BDeJrvbz9oi99eLBY3pUI7dWh3zwsWkT2fjf+59deY9wr8SvSGHIasjwg7OoEWak5?= =?utf-8?q?+YKeg/fOKdOaYvuVAC7LN4tqWlmurscIC8yjfyESv0kJOjBj/pUeeQivRuCtXIePe?= =?utf-8?q?ZijHS4PVjQIKcLF2uoSaKcJEP2eAxAMIQRIsqWxImpNeOORJMlkr4BhwZON7Gpgoa?= =?utf-8?q?QtIzDSfnDTVd9tcyoHpARvRzCwEW0LINlOMvIVKMYeJ4y4j5uPRJpAvPXoHDQdP7W?= =?utf-8?q?igHtXP2xdT+vVx2/KpBMp1aktjTJi4e77n3J+A2t+txU/Twk3acJBbxMdmmRG8ZFe?= =?utf-8?q?ThLwLo1BDo0lZRnskvV272Zzm5yLBJNTaZTTa5q1l25U2lLXA7JCVvBarWivo/1sa?= =?utf-8?q?FcUYY//V8QJd5tkJXicsg1PKdL4ts+T8ptmeDn1HuiVGKOoGFfMGhd3NWzAB5exVJ?= =?utf-8?q?iJKs+L4q92fLu5EYrzBxeTejaRofom8UgF4rWiKC6hMOaCps4AacRN/lex/FJaiu2?= =?utf-8?q?MGt06MVraBASVgS0U7Gz71NZVj/R5hSGIdrvucdycJp+MGQAC7GJj1VSh8qxsGmA0?= =?utf-8?q?s5lhx2VEBP7/kY/XRByvWD6KkxX1LAICyAzTyc1u5+PHka7McKG9JZ0RNoLUZhjEh?= =?utf-8?q?XQ37J5Wg7GXFiPI4Xic3LzkSpRV2hSU2KWILmq33kPxy7IrqyK6cwK0+PI1gSOfSs?= =?utf-8?q?uvSkbshVadWxwp21pWWSziIMdYkbwPwVMZYMTP7zKp1v4L7Yh954Aqr3EJUvPDDXr?= =?utf-8?q?Klw7IegiOfY4hENqEUEFQ09KKdS1wNn39eekSnbk2g+zKQ1VnjlKiS/ZPgA29HlS8?= =?utf-8?q?VM6Efo4YYopilbCLoAD6Xyos64jkd5G+LCZrgz1xMBuuFR0NTGghP7WdxvLe0OVZq?= =?utf-8?q?mvnA/7aR9G2SV8IF8zxrzF5dlpG6Ox/Xd2A=3D=3D?= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(1800799015)(376005)(35042699013)(82310400017)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2024 14:47:26.6243 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3697d95d-c5b5-45e9-4e38-08dc7f2517af X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000047.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6264 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions use new SVE2 vector operands. They are called SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have 1 bit, 2 bit, and 3 bit indices respectively. The lsb and width of these new operands are the same as many existing operands but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h. We made a design choice for the second operand of the halfword variant of luti4 with two register tables. We could have either defined a new operand, like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With the new operand, we would need to implement constraints on register lists based on either operand or opcode flag. With existing operand, we could just existing constraint checks using opcode flag. We chose the second approach and went with SVE_ZnxN and added opcode flag to enforce lengths of vector register list operands. This way, we can reuse the existing constraint check logic. --- Hi, Regression tested for aarch64-none-elf and found no regressions. Ok for binutils-master? I don't have commit access so can someone please commit on my behalf? Regards, Saurabh --- gas/config/tc-aarch64.c | 3 + gas/testsuite/gas/aarch64/sme2-8-invalid.l | 2 +- gas/testsuite/gas/aarch64/sve2-lut-bad.d | 3 + gas/testsuite/gas/aarch64/sve2-lut-bad.l | 34 +++ gas/testsuite/gas/aarch64/sve2-lut-illegal.d | 3 + gas/testsuite/gas/aarch64/sve2-lut-illegal.l | 212 +++++++++++++++++++ gas/testsuite/gas/aarch64/sve2-lut-illegal.s | 128 +++++++++++ gas/testsuite/gas/aarch64/sve2-lut.d | 41 ++++ gas/testsuite/gas/aarch64/sve2-lut.s | 39 ++++ include/opcode/aarch64.h | 3 + opcodes/aarch64-opc.c | 20 ++ opcodes/aarch64-opc.h | 4 + opcodes/aarch64-tbl.h | 36 +++- 13 files changed, 526 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sve2-lut-bad.d create mode 100644 gas/testsuite/gas/aarch64/sve2-lut-bad.l create mode 100644 gas/testsuite/gas/aarch64/sve2-lut-illegal.d create mode 100644 gas/testsuite/gas/aarch64/sve2-lut-illegal.l create mode 100644 gas/testsuite/gas/aarch64/sve2-lut-illegal.s create mode 100644 gas/testsuite/gas/aarch64/sve2-lut.d create mode 100644 gas/testsuite/gas/aarch64/sve2-lut.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 41547866d2c..fec17c40a43 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6784,7 +6784,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->qualifier = AARCH64_OPND_QLF_S_D; break; + case AARCH64_OPND_SVE_Zm1_23_INDEX: + case AARCH64_OPND_SVE_Zm2_22_INDEX: case AARCH64_OPND_SVE_Zm3_INDEX: + case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.l b/gas/testsuite/gas/aarch64/sme2-8-invalid.l index afea8bb6735..aa393657c4b 100644 --- a/gas/testsuite/gas/aarch64/sme2-8-invalid.l +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.l @@ -128,7 +128,7 @@ [^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] [^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] [^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 0,zt0,z0\[0\]' -[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti4 z0\.b,0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `luti4 z0\.b,0,z0\[0\]' [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.b,zt0,0' [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[-1\]' [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[8\]' diff --git a/gas/testsuite/gas/aarch64/sve2-lut-bad.d b/gas/testsuite/gas/aarch64/sve2-lut-bad.d new file mode 100644 index 00000000000..1134589dc86 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut-bad.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+lut +#source: sve2-lut.s +#error_output: sve2-lut-bad.l \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sve2-lut-bad.l b/gas/testsuite/gas/aarch64/sve2-lut-bad.l new file mode 100644 index 00000000000..8bbdc3e8518 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut-bad.l @@ -0,0 +1,34 @@ +[^ :]+: Assembler messages: +.*: Error: selected processor does not support `luti2 z0.b,{z0.b},z0\[0\]' +.*: Error: selected processor does not support `luti2 z31.b,{z0.b},z0\[0\]' +.*: Error: selected processor does not support `luti2 z0.b,{z31.b},z0\[0\]' +.*: Error: selected processor does not support `luti2 z0.b,{z0.b},z31\[0\]' +.*: Error: selected processor does not support `luti2 z0.b,{z0.b},z0\[3\]' +.*: Error: selected processor does not support `luti2 z4.b,{z9.b},z15\[2\]' +.*: Error: selected processor does not support `luti2 z0.h,{z0.h},z0\[0\]' +.*: Error: selected processor does not support `luti2 z31.h,{z0.h},z0\[0\]' +.*: Error: selected processor does not support `luti2 z0.h,{z31.h},z0\[0\]' +.*: Error: selected processor does not support `luti2 z0.h,{z0.h},z31\[0\]' +.*: Error: selected processor does not support `luti2 z0.h,{z0.h},z0\[7\]' +.*: Error: selected processor does not support `luti2 z4.h,{z9.h},z15\[2\]' +.*: Error: selected processor does not support `luti2 z4.h,{z9.h},z15\[1\]' +.*: Error: selected processor does not support `luti2 z4.h,{z9.h},z15\[4\]' +.*: Error: selected processor does not support `luti4 z0.b,{z0.b},z0\[0\]' +.*: Error: selected processor does not support `luti4 z31.b,{z0.b},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.b,{z31.b},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.b,{z0.b},z31\[0\]' +.*: Error: selected processor does not support `luti4 z0.b,{z0.b},z0\[1\]' +.*: Error: selected processor does not support `luti4 z4.b,{z9.b},z15\[1\]' +.*: Error: selected processor does not support `luti4 z0.h,{z0.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z31.h,{z0.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z30.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z0.h},z31\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z0.h},z0\[3\]' +.*: Error: selected processor does not support `luti4 z4.h,{z9.h},z15\[2\]' +.*: Error: selected processor does not support `luti4 z0.h,{z0.h,z1.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z31.h,{z0.h,z1.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z30.h,z31.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z31.h,z0.h},z0\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z0.h,z1.h},z31\[0\]' +.*: Error: selected processor does not support `luti4 z0.h,{z0.h,z1.h},z0\[3\]' +.*: Error: selected processor does not support `luti4 z4.h,{z9.h,z10.h},z15\[2\]' diff --git a/gas/testsuite/gas/aarch64/sve2-lut-illegal.d b/gas/testsuite/gas/aarch64/sve2-lut-illegal.d new file mode 100644 index 00000000000..542096321b0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut-illegal.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+lut+sve2 +#source: sve2-lut-illegal.s +#error_output: sve2-lut-illegal.l \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sve2-lut-illegal.l b/gas/testsuite/gas/aarch64/sve2-lut-illegal.l new file mode 100644 index 00000000000..bd6e41937d1 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut-illegal.l @@ -0,0 +1,212 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z2\.b,\{z5\.h\},z7\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z2\.b, \{z5\.b\}, z7\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z2\.h,\{z5\.b\},z7\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z2\.b, \{z5\.b\}, z7\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.b,\{z5\.h\},z7\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z2\.b, \{z5\.b\}, z7\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.h,\{z5\.b\},z7\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z2\.b, \{z5\.b\}, z7\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.b,\{z5\.h,z6\.h\},z12\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z2\.b, \{z5\.b-z6\.b\}, z12\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z2\.h,\{z5\.b,z6\.b\},z12\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z2\.b, \{z5\.b-z6\.b\}, z12\[1\] +[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `luti4 z2\.b,\{z5\.b,z6\.h\},z12\[1\]' +[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `luti4 z2\.h,\{z5\.h,z6\.b\},z12\[1\]' +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5\.b,\{\},z7\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 \{z5\.b\},z6\.b,z7\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 z5\.b,\{z7\.b,z8\.b\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5\.h,\{\},z7\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 \{z5\.h\},z6\.h,z7\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti2 z5\.h,\{z7\.h,z8\.h\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.b,\{\},z7\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 \{z5\.b\},z6\.b,z7\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a single-register list at operand 2 -- `luti4 z5\.b,\{z7\.b,z8\.b\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.h,\{\},z7\[1\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 \{z5\.h\},z6\.h,z7\[1\]' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `luti4 z5\.h,\{z7\.h,z9\.h\},z3\[3\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z5\.s,\{z7\.s\},z9\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z5\.b, \{z7\.b\}, z9\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.s,\{z7\.s\},z9\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z5\.b, \{z7\.b\}, z9\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.s,\{z7\.s,z8\.s\},z9\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z5\.b, \{z7\.b-z8\.b\}, z9\[1\] +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti2 z5\.b' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti2 z5\.b,\{z7\.b\}' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 z5\.b,\{z7\.b\},z9\[1\],z11\.b' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti2 z5\.h' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti2 z5\.h,\{z7\.h\}' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti2 z5\.h,\{z7\.h\},z9\[1\],z11\.h' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti4 z5\.b' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti4 z5\.b,\{z7\.b\}' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 z5\.b,\{z7\.b\},z9\[1\],z11\.b' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `luti4 z5\.h' +[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti4 z5\.h,\{z7\.h\}' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 z5\.h,\{z7\.h\},z9\[1\],z11\.h' +[^ :]+:[0-9]+: Error: comma expected between operands at operand 3 -- `luti4 z5\.h,\{z7\.h,z8\.h\}' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `luti4 z5\.h,\{z7\.h,z8\.h\},z9\[1\],z11\.h' +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti2 z5\.t,\{z7\.b},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti2 z5\.b,\{z7\.t},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z5\.b,\{z7\.b},z9\.b' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti2 z5\.t,\{z7\.h},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti2 z5\.h,\{z7\.t},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z5\.h,\{z7\.h},z9\.h' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 z5\.t,\{z7\.b},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 z5\.b,\{z7\.t},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z5\.b,\{z7\.b},z9\.b' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 1 -- `luti4 z5\.t,\{z7\.h,z8\.h},z9\[1\]' +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 z5\.h,\{z7\.t,z8\.h},z9\[1\]' +[^ :]+:[0-9]+: Error: unexpected character `t' in element size at operand 2 -- `luti4 z5\.h,\{z7\.h,z8\.t},z9\[1\]' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z5\.h,\{z7\.h,z8\.h},z9\.h' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 5.b,\{z7.b\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `luti2 z5.b,\{z7\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5.b,\{7.b\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z5.b,\{z7.b\},9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 5.h,\{z7.h\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `luti2 z5.h,\{z7\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti2 z5.h,\{7.h\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z5.h,\{z7.h\},9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 5\.b,\{z7.b},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `luti4 z5\.b,\{z7\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.b,\{7\.b\},z9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z5\.b,\{z7\.b\},9\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `luti4 z5\.h,\{z7,z8\.h\},z9\[1\]' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 5\.h,\{z7\.h,z8\.h},z9\[1\]' +[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `luti4 z5\.h,\{7\.h,z8\.h\},z9\[1\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z5\.h,\{z7\.h,z8\.h\},9\[1\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z5\.b,\{z7\.b\},z9\.b\[2\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z5\.b, \{z7\.b\}, z9\[2\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z5\.h,\{z7\.h\},z9\.h\[2\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z5\.h, \{z7\.h\}, z9\[2\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.b,\{z7\.b\},z9\.b\[1\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z5\.b, \{z7\.b\}, z9\[1\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.h,\{z7\.h\},z9\.h\[2\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z5\.h, \{z7\.h\}, z9\[2\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z5\.h,\{z7\.h,z8\.h\},z9\.h\[2\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z5\.h, \{z7\.h-z8\.h\}, z9\[2\] +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\.b\[2\],\{z9\.b\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\.b\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 z4.b,\{z9.b\[2\]\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\[2\]\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\.h\[2\],\{z9\.h\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\.h\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti2 z4.h,\{z9.h\[2\]\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti2 z4\[2\],\{z9\[2\]\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\.b\[2\],\{z9\.b\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9\.b\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 z4.b,\{z9.b\[2\]\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9\[2\]\},z15' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\.h\[2\],\{z9.h,z10.h\},z15' +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9.h,z10.h\},z15' +[^ :]+:[0-9]+: Error: index not allowed inside register list at operand 2 -- `luti4 z4.h,\{z9.h,z10.h\[2\]\},z15' +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `luti4 z4\[2\],\{z9,z10\[2\]\},z15' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.b,\{z9.b\},z15.b' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.b,\{z9.b\},z15' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.h,\{z9.h\},z15.h' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti2 z4.h,\{z9.h\},z15' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.b,\{z9.b\},z15.b' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.b,\{z9.b\},z15' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h\},z15.h' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h\},z15' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h,z10.h\},z15.h' +[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `luti4 z4.h,\{z9.h,z10.h\},z15' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 z32.b,\{z9.b\},z15\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti2 z4.b,\{z32.b\},z4\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z4.b,\{z9.b\},z32\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 z2.b,\{z9.b\},z4\[4\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 z4.b,\{z9.b\},z15\[-1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 z32.h,\{z9.h\},z15\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti2 z4.h,\{z32.h\},z4\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z4.h,\{z9.h\},z32\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 z2.h,\{z9.h\},z4\[8\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 z4.h,\{z9.h\},z15\[-1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 z32.b,\{z9.b\},z15\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti4 z4.b,\{z32.b\},z4\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z4.b,\{z9.b\},z32\[1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 z2.b,\{z9.b\},z4\[2\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 z4.b,\{z9.b\},z15\[-1\]' +[^ :]+:[0-9]+: Info: macro invoked from here +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 z32.h,\{z9.h\},z4\[2\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `luti4 z4.h,\{z32.h\},z15\[2\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z4.h,\{z9.h\},z32\[2\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 z2.h,\{z9.h\},z15\[4\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 z4.h,\{z9.h\},z15\[-1\]' diff --git a/gas/testsuite/gas/aarch64/sve2-lut-illegal.s b/gas/testsuite/gas/aarch64/sve2-lut-illegal.s new file mode 100644 index 00000000000..6be60e22823 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut-illegal.s @@ -0,0 +1,128 @@ + // Operand mismatch + luti2 z2.b, { z5.h }, z7[1] + luti2 z2.h, { z5.b }, z7[1] + luti4 z2.b, { z5.h }, z7[1] + luti4 z2.h, { z5.b }, z7[1] + luti4 z2.b, { z5.h, z6.h }, z12[1] + luti4 z2.h, { z5.b, z6.b }, z12[1] + luti4 z2.b, { z5.b, z6.h }, z12[1] + luti4 z2.h, { z5.h, z6.b }, z12[1] + + // Incorrect operands + .macro incorrect_operands, op, operand_type + \op z5\operand_type, { }, z7[1] + \op { z5\operand_type }, z6\operand_type, z7[1] + \op z5\operand_type, { z7\operand_type, z8\operand_type }, z9[1] + .endm + + incorrect_operands luti2 .b + incorrect_operands luti2 .h + incorrect_operands luti4 .b + luti4 z5.h, { }, z7[1] + luti4 { z5.h }, z6.h, z7[1] + luti4 z5.h, { z7.h, z9.h }, z3[3] + + // Disallowed types + luti2 z5.s, { z7.s }, z9[1] + luti4 z5.s, { z7.s }, z9[1] + luti4 z5.s, { z7.s, z8.s }, z9[1] + + // Incorrect number of operands + .macro incorrect_number_of_operands, op, operand_type + \op z5\operand_type + \op z5\operand_type, { z7\operand_type } + \op z5\operand_type, { z7\operand_type }, z9[1], z11\operand_type + .endm + incorrect_number_of_operands luti2 .b + incorrect_number_of_operands luti2 .h + incorrect_number_of_operands luti4 .b + luti4 z5.h + luti4 z5.h, { z7.h } + luti4 z5.h, { z7.h }, z9[1], z11.h + luti4 z5.h, { z7.h, z8.h } + luti4 z5.h, { z7.h, z8.h }, z9[1], z11.h + + // Spelling mistakes + .macro spelling_mistakes, op, operand_type + \op z5.t, { z7\operand_type }, z9[1] + \op z5\operand_type, { z7.t }, z9[1] + \op z5\operand_type, { z7\operand_type }, z9\operand_type + .endm + + spelling_mistakes luti2 .b + spelling_mistakes luti2 .h + spelling_mistakes luti4 .b + luti4 z5.t, { z7.h, z8.h }, z9[1] + luti4 z5.h, { z7.t, z8.h }, z9[1] + luti4 z5.h, { z7.h, z8.t }, z9[1] + luti4 z5.h, { z7.h, z8.h }, z9.h + + // Missing qualifiers + .macro missing_qualifiers, op, operand_type + \op 5\operand_type, { z7\operand_type }, z9[1] + \op z5\operand_type, { z7 }, z9[1] + \op z5\operand_type, { 7\operand_type }, z9[1] + \op z5\operand_type, { z7\operand_type }, 9[1] + .endm + + missing_qualifiers luti2 .b + missing_qualifiers luti2 .h + missing_qualifiers luti4 .b + luti4 z5.h, { z7, z8.h }, z9[1] + luti4 5.h, { z7.h, z8.h }, z9[1] + luti4 z5.h, { 7.h, z8.h }, z9[1] + luti4 z5.h, { z7.h, z8.h }, 9[1] + + // Index with qualifiers + luti2 z5.b, { z7.b }, z9.b[2] + luti2 z5.h, { z7.h }, z9.h[2] + luti4 z5.b, { z7.b }, z9.b[1] + luti4 z5.h, { z7.h }, z9.h[2] + luti4 z5.h, { z7.h, z8.h }, z9.h[2] + + // Index on the wrong operand + .macro index_wrong_operand op, operand_type + \op z4\operand_type[2], { z9\operand_type }, z15 + \op z4[2], { z9\operand_type }, z15 + \op z4\operand_type, { z9\operand_type[2] }, z15 + \op z4[2], { z9[2] }, z15 + .endm + + index_wrong_operand luti2 .b + index_wrong_operand luti2 .h + index_wrong_operand luti4 .b + luti4 z4.h[2], { z9.h, z10.h }, z15 + luti4 z4[2], { z9.h, z10.h }, z15 + luti4 z4.h, { z9.h, z10.h[2] }, z15 + luti4 z4[2], { z9, z10[2] }, z15 + + // Missing index + luti2 z4.b, { z9.b }, z15.b + luti2 z4.b, { z9.b }, z15 + luti2 z4.h, { z9.h }, z15.h + luti2 z4.h, { z9.h }, z15 + + luti4 z4.b, { z9.b }, z15.b + luti4 z4.b, { z9.b }, z15 + luti4 z4.h, { z9.h }, z15.h + luti4 z4.h, { z9.h }, z15 + luti4 z4.h, { z9.h, z10.h }, z15.h + luti4 z4.h, { z9.h, z10.h }, z15 + + // Out of range numbers + .macro out_of_range op, operand_type, max_index_plus_one + \op z32\operand_type, { z9\operand_type }, z15[1] + \op z4\operand_type, { z32\operand_type }, z4[1] + \op z4\operand_type, { z9\operand_type }, z32[1] + \op z2\operand_type, { z9\operand_type }, z4[\max_index_plus_one] + \op z4\operand_type, { z9\operand_type }, z15[-1] + .endm + + out_of_range luti2, .b, 4 + out_of_range luti2, .h, 8 + out_of_range luti4, .b, 2 + luti4 z32.h, { z9.h }, z4[2] + luti4 z4.h, { z32.h }, z15[2] + luti4 z4.h, { z9.h }, z32[2] + luti4 z2.h, { z9.h }, z15[4] + luti4 z4.h, { z9.h }, z15[-1] diff --git a/gas/testsuite/gas/aarch64/sve2-lut.d b/gas/testsuite/gas/aarch64/sve2-lut.d new file mode 100644 index 00000000000..7b39b17d35d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut.d @@ -0,0 +1,41 @@ +#objdump: -dr +#as: -march=armv8-a+lut+sve2 + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +[^:]+: 4520b000 luti2 z0.b, \{z0.b\}, z0\[0\] +[^:]+: 4520b01f luti2 z31.b, \{z0.b\}, z0\[0\] +[^:]+: 4520b3e0 luti2 z0.b, \{z31.b\}, z0\[0\] +[^:]+: 453fb000 luti2 z0.b, \{z0.b\}, z31\[0\] +[^:]+: 45e0b000 luti2 z0.b, \{z0.b\}, z0\[3\] +[^:]+: 45afb124 luti2 z4.b, \{z9.b\}, z15\[2\] +[^:]+: 4520a800 luti2 z0.h, \{z0.h\}, z0\[0\] +[^:]+: 4520a81f luti2 z31.h, \{z0.h\}, z0\[0\] +[^:]+: 4520abe0 luti2 z0.h, \{z31.h\}, z0\[0\] +[^:]+: 453fa800 luti2 z0.h, \{z0.h\}, z31\[0\] +[^:]+: 45e0b800 luti2 z0.h, \{z0.h\}, z0\[7\] +[^:]+: 456fa924 luti2 z4.h, \{z9.h\}, z15\[2\] +[^:]+: 452fb924 luti2 z4.h, \{z9.h\}, z15\[1\] +[^:]+: 45afa924 luti2 z4.h, \{z9.h\}, z15\[4\] +[^:]+: 4560a400 luti4 z0.b, \{z0.b\}, z0\[0\] +[^:]+: 4560a41f luti4 z31.b, \{z0.b\}, z0\[0\] +[^:]+: 4560a7e0 luti4 z0.b, \{z31.b\}, z0\[0\] +[^:]+: 457fa400 luti4 z0.b, \{z0.b\}, z31\[0\] +[^:]+: 45e0a400 luti4 z0.b, \{z0.b\}, z0\[1\] +[^:]+: 45efa524 luti4 z4.b, \{z9.b\}, z15\[1\] +[^:]+: 4520bc00 luti4 z0.h, \{z0.h\}, z0\[0\] +[^:]+: 4520bc1f luti4 z31.h, \{z0.h\}, z0\[0\] +[^:]+: 4520bfc0 luti4 z0.h, \{z30.h\}, z0\[0\] +[^:]+: 453fbc00 luti4 z0.h, \{z0.h\}, z31\[0\] +[^:]+: 45e0bc00 luti4 z0.h, \{z0.h\}, z0\[3\] +[^:]+: 45afbd24 luti4 z4.h, \{z9.h\}, z15\[2\] +[^:]+: 4520b400 luti4 z0.h, \{z0.h-z1.h\}, z0\[0\] +[^:]+: 4520b41f luti4 z31.h, \{z0.h-z1.h\}, z0\[0\] +[^:]+: 4520b7c0 luti4 z0.h, \{z30.h-z31.h\}, z0\[0\] +[^:]+: 4520b7e0 luti4 z0.h, \{z31.h-z0.h\}, z0\[0\] +[^:]+: 453fb400 luti4 z0.h, \{z0.h-z1.h\}, z31\[0\] +[^:]+: 45e0b400 luti4 z0.h, \{z0.h-z1.h\}, z0\[3\] +[^:]+: 45afb524 luti4 z4.h, \{z9.h-z10.h\}, z15\[2\] \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sve2-lut.s b/gas/testsuite/gas/aarch64/sve2-lut.s new file mode 100644 index 00000000000..e9c79c6e84e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve2-lut.s @@ -0,0 +1,39 @@ + // Valid luti2 instructions + luti2 z0.b, { z0.b }, z0[0] + luti2 z31.b, { z0.b }, z0[0] + luti2 z0.b, { z31.b }, z0[0] + luti2 z0.b, { z0.b }, z31[0] + luti2 z0.b, { z0.b }, z0[3] + luti2 z4.b, { z9.b }, z15[2] + + luti2 z0.h, { z0.h }, z0[0] + luti2 z31.h, { z0.h }, z0[0] + luti2 z0.h, { z31.h }, z0[0] + luti2 z0.h, { z0.h }, z31[0] + luti2 z0.h, { z0.h }, z0[7] + luti2 z4.h, { z9.h }, z15[2] + luti2 z4.h, { z9.h }, z15[1] + luti2 z4.h, { z9.h }, z15[4] + + // Valid luti4 instructions + luti4 z0.b, { z0.b }, z0[0] + luti4 z31.b, { z0.b }, z0[0] + luti4 z0.b, { z31.b }, z0[0] + luti4 z0.b, { z0.b }, z31[0] + luti4 z0.b, { z0.b }, z0[1] + luti4 z4.b, { z9.b }, z15[1] + + luti4 z0.h, { z0.h }, z0[0] + luti4 z31.h, { z0.h }, z0[0] + luti4 z0.h, { z30.h }, z0[0] + luti4 z0.h, { z0.h }, z31[0] + luti4 z0.h, { z0.h }, z0[3] + luti4 z4.h, { z9.h }, z15[2] + + luti4 z0.h, { z0.h, z1.h }, z0[0] + luti4 z31.h, { z0.h, z1.h }, z0[0] + luti4 z0.h, { z30.h, z31.h }, z0[0] + luti4 z0.h, { z31.h, z0.h }, z0[0] + luti4 z0.h, { z0.h, z1.h }, z31[0] + luti4 z0.h, { z0.h, z1.h }, z0[3] + luti4 z4.h, { z9.h, z10.h }, z15[2] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 95448b58721..8a21611e3ff 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -737,8 +737,11 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ + AARCH64_OPND_SVE_Zm1_23_INDEX, /* SVE bit index in Zm, bit 23. */ + AARCH64_OPND_SVE_Zm2_22_INDEX, /* SVE bit index in Zm, bits [23,22]. */ AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ + AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */ AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 84a3955b83b..bbe6f09808b 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -294,10 +294,14 @@ const aarch64_field fields[] = { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */ { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */ { 5, 1 }, /* SVE_i1: single-bit immediate. */ + { 23, 1 }, /* SVE_i1_23: single-bit immediate. */ + { 22, 2 }, /* SVE_i2: 2-bit index, bits [23,22]. */ { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */ { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */ { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */ + { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ + { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -1813,6 +1817,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SVE_Zm1_23_INDEX: + size = get_operand_fields_width (get_operand_from_code (type)); + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 1)) + return 0; + break; + + case AARCH64_OPND_SVE_Zm2_22_INDEX: + size = get_operand_fields_width (get_operand_from_code (type)); + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 3)) + return 0; + break; + case AARCH64_OPND_SVE_Zn_INDEX: size = aarch64_get_qualifier_esize (opnd->qualifier); if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, @@ -1840,6 +1856,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: @@ -4194,9 +4211,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, print_register_list (buf, size, opnd, "z", styler); break; + case AARCH64_OPND_SVE_Zm1_23_INDEX: + case AARCH64_OPND_SVE_Zm2_22_INDEX: case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: + case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 23e634f1250..8bf3fc8b874 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -104,10 +104,14 @@ enum aarch64_field_kind FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_i1, + FLD_SVE_i1_23, + FLD_SVE_i2, FLD_SVE_i2h, FLD_SVE_i3h, FLD_SVE_i3h2, + FLD_SVE_i3h3, FLD_SVE_i3l, + FLD_SVE_i3l2, FLD_SVE_imm3, FLD_SVE_imm4, FLD_SVE_imm5, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 6b98a1bc22d..1d12630273e 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1529,9 +1529,21 @@ { \ QLF2(S_H,S_H), \ } +/* e.g. luti2 .B, { .B }, [index]. */ +/* The third operand is an index (e.g. immediate or bit) + without a type qualifier and is checked separately + based on operand enum. */ #define OP_SVE_BBU \ { \ - QLF3(S_B,S_B,NIL), \ + QLF3(S_B,S_B,NIL), \ +} +/* e.g. luti2 .H, { .H }, [index]. */ +/* The third operand is an index (e.g. immediate or bit) + without a type qualifier and is checked separately + based on operand enum. */ +#define OP_SVE_HHU \ +{ \ + QLF3(S_H,S_H,NIL), \ } #define OP_SVE_BBB \ { \ @@ -2731,6 +2743,8 @@ static const aarch64_feature_set aarch64_feature_fp8_sme2 = AARCH64_FEATURES (2, FP8, SME2); static const aarch64_feature_set aarch64_feature_lut = AARCH64_FEATURE (LUT); +static const aarch64_feature_set aarch64_feature_lut_sve2 = + AARCH64_FEATURES (2, LUT, SVE2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2806,6 +2820,7 @@ static const aarch64_feature_set aarch64_feature_lut = #define FP8_SVE2 &aarch64_feature_fp8_sve2 #define FP8_SME2 &aarch64_feature_fp8_sme2 #define LUT &aarch64_feature_lut +#define LUT_SVE2 &aarch64_feature_lut_sve2 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -3001,6 +3016,9 @@ static const aarch64_feature_set aarch64_feature_lut = F_STRICT | FLAGS, 0, TIED, NULL } #define LUT_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, lut, 0, LUT, OPS, QUALS, FLAGS, 0, 0, NULL } +#define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \ + { NAME, OPCODE, MASK, lut, 0, LUT_SVE2, OPS, QUALS, \ + FLAGS, CONSTRAINTS, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6579,6 +6597,13 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUT_INSN ("luti4", 0x4e402000, 0xffe0bc00, OP3 (Vd, LVn_LUT, Em_INDEX1_14), QL_VVUB, F_OD(1)), LUT_INSN ("luti4", 0x4e401000, 0xffe09c00, OP3 (Vd, LVn_LUT, Em_INDEX2_13), QL_VVUH, F_OD(2)), + /* SVE2 lut. */ + LUT_SVE2_INSN ("luti2", 0x4520b000, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_BBU, F_OD(1), 0), + LUT_SVE2_INSN ("luti2", 0x4520a800, 0xff20ec00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm3_12_INDEX), OP_SVE_HHU, F_OD(1), 0), + LUT_SVE2_INSN ("luti4", 0x4560a400, 0xff60fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm1_23_INDEX), OP_SVE_BBU, F_OD(1), 0), + LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0), + LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -7052,12 +7077,21 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an SVE vector register") \ Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ "an SVE vector register") \ + Y(SVE_REG, simple_index, "SVE_Zm1_23_INDEX", \ + 0, F(FLD_SVE_Zm_16, FLD_SVE_i1_23), \ + "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SVE_Zm2_22_INDEX", \ + 0, F(FLD_SVE_Zm_16, FLD_SVE_i2), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \ "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SVE_Zm3_12_INDEX", \ + 0, F(FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_19_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_imm2_19, FLD_SVE_imm3), \ "an indexed SVE vector register") \