From patchwork Wed May 15 06:31:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cui, Lili" X-Patchwork-Id: 90163 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 20CA0384AB74 for ; Wed, 15 May 2024 06:33:51 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by sourceware.org (Postfix) with ESMTPS id 60BE3385842A for ; Wed, 15 May 2024 06:32:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 60BE3385842A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 60BE3385842A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715754725; cv=none; b=q/eDYhRWE+JjlRedfap98B0Gsd+v93jGR2hot450JuEUSNhWFZAQO4mUvmkVR6jROjM7MIf7JXZXAeBb3Hp+jipY0qudGDAQwcOZCipVFFEmu6uw3bOm1f+2QbNfrC88yf2E6potZmXSpLyTNeN787h+crozNvlI9d3pJwS7urQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715754725; c=relaxed/simple; bh=A3g1UMWT1qBYvDoxVrbmXAV8sJUeXAlMIhWV+GREWa0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=uVfgw2QgDLe0Alo+JszxlQLfgXeKlr8qZhMo5kBpgNSI+4QzGhQyRCWTn0RwVgsfmNPJ8bdBLydSTGI2aGyM3lYsyz9Sunmkw+isnjZ1mBehNBuknglCKQAEPy6wILouS8oeUQjKSF8W9fkGYtx2KW30aoMDAg384jp8AhGmJxo= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715754722; x=1747290722; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A3g1UMWT1qBYvDoxVrbmXAV8sJUeXAlMIhWV+GREWa0=; b=h7Wz4Si98QD3bfIAAcQWtuPHau6mQY+7d1t8vizcOcVWpwSTZuYjFZ1L yPhabu8zxVB20+r24UmJckhdzRg+18wrx+ZzVkOq965/vdPfKy6fE8dtl 8fXLzeWdqaKjvGSF/N8wlURf/SdY9q2twdfmEQY5tUqXcEEm56J6alSDJ UZRnhkt919r8qu/67YsSfWlbhhlPrhViGjHXSkCgpQwADZuuiDoWVOLGX eIHAU2DBVdzWnQdEFmPM39KkKzvK1h3OSUkq8pVP446AX3SgKqb/kJGGG V/Mwg7TarN3vz3JXFUQv1cktAYHMTZ+ZOHvsAEfNNKW3Xw/x7k4WnpxCy w==; X-CSE-ConnectionGUID: OXq/i3IETniShKjBe8NCaw== X-CSE-MsgGUID: HhFT25BPRnyW1pefXG+Zgg== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="34293631" X-IronPort-AV: E=Sophos;i="6.08,161,1712646000"; d="scan'208";a="34293631" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 23:32:01 -0700 X-CSE-ConnectionGUID: CJFhegNlTy2Dezij28+qkw== X-CSE-MsgGUID: pfe/M3llRM2xNIXebGjg0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,161,1712646000"; d="scan'208";a="31521597" Received: from scymds04.sc.intel.com ([10.82.73.238]) by orviesa007.jf.intel.com with ESMTP; 14 May 2024 23:32:01 -0700 Received: from shgcc10.sh.intel.com (unknown [10.239.85.189]) by scymds04.sc.intel.com (Postfix) with ESMTP id A49082003A88; Tue, 14 May 2024 23:32:00 -0700 (PDT) From: "Cui, Lili" To: binutils@sourceware.org Cc: hjl.tools@gmail.com, jbeulich@suse.com Subject: [PATCH 1/2] Add check for 8-bit old registers in EVEX format Date: Wed, 15 May 2024 14:31:57 +0800 Message-Id: <20240515063158.3960697-2-lili.cui@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515063158.3960697-1-lili.cui@intel.com> References: <20240515063158.3960697-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org gas/ChangeLog: * config/tc-i386.c (md_assemble): Add invalid check for old byte registers in EVEX/VEX format. * testsuite/gas/i386/x86-64-apx-inval.l: Add new test. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. --- gas/config/tc-i386.c | 12 ++++++++++++ gas/testsuite/gas/i386/x86-64-apx-inval.l | 3 +++ gas/testsuite/gas/i386/x86-64-apx-inval.s | 2 ++ 3 files changed, 17 insertions(+) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 339e849a971..18d06371321 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -7029,6 +7029,18 @@ md_assemble (char *line) as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm)); return; } + /* Check for 8 bit operand that uses old registers. */ + for (unsigned int op = 0; op < i.operands; op++) + { + if (i.types[op].bitfield.class == Reg + && i.types[op].bitfield.byte + && !(i.op[op].regs->reg_flags & RegRex64) + && i.op[op].regs->reg_num > 3) + + as_bad (_("can't encode register '%s' in an " + " EVEX/VEX prefix instruction"), + i.op[op].regs->reg_name); + } if (is_apx_evex_encoding ()) build_apx_evex_prefix (); diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.l b/gas/testsuite/gas/i386/x86-64-apx-inval.l index 7a870b27b72..3595213b179 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-inval.l +++ b/gas/testsuite/gas/i386/x86-64-apx-inval.l @@ -12,3 +12,6 @@ .*:13: Error: \{nf\} unsupported for `mulx' .*:14: Error: \{nf\} cannot be combined with \{vex\}/\{vex3\} .*:15: Error: \{nf\} cannot be combined with \{vex\}/\{vex3\} +.*:16: Error: can't encode register 'ah' in an EVEX/VEX prefix instruction +.*:17: Error: can't encode register 'ah' in an EVEX/VEX prefix instruction +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.s b/gas/testsuite/gas/i386/x86-64-apx-inval.s index 0487b885ec8..3a8402429ed 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-inval.s +++ b/gas/testsuite/gas/i386/x86-64-apx-inval.s @@ -13,3 +13,5 @@ {nf} mulx %r15,%r15,%r11 {nf} {vex} bextr %ecx, %edx, %r10d {vex} {nf} bextr %ecx, %edx, %r10d + {nf} add %dl,%ah + {evex} adc %dl,%ah