[V2] Support APX NF

Message ID 20240304081527.1724628-1-lili.cui@intel.com
State New
Headers
Series [V2] Support APX NF |

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Commit Message

Cui, Lili March 4, 2024, 8:15 a.m. UTC
  gas/ChangeLog:

       * NEWS: Support Intel APX NF.
       * config/tc-i386.c (enum i386_error): Add unsupported_nf.
       (struct _i386_insn): Add has_nf.
       (is_apx_evex_encoding): Ditto.
       (build_apx_evex_prefix): Encode the NF bit.
       (md_assemble): Handle unsupported_nf.
       (parse_insn): Handle Prefix_NF.
       (can_convert_NDD_to_legacy):
       (match_template): Support D for APX_F insns.
       * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit.
       * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
       * testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
       * testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
       * testsuite/gas/i386/x86-64.exp: Add apx nf tests.
       * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
       * testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
       * testsuite/gas/i386/x86-64-apx-nf.s: Ditto.

opcodes/ChangeLog:

       * i386-dis-evex.h: Add %XN to the instructions that support APX NF and
       add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
       * i386-dis-evex-reg.h: Ditto.
       * i386-dis.c (struct instr_info): Add nf.
       (struct dis386): Add "NF" for EVEX.NF.
       (get_valid_dis386): Set ins->vex.nf.
       (print_insn): Handle ins.vex.nf.
       (putop): Handle "%NF".
       * i386-opc.h (Prefix_NoOptimize): Adjust the value.
       (Prefix_NF): New.
       * i386-opc.tbl: Add new entries for the instructions that support APX NF.
       * i386-mnem.h: Regenerated.
       * i386-tbl.h: Regenerated.
---
 gas/NEWS                                      |    2 +
 gas/config/tc-i386.c                          |   29 +-
 .../gas/i386/x86-64-apx-evex-promoted-bad.d   |    9 +-
 .../gas/i386/x86-64-apx-evex-promoted-bad.s   |   12 +-
 gas/testsuite/gas/i386/x86-64-apx-inval.l     |    7 +
 gas/testsuite/gas/i386/x86-64-apx-inval.s     |    7 +
 gas/testsuite/gas/i386/x86-64-apx-nf-intel.d  | 1315 +++++++++++++++++
 gas/testsuite/gas/i386/x86-64-apx-nf.d        | 1315 +++++++++++++++++
 gas/testsuite/gas/i386/x86-64-apx-nf.s        | 1310 ++++++++++++++++
 gas/testsuite/gas/i386/x86-64.exp             |    2 +
 opcodes/i386-dis-evex-reg.h                   |   54 +-
 opcodes/i386-dis-evex.h                       |   60 +-
 opcodes/i386-dis.c                            |  134 +-
 opcodes/i386-opc.h                            |    1 +
 opcodes/i386-opc.tbl                          |   68 +-
 15 files changed, 4214 insertions(+), 111 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.s
  

Comments

Jan Beulich March 8, 2024, 9:36 a.m. UTC | #1
On 04.03.2024 09:15, Cui, Lili wrote:
> gas/ChangeLog:
> 
>        * NEWS: Support Intel APX NF.
>        * config/tc-i386.c (enum i386_error): Add unsupported_nf.
>        (struct _i386_insn): Add has_nf.
>        (is_apx_evex_encoding): Ditto.
>        (build_apx_evex_prefix): Encode the NF bit.
>        (md_assemble): Handle unsupported_nf.
>        (parse_insn): Handle Prefix_NF.
>        (can_convert_NDD_to_legacy):
>        (match_template): Support D for APX_F insns.
>        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit.
>        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
>        * testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
>        * testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
>        * testsuite/gas/i386/x86-64.exp: Add apx nf tests.
>        * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
>        * testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
>        * testsuite/gas/i386/x86-64-apx-nf.s: Ditto.
> 
> opcodes/ChangeLog:
> 
>        * i386-dis-evex.h: Add %XN to the instructions that support APX NF and
>        add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
>        * i386-dis-evex-reg.h: Ditto.
>        * i386-dis.c (struct instr_info): Add nf.
>        (struct dis386): Add "NF" for EVEX.NF.
>        (get_valid_dis386): Set ins->vex.nf.
>        (print_insn): Handle ins.vex.nf.
>        (putop): Handle "%NF".
>        * i386-opc.h (Prefix_NoOptimize): Adjust the value.

Stale entry? As asked for before: If you provide this information, it needs
to be adjusted as patch contents actually changes.

>        (Prefix_NF): New.
>        * i386-opc.tbl: Add new entries for the instructions that support APX NF.

... plus a few that don't (while others that don't and aren't of use except
when used with {evex} were added prematurely).

> @@ -6655,6 +6663,9 @@ md_assemble (char *line)
>  	case unsupported_EGPR_for_addressing:
>  	  err_msg = _("extended GPR cannot be used as base/index");
>  	  break;
> +	case unsupported_nf:
> +	  err_msg = _("unsupported NF");
> +	  break;

"{nf} unsupported" (yielding an overall better complete diagnostic)?

> @@ -7218,6 +7229,11 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only)
>  		  /* {rex2} */
>  		  i.rex2_encoding = true;
>  		  break;
> +		case Prefix_NF:
> +		  /* {nf} */
> +		  i.has_nf = true;
> +		  i.encoding = encoding_evex;
> +		  break;

It's not quite as easy, I'm afraid: Have you thought of the "{vex} {nf} ..."
case? (I think I previously indicated that their combination, actually in
either order, needs properly rejecting.) Without having spent much thought
on it, perhaps it would suffice to check here that the field is still
encoding_default, and leave the value alone otherwise (in order to reject
bad combinations elsewhere).

> --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
> +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
> @@ -23,7 +23,7 @@ _start:
>  	.insn EVEX.L1.66.M12.W0 0x60, %di, %ax
>  
>  	#EVEX_MAP4 movbe %r18w,%ax set EVEX.z == 0b1.
> -	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k7}{z}
> +	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k3}{z}

What's going on here ...

> @@ -33,17 +33,25 @@ _start:
>  	.insn EVEX.L1.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx
>  
>  	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[23](EVEX.z) == 0b1
> -	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k7}{z}
> +	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k3}{z}

... and here? This is the kind of thing that wants mentioning in the
patch description. And once again, especially for larger patches it is
generally a bad idea if they come with only legacy ChangeLog entries:
These only say "what", never "why". (That said, I think I see why the
change is needed.)

Additionally may I ask that you get used to providing a brief revision
log when sending new versions of earlier patches? This helps reviewers
when they did look at the earlier version(s).

>  	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[20](EVEX.b) == 0b1
>  	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx){1to8}, %rcx
>  
>  	#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
>  	.byte 0x62, 0xf4, 0xe4, 0x08, 0xff, 0x04, 0x08
> +
>  	# pop2 %rax, %r8 set EVEX.ND=0.
>  	.byte 0x62, 0xf4, 0x3c, 0x08, 0x8f, 0xc0
>  	.byte 0xff, 0xff, 0xff
> +
>  	# pop2 %rax, %r8 set EVEX.vvvv = 1111.
>  	.insn EVEX.L0.M4.W0 0x8f,  %rax, {rn-sae},%r8
> +
>  	# pop2 %r8, %r8.
>  	.byte 0x62, 0xd4, 0x3c, 0x18, 0x8f, 0xc0
> +	.byte 0xff, 0xff

As indicated - this would better be avoided by picking a more suitable
ModR/M byte on the earlier line. Using %r11 instead of %r8 ought to do
just fine here, I suppose.

> +	#EVEX_MAP4 movbe %r18w,%ax set EVEX.nf = 1.
> +        .insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k4}

Nit: Inconsistent indentation.

> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s
>[...]
> +	{nf}	rorq	%cl, 291(%r8, %rax, 4)
> +	{nf}	ror	%cl, 291(%r8, %rax, 4), %r9
> +	{nf}	sar	$1, %bl
> +	{nf}	sar	$1, %bl, %dl
> +	{nf}	sar	$1, %dx
> +	{nf}	sar	$1, %dx, %ax
> +	{nf}	sar	$1, %ecx
> +	{nf}	sar	$1, %ecx, %edx
> +	{nf}	sar	$1, %r9
> +	{nf}	sar	$1, %r9, %r31
> +	{nf}	sarb	$1, 291(%r8, %rax, 4)
> +	{nf}	sar	$1, 291(%r8, %rax, 4), %bl
> +	{nf}	sarw	$1, 291(%r8, %rax, 4)
> +	{nf}	sar	$1, 291(%r8, %rax, 4), %dx
> +	{nf}	sarl	$1, 291(%r8, %rax, 4)
> +	{nf}	sar	$1, 291(%r8, %rax, 4), %ecx
> +	{nf}	sarq	$1, 291(%r8, %rax, 4)
> +	{nf}	sar	$1, 291(%r8, %rax, 4), %r9
> +	{nf}	sar	$123, %bl
> +	{nf}	sar	$123, %bl, %dl
> +	{nf}	sar	$123, %dx
> +	{nf}	sar	$123, %dx, %ax
> +	{nf}	sar	$123, %ecx
> +	{nf}	sar	$123, %ecx, %edx
> +	{nf}	sar	$123, %r9
> +	{nf}	sar	$123, %r9, %r31
> +	{nf}	sarb	$123, 291(%r8, %rax, 4)
> +	{nf}	sar	$123, 291(%r8, %rax, 4), %bl
> +	{nf}	sarw	$123, 291(%r8, %rax, 4)
> +	{nf}	sar	$123, 291(%r8, %rax, 4), %dx
> +	{nf}	sarl	$123, 291(%r8, %rax, 4)
> +	{nf}	sar	$123, 291(%r8, %rax, 4), %ecx
> +	{nf}	sarq	$123, 291(%r8, %rax, 4)
> +	{nf}	sar	$123, 291(%r8, %rax, 4), %r9
> +	{nf}	sar	%cl, %bl
> +	{nf}	sar	%cl, %bl, %dl
> +	{nf}	sar	%cl, %dx
> +	{nf}	sar	%cl, %dx, %ax
> +	{nf}	sar	%cl, %ecx
> +	{nf}	sar	%cl, %ecx, %edx
> +	{nf}	sar	%cl, %r9
> +	{nf}	sar	%cl, %r9, %r31
> +	{nf}	sarb	%cl, 291(%r8, %rax, 4)
> +	{nf}	sar	%cl, 291(%r8, %rax, 4), %bl
> +	{nf}	sarw	%cl, 291(%r8, %rax, 4)
> +	{nf}	sar	%cl, 291(%r8, %rax, 4), %dx
> +	{nf}	sarl	%cl, 291(%r8, %rax, 4)
> +	{nf}	sar	%cl, 291(%r8, %rax, 4), %ecx
> +	{nf}	sarq	%cl, 291(%r8, %rax, 4)
> +	{nf}	sar	%cl, 291(%r8, %rax, 4), %r9
> +	{nf}	sal	$1, %bl
> +	{nf}	sal	$1, %bl, %dl

Hmm "sal" sorts ahead of "sar", doesn't it?

> --- a/opcodes/i386-dis-evex-reg.h
> +++ b/opcodes/i386-dis-evex-reg.h
> @@ -51,33 +51,33 @@
>    },
>    /* REG_EVEX_MAP4_80 */
>    {
> -    { "addA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "orA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> +    { "%NFaddA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> +    { "%NForA",	{ VexGb, Eb, Ib }, NO_PREFIX },
>      { "adcA",	{ VexGb, Eb, Ib }, NO_PREFIX },
>      { "sbbA",	{ VexGb, Eb, Ib }, NO_PREFIX },

You (correctly) leave these alone.

> @@ -87,25 +87,33 @@
>    {
>      { Bad_Opcode },
>      { Bad_Opcode },
> -    { "notA",	{ VexGb, Eb }, NO_PREFIX },
> -    { "negA",	{ VexGb, Eb }, NO_PREFIX },
> +    { "%NFnotA",	{ VexGb, Eb }, NO_PREFIX },

Why does this gain %NF then?

> @@ -1815,6 +1817,8 @@ struct dis386 {
>     "XV" => print "{vex} " pseudo prefix
>     "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
>  	   is used by an EVEX-encoded (AVX512VL) instruction.
> +   "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1.
> +	   a valid encoding.

What is this 2nd line, not even a complete sentence, supposed to be
saying?

> @@ -2619,25 +2623,25 @@ static const struct dis386 reg_table[][8] = {
>    },
>    /* REG_C0 */
>    {
> -    { "rolA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "rorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "rclA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "rcrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "shlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "shrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "shlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> -    { "sarA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> +    { "%NFrolA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> +    { "%NFrorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> +    { "%NFrclA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> +    { "%NFrcrA",	{ VexGb, Eb, Ib }, NO_PREFIX },

Like NOT, RC{L,R} look to be wrongly being modified here. Interestingly
for D0...D3 you leave them alone.

> @@ -9147,6 +9151,10 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
>        ins->vex.v = *ins->codep & 0x8;
>        ins->vex.mask_register_specifier = *ins->codep & 0x7;
>        ins->vex.zeroing = *ins->codep & 0x80;
> +      /* Set the NF bit for the EVEX instruction extended from the legacy or
> +	 vex instruction, this bit will be cleared when it can be confirmed
> +	 that its defaut type is evex.  */
> +      ins->vex.nf = *ins->codep & 0x4;

Whow or what is "its" in the comment? Also nit: "default". Assuming it's
the insn that's meant, how about "when it's an evex_default one"?

> @@ -9600,10 +9608,21 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
>  	  && ins.vex.prefix == DATA_PREFIX_OPCODE)
>  	sizeflag ^= DFLAG;
>  
> +      if(ins.evex_type == evex_default)
> +	ins.vex.nf = false;
> +      else
> +	/* For EVEX-promoted formats, we need to clear EVEX.NF (For ccmp and
> +	   ctest, they will be cleared separately.) in mask_register_specifier
> +	   and keep the low 2 bits of mask_register_specifier to report errors
> +	   for invalid cases.*/
> +	ins.vex.mask_register_specifier &= 0x3;
> +
>        if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
>  	{
>  	  if (!get_sib (&ins, sizeflag))
>  	    goto fetch_error_out;
> +	  if (!ins.has_nf && ins.vex.nf)
> +	    oappend (&ins, "{bad}");

As can be seen from the testcase additions, this suffixes onto the insn
menmonic. Since it's a bogus (pseudo) prefix, maybe better also print as
such, and then maybe also indicate what it is that is bad (e.g. {bad-nf})?

> @@ -10564,6 +10583,29 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
>  	    }
>  	  else if (l == 1 && last[0] == 'C')
>  	    break;
> +	  else if (l == 1 && last[0] == 'N')
> +	    {
> +	      ins->has_nf = true;
> +
> +	      if (ins->vex.nf == true)
> +		{
> +		  *ins->obufp++ = '{';
> +		  *ins->obufp++ = 'n';
> +		  *ins->obufp++ = 'f';
> +		  *ins->obufp++ = '}';
> +		  *ins->obufp++ = ' ';
> +		}

Do we really need two booleans here? Can't you simply clear ->vex.nf here,
making print_insn() spot when it's still set?

> +	      else if (ins->evex_type == evex_from_legacy && !ins->vex.b)
> +		{
> +		  *ins->obufp++ = '{';
> +		  *ins->obufp++ = 'e';
> +		  *ins->obufp++ = 'v';
> +		  *ins->obufp++ = 'e';
> +		  *ins->obufp++ = 'x';
> +		  *ins->obufp++ = '}';
> +		  *ins->obufp++ = ' ';
> +		}

This looks unrelated (by the title perhaps more related to the other patch
you sent subsequently), and is also not tested anywhere if I'm not mistaken.
I don't mind it being kept here, but besides needing at least minimal
testing this is then also something that wants mentioning in the
description (for going beyond the basic purpose of the patch). Plus this
effect also needs mentioning above in the documentation of "NF".

Finally for both parts: Why not oappend() or even oappend_with_style()? I
realize we have other similar pieces of code, but I question their
correctness the latest after styling was added.

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -310,32 +310,42 @@ sti, 0xfb, 0, NoSuf, {}
>  // Arithmetic.
>  add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
>  add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +add, 0x0, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  add, 0x83/0, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>  add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
>  add, 0x80/0, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
>  add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

As before, this (and similar new ones) can also be picked up without use of
{nf}, which will want testing. If you deliberately defer adding such a test,
this needs saying in the description.

One further remark: In the course of adding APX support the set of templates
for ADD and its sibling ALU ops was bumped from 4 to 10. There was quite a
bit of redundancy between these 7 groups before, but it's growing much worse
now. Did you consider templatizing them up front? This may even be worthwhile
for just the ...

>  inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
>  inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
>  inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

... pair of INC/DEC as well, despite it their number only going from 2 to 4.
And quite certainly also for others below.

> @@ -434,24 +464,34 @@ imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|R
>  
>  div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  div, 0xf6/6, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
> +div, 0xf6/6, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>  idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
> +idiv, 0xf6/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

What about the secondary forms with an explicit destination operand?

> @@ -2027,6 +2090,7 @@ blsi, 0xf3/3, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVV
>  blsmsk, 0xf3/2, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
>  blsr, 0xf3/1, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
>  tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> +tzcnt, 0xf4, BMI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }

Like e.g. here, ...

> @@ -2104,9 +2168,11 @@ insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM }
>  
>  // LZCNT instruction
>  lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> +lzcnt, 0xf5, LZCNT|APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }

... I think you mean LZCNT&APX_F here.

>  // POPCNT instruction
>  popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> +popcnt, 0x88, POPCNT|APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }

Whereas here it ought to be just APX_F if the doc is to be trusted.

Jan
  
Jan Beulich March 8, 2024, 10:40 a.m. UTC | #2
On 04.03.2024 09:15, Cui, Lili wrote:
> @@ -10564,6 +10583,29 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
>  	    }
>  	  else if (l == 1 && last[0] == 'C')
>  	    break;
> +	  else if (l == 1 && last[0] == 'N')
> +	    {
> +	      ins->has_nf = true;
> +
> +	      if (ins->vex.nf == true)
> +		{
> +		  *ins->obufp++ = '{';
> +		  *ins->obufp++ = 'n';
> +		  *ins->obufp++ = 'f';
> +		  *ins->obufp++ = '}';
> +		  *ins->obufp++ = ' ';
> +		}
> +	      else if (ins->evex_type == evex_from_legacy && !ins->vex.b)

Please leverage here the

#define nd b

that we have higher up in the file.

Jan
  
Cui, Lili March 11, 2024, 1:54 p.m. UTC | #3
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, March 8, 2024 5:36 PM
> To: Cui, Lili <lili.cui@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH V2] Support APX NF
> 
> On 04.03.2024 09:15, Cui, Lili wrote:
> > gas/ChangeLog:
> >
> >        * NEWS: Support Intel APX NF.
> >        * config/tc-i386.c (enum i386_error): Add unsupported_nf.
> >        (struct _i386_insn): Add has_nf.
> >        (is_apx_evex_encoding): Ditto.
> >        (build_apx_evex_prefix): Encode the NF bit.
> >        (md_assemble): Handle unsupported_nf.
> >        (parse_insn): Handle Prefix_NF.
> >        (can_convert_NDD_to_legacy):
> >        (match_template): Support D for APX_F insns.
> >        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for
> NF bit.
> >        * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
> >        * testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
> >        * testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
> >        * testsuite/gas/i386/x86-64.exp: Add apx nf tests.
> >        * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
> >        * testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
> >        * testsuite/gas/i386/x86-64-apx-nf.s: Ditto.
> >
> > opcodes/ChangeLog:
> >
> >        * i386-dis-evex.h: Add %XN to the instructions that support APX NF and
> >        add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
> >        * i386-dis-evex-reg.h: Ditto.
> >        * i386-dis.c (struct instr_info): Add nf.
> >        (struct dis386): Add "NF" for EVEX.NF.
> >        (get_valid_dis386): Set ins->vex.nf.
> >        (print_insn): Handle ins.vex.nf.
> >        (putop): Handle "%NF".
> >        * i386-opc.h (Prefix_NoOptimize): Adjust the value.
> 
> Stale entry? As asked for before: If you provide this information, it needs to be
> adjusted as patch contents actually changes.
> 
> >        (Prefix_NF): New.
> >        * i386-opc.tbl: Add new entries for the instructions that support APX NF.
> 
> ... plus a few that don't (while others that don't and aren't of use except when
> used with {evex} were added prematurely).
> 

Ok.

> > @@ -6655,6 +6663,9 @@ md_assemble (char *line)
> >  	case unsupported_EGPR_for_addressing:
> >  	  err_msg = _("extended GPR cannot be used as base/index");
> >  	  break;
> > +	case unsupported_nf:
> > +	  err_msg = _("unsupported NF");
> > +	  break;
> 
> "{nf} unsupported" (yielding an overall better complete diagnostic)?
> 

Ok.

> > @@ -7218,6 +7229,11 @@ parse_insn (const char *line, char *mnemonic,
> bool prefix_only)
> >  		  /* {rex2} */
> >  		  i.rex2_encoding = true;
> >  		  break;
> > +		case Prefix_NF:
> > +		  /* {nf} */
> > +		  i.has_nf = true;
> > +		  i.encoding = encoding_evex;
> > +		  break;
> 
> It's not quite as easy, I'm afraid: Have you thought of the "{vex} {nf} ..."
> case? (I think I previously indicated that their combination, actually in either
> order, needs properly rejecting.) Without having spent much thought on it,
> perhaps it would suffice to check here that the field is still encoding_default,
> and leave the value alone otherwise (in order to reject bad combinations
> elsewhere).
> 
Oh, good point. Do you think it's ok to report bad outside of "switch"?

                case Prefix_NF:
                  /* {nf} */
                  i.has_nf = true;
-                 i.encoding = encoding_evex;
+                 if (i.encoding == encoding_default)
+                   i.encoding = encoding_evex;
                  break;
                case Prefix_NoOptimize:
                  /* {nooptimize} */
                  i.no_optimize = true;
                  break;
                default:
                  abort ();
                }
+             if (i.has_nf && i.encoding != encoding_evex)
+               {
+                 as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
+                 return NULL;
+               }


> > --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
> > +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
> > @@ -23,7 +23,7 @@ _start:
> >  	.insn EVEX.L1.66.M12.W0 0x60, %di, %ax
> >
> >  	#EVEX_MAP4 movbe %r18w,%ax set EVEX.z == 0b1.
> > -	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k7}{z}
> > +	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k3}{z}
> 
> What's going on here ...
> 
> > @@ -33,17 +33,25 @@ _start:
> >  	.insn EVEX.L1.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx
> >
> >  	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[23](EVEX.z) ==
> 0b1
> > -	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k7}{z}
> > +	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k3}{z}
> 
> ... and here? This is the kind of thing that wants mentioning in the patch
> description. And once again, especially for larger patches it is generally a bad
> idea if they come with only legacy ChangeLog entries:
> These only say "what", never "why". (That said, I think I see why the change is
> needed.)
> 

Do you remember that you asked a bad report for illegal use of nf bit? When we use K7 it sets the nf bit, not wanting to lose their original testing purpose due to the interception of nf, I adjusted its value.

> Additionally may I ask that you get used to providing a brief revision log when
> sending new versions of earlier patches? This helps reviewers when they did
> look at the earlier version(s).
> 

Okay, I'll list the changes I think are important.

> >  #EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[20](EVEX.b) ==
> 0b1
> >  	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx){1to8}, %rcx
> >
> >  	#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
> >  	.byte 0x62, 0xf4, 0xe4, 0x08, 0xff, 0x04, 0x08
> > +
> >  	# pop2 %rax, %r8 set EVEX.ND=0.
> >  	.byte 0x62, 0xf4, 0x3c, 0x08, 0x8f, 0xc0
> >  	.byte 0xff, 0xff, 0xff
> > +
> >  	# pop2 %rax, %r8 set EVEX.vvvv = 1111.
> >  	.insn EVEX.L0.M4.W0 0x8f,  %rax, {rn-sae},%r8
> > +
> >  	# pop2 %r8, %r8.
> >  	.byte 0x62, 0xd4, 0x3c, 0x18, 0x8f, 0xc0
> > +	.byte 0xff, 0xff
> 
> As indicated - this would better be avoided by picking a more suitable
> ModR/M byte on the earlier line. Using %r11 instead of %r8 ought to do just
> fine here, I suppose.
> 

Yes, it works.

> > +	#EVEX_MAP4 movbe %r18w,%ax set EVEX.nf = 1.
> > +        .insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k4}
> 
> Nit: Inconsistent indentation.

Done.

> 
> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s
> >[...]
> > +	{nf}	rorq	%cl, 291(%r8, %rax, 4)
> > +	{nf}	ror	%cl, 291(%r8, %rax, 4), %r9
> > +	{nf}	sar	$1, %bl
> > +	{nf}	sar	$1, %bl, %dl
> > +	{nf}	sar	$1, %dx
> > +	{nf}	sar	$1, %dx, %ax
> > +	{nf}	sar	$1, %ecx
> > +	{nf}	sar	$1, %ecx, %edx
> > +	{nf}	sar	$1, %r9
> > +	{nf}	sar	$1, %r9, %r31
> > +	{nf}	sarb	$1, 291(%r8, %rax, 4)
> > +	{nf}	sar	$1, 291(%r8, %rax, 4), %bl
> > +	{nf}	sarw	$1, 291(%r8, %rax, 4)
> > +	{nf}	sar	$1, 291(%r8, %rax, 4), %dx
> > +	{nf}	sarl	$1, 291(%r8, %rax, 4)
> > +	{nf}	sar	$1, 291(%r8, %rax, 4), %ecx
> > +	{nf}	sarq	$1, 291(%r8, %rax, 4)
> > +	{nf}	sar	$1, 291(%r8, %rax, 4), %r9
> > +	{nf}	sar	$123, %bl
> > +	{nf}	sar	$123, %bl, %dl
> > +	{nf}	sar	$123, %dx
> > +	{nf}	sar	$123, %dx, %ax
> > +	{nf}	sar	$123, %ecx
> > +	{nf}	sar	$123, %ecx, %edx
> > +	{nf}	sar	$123, %r9
> > +	{nf}	sar	$123, %r9, %r31
> > +	{nf}	sarb	$123, 291(%r8, %rax, 4)
> > +	{nf}	sar	$123, 291(%r8, %rax, 4), %bl
> > +	{nf}	sarw	$123, 291(%r8, %rax, 4)
> > +	{nf}	sar	$123, 291(%r8, %rax, 4), %dx
> > +	{nf}	sarl	$123, 291(%r8, %rax, 4)
> > +	{nf}	sar	$123, 291(%r8, %rax, 4), %ecx
> > +	{nf}	sarq	$123, 291(%r8, %rax, 4)
> > +	{nf}	sar	$123, 291(%r8, %rax, 4), %r9
> > +	{nf}	sar	%cl, %bl
> > +	{nf}	sar	%cl, %bl, %dl
> > +	{nf}	sar	%cl, %dx
> > +	{nf}	sar	%cl, %dx, %ax
> > +	{nf}	sar	%cl, %ecx
> > +	{nf}	sar	%cl, %ecx, %edx
> > +	{nf}	sar	%cl, %r9
> > +	{nf}	sar	%cl, %r9, %r31
> > +	{nf}	sarb	%cl, 291(%r8, %rax, 4)
> > +	{nf}	sar	%cl, 291(%r8, %rax, 4), %bl
> > +	{nf}	sarw	%cl, 291(%r8, %rax, 4)
> > +	{nf}	sar	%cl, 291(%r8, %rax, 4), %dx
> > +	{nf}	sarl	%cl, 291(%r8, %rax, 4)
> > +	{nf}	sar	%cl, 291(%r8, %rax, 4), %ecx
> > +	{nf}	sarq	%cl, 291(%r8, %rax, 4)
> > +	{nf}	sar	%cl, 291(%r8, %rax, 4), %r9
> > +	{nf}	sal	$1, %bl
> > +	{nf}	sal	$1, %bl, %dl
> 
> Hmm "sal" sorts ahead of "sar", doesn't it?
> 

Ok.

> > --- a/opcodes/i386-dis-evex-reg.h
> > +++ b/opcodes/i386-dis-evex-reg.h
> > @@ -51,33 +51,33 @@
> >    },
> >    /* REG_EVEX_MAP4_80 */
> >    {
> > -    { "addA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "orA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > +    { "%NFaddA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > +    { "%NForA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> >      { "adcA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> >      { "sbbA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> 
> You (correctly) leave these alone.
> 
> > @@ -87,25 +87,33 @@
> >    {
> >      { Bad_Opcode },
> >      { Bad_Opcode },
> > -    { "notA",	{ VexGb, Eb }, NO_PREFIX },
> > -    { "negA",	{ VexGb, Eb }, NO_PREFIX },
> > +    { "%NFnotA",	{ VexGb, Eb }, NO_PREFIX },
> 
> Why does this gain %NF then?
> 

Removed %NF for 'not'.

> > @@ -1815,6 +1817,8 @@ struct dis386 {
> >     "XV" => print "{vex} " pseudo prefix
> >     "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
> >  	   is used by an EVEX-encoded (AVX512VL) instruction.
> > +   "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1.
> > +	   a valid encoding.
> 
> What is this 2nd line, not even a complete sentence, supposed to be saying?
>
 
Dropped.

> > @@ -2619,25 +2623,25 @@ static const struct dis386 reg_table[][8] = {
> >    },
> >    /* REG_C0 */
> >    {
> > -    { "rolA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "rorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "rclA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "rcrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "shlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "shrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "shlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > -    { "sarA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > +    { "%NFrolA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > +    { "%NFrorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > +    { "%NFrclA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> > +    { "%NFrcrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
> 
> Like NOT, RC{L,R} look to be wrongly being modified here. Interestingly for
> D0...D3 you leave them alone.
> 

I also found this issue and fixed them when I rebase {evex} patche last week. :) 

> > @@ -9147,6 +9151,10 @@ get_valid_dis386 (const struct dis386 *dp,
> instr_info *ins)
> >        ins->vex.v = *ins->codep & 0x8;
> >        ins->vex.mask_register_specifier = *ins->codep & 0x7;
> >        ins->vex.zeroing = *ins->codep & 0x80;
> > +      /* Set the NF bit for the EVEX instruction extended from the legacy or
> > +	 vex instruction, this bit will be cleared when it can be confirmed
> > +	 that its defaut type is evex.  */
> > +      ins->vex.nf = *ins->codep & 0x4;
> 
> Whow or what is "its" in the comment? Also nit: "default". Assuming it's the
> insn that's meant, how about "when it's an evex_default one"?
> 

Done, thanks.

> > @@ -9600,10 +9608,21 @@ print_insn (bfd_vma pc, disassemble_info
> *info, int intel_syntax)
> >  	  && ins.vex.prefix == DATA_PREFIX_OPCODE)
> >  	sizeflag ^= DFLAG;
> >
> > +      if(ins.evex_type == evex_default)
> > +	ins.vex.nf = false;
> > +      else
> > +	/* For EVEX-promoted formats, we need to clear EVEX.NF (For ccmp
> and
> > +	   ctest, they will be cleared separately.) in mask_register_specifier
> > +	   and keep the low 2 bits of mask_register_specifier to report errors
> > +	   for invalid cases.*/
> > +	ins.vex.mask_register_specifier &= 0x3;
> > +
> >        if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
> >  	{
> >  	  if (!get_sib (&ins, sizeflag))
> >  	    goto fetch_error_out;
> > +	  if (!ins.has_nf && ins.vex.nf)
> > +	    oappend (&ins, "{bad}");
> 
> As can be seen from the testcase additions, this suffixes onto the insn
> menmonic. Since it's a bogus (pseudo) prefix, maybe better also print as such,
> and then maybe also indicate what it is that is bad (e.g. {bad-nf})?
> 

Good advice.

> > @@ -10564,6 +10583,29 @@ putop (instr_info *ins, const char
> *in_template, int sizeflag)
> >  	    }
> >  	  else if (l == 1 && last[0] == 'C')
> >  	    break;
> > +	  else if (l == 1 && last[0] == 'N')
> > +	    {
> > +	      ins->has_nf = true;
> > +
> > +	      if (ins->vex.nf == true)
> > +		{
> > +		  *ins->obufp++ = '{';
> > +		  *ins->obufp++ = 'n';
> > +		  *ins->obufp++ = 'f';
> > +		  *ins->obufp++ = '}';
> > +		  *ins->obufp++ = ' ';
> > +		}
> 
> Do we really need two booleans here? Can't you simply clear ->vex.nf here,
> making print_insn() spot when it's still set?

It's a good idea to drop has_nf, vex.nf is cleared after it is consumed, and move the invalidity check after the operand printing, because we will add ccmp and cctest whose vex.nf is cleaned up in the *fixup() function.

Thanks,
Lili.
  
Jan Beulich March 11, 2024, 2:09 p.m. UTC | #4
On 11.03.2024 14:54, Cui, Lili wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, March 8, 2024 5:36 PM
>>
>> On 04.03.2024 09:15, Cui, Lili wrote:
>>> @@ -7218,6 +7229,11 @@ parse_insn (const char *line, char *mnemonic,
>> bool prefix_only)
>>>  		  /* {rex2} */
>>>  		  i.rex2_encoding = true;
>>>  		  break;
>>> +		case Prefix_NF:
>>> +		  /* {nf} */
>>> +		  i.has_nf = true;
>>> +		  i.encoding = encoding_evex;
>>> +		  break;
>>
>> It's not quite as easy, I'm afraid: Have you thought of the "{vex} {nf} ..."
>> case? (I think I previously indicated that their combination, actually in either
>> order, needs properly rejecting.) Without having spent much thought on it,
>> perhaps it would suffice to check here that the field is still encoding_default,
>> and leave the value alone otherwise (in order to reject bad combinations
>> elsewhere).
>>
> Oh, good point. Do you think it's ok to report bad outside of "switch"?
> 
>                 case Prefix_NF:
>                   /* {nf} */
>                   i.has_nf = true;
> -                 i.encoding = encoding_evex;
> +                 if (i.encoding == encoding_default)
> +                   i.encoding = encoding_evex;
>                   break;
>                 case Prefix_NoOptimize:
>                   /* {nooptimize} */
>                   i.no_optimize = true;
>                   break;
>                 default:
>                   abort ();
>                 }
> +             if (i.has_nf && i.encoding != encoding_evex)
> +               {
> +                 as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
> +                 return NULL;
> +               }

Where the checking is done is secondary to me. My primary point is that
the above isn't correct: There are more encoding variants than just
vex, vex3, and evex.

That said, reporting the error right here may lead to multiple identical
errors being reported for a single line of input. This wants avoiding,
at which point placing the check here is ruled out.

>>> --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
>>> +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
>>> @@ -23,7 +23,7 @@ _start:
>>>  	.insn EVEX.L1.66.M12.W0 0x60, %di, %ax
>>>
>>>  	#EVEX_MAP4 movbe %r18w,%ax set EVEX.z == 0b1.
>>> -	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k7}{z}
>>> +	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k3}{z}
>>
>> What's going on here ...
>>
>>> @@ -33,17 +33,25 @@ _start:
>>>  	.insn EVEX.L1.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx
>>>
>>>  	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[23](EVEX.z) ==
>> 0b1
>>> -	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k7}{z}
>>> +	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k3}{z}
>>
>> ... and here? This is the kind of thing that wants mentioning in the patch
>> description. And once again, especially for larger patches it is generally a bad
>> idea if they come with only legacy ChangeLog entries:
>> These only say "what", never "why". (That said, I think I see why the change is
>> needed.)
> 
> Do you remember that you asked a bad report for illegal use of nf bit?

Yes.

> When we use K7 it sets the nf bit, not wanting to lose their original testing purpose due to the interception of nf, I adjusted its value.

Yes. What's missing is an explanation for the need of this in the patch
description. Without this you made me work out what this change is about,
when otherwise I would have had to merely check that what you say fits
what changes (i.e. me then knowing what exactly to look for).

Jan
  
Cui, Lili March 12, 2024, 6:12 a.m. UTC | #5
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, March 11, 2024 10:10 PM
> To: Cui, Lili <lili.cui@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH V2] Support APX NF
> 
> On 11.03.2024 14:54, Cui, Lili wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Friday, March 8, 2024 5:36 PM
> >>
> >> On 04.03.2024 09:15, Cui, Lili wrote:
> >>> @@ -7218,6 +7229,11 @@ parse_insn (const char *line, char
> *mnemonic,
> >> bool prefix_only)
> >>>  		  /* {rex2} */
> >>>  		  i.rex2_encoding = true;
> >>>  		  break;
> >>> +		case Prefix_NF:
> >>> +		  /* {nf} */
> >>> +		  i.has_nf = true;
> >>> +		  i.encoding = encoding_evex;
> >>> +		  break;
> >>
> >> It's not quite as easy, I'm afraid: Have you thought of the "{vex} {nf} ..."
> >> case? (I think I previously indicated that their combination,
> >> actually in either order, needs properly rejecting.) Without having
> >> spent much thought on it, perhaps it would suffice to check here that
> >> the field is still encoding_default, and leave the value alone
> >> otherwise (in order to reject bad combinations elsewhere).
> >>
> > Oh, good point. Do you think it's ok to report bad outside of "switch"?
> >
> >                 case Prefix_NF:
> >                   /* {nf} */
> >                   i.has_nf = true;
> > -                 i.encoding = encoding_evex;
> > +                 if (i.encoding == encoding_default)
> > +                   i.encoding = encoding_evex;
> >                   break;
> >                 case Prefix_NoOptimize:
> >                   /* {nooptimize} */
> >                   i.no_optimize = true;
> >                   break;
> >                 default:
> >                   abort ();
> >                 }
> > +             if (i.has_nf && i.encoding != encoding_evex)
> > +               {
> > +                 as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
> > +                 return NULL;
> > +               }
> 
> Where the checking is done is secondary to me. My primary point is that the
> above isn't correct: There are more encoding variants than just vex, vex3, and
> evex.
> 
> That said, reporting the error right here may lead to multiple identical errors
> being reported for a single line of input. This wants avoiding, at which point
> placing the check here is ruled out.
> 

Sorry,  I didn’t get you here, do you think the current implementation is wrong? I think for parse_insn stage i.encodin only has those encoding variants, do you think we need to move further back? Maybe put them together with REX/REX2 prefix checking?

      /* Check for explicit REX prefix.  */
      if (i.prefix[REX_PREFIX] || i.rex_encoding)
        {
          as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm));
          return;
        }

      /* Check for explicit REX2 prefix.  */
      if (i.rex2_encoding)
        {
          as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm));
          return;
        }

Thanks,
Lili.
  
Jan Beulich March 12, 2024, 7:46 a.m. UTC | #6
On 12.03.2024 07:12, Cui, Lili wrote:
> 
> 
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Monday, March 11, 2024 10:10 PM
>> To: Cui, Lili <lili.cui@intel.com>
>> Cc: hjl.tools@gmail.com; binutils@sourceware.org
>> Subject: Re: [PATCH V2] Support APX NF
>>
>> On 11.03.2024 14:54, Cui, Lili wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Friday, March 8, 2024 5:36 PM
>>>>
>>>> On 04.03.2024 09:15, Cui, Lili wrote:
>>>>> @@ -7218,6 +7229,11 @@ parse_insn (const char *line, char
>> *mnemonic,
>>>> bool prefix_only)
>>>>>  		  /* {rex2} */
>>>>>  		  i.rex2_encoding = true;
>>>>>  		  break;
>>>>> +		case Prefix_NF:
>>>>> +		  /* {nf} */
>>>>> +		  i.has_nf = true;
>>>>> +		  i.encoding = encoding_evex;
>>>>> +		  break;
>>>>
>>>> It's not quite as easy, I'm afraid: Have you thought of the "{vex} {nf} ..."
>>>> case? (I think I previously indicated that their combination,
>>>> actually in either order, needs properly rejecting.) Without having
>>>> spent much thought on it, perhaps it would suffice to check here that
>>>> the field is still encoding_default, and leave the value alone
>>>> otherwise (in order to reject bad combinations elsewhere).
>>>>
>>> Oh, good point. Do you think it's ok to report bad outside of "switch"?
>>>
>>>                 case Prefix_NF:
>>>                   /* {nf} */
>>>                   i.has_nf = true;
>>> -                 i.encoding = encoding_evex;
>>> +                 if (i.encoding == encoding_default)
>>> +                   i.encoding = encoding_evex;
>>>                   break;
>>>                 case Prefix_NoOptimize:
>>>                   /* {nooptimize} */
>>>                   i.no_optimize = true;
>>>                   break;
>>>                 default:
>>>                   abort ();
>>>                 }
>>> +             if (i.has_nf && i.encoding != encoding_evex)
>>> +               {
>>> +                 as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
>>> +                 return NULL;
>>> +               }
>>
>> Where the checking is done is secondary to me. My primary point is that the
>> above isn't correct: There are more encoding variants than just vex, vex3, and
>> evex.
>>
>> That said, reporting the error right here may lead to multiple identical errors
>> being reported for a single line of input. This wants avoiding, at which point
>> placing the check here is ruled out.
>>
> 
> Sorry,  I didn’t get you here, do you think the current implementation is wrong? I think for parse_insn stage i.encodin only has those encoding variants,

Hmm, you're right - operands weren't parsed yet at this point. While ...

> do you think we need to move further back? Maybe put them together with REX/REX2 prefix checking?
> 
>       /* Check for explicit REX prefix.  */
>       if (i.prefix[REX_PREFIX] || i.rex_encoding)
>         {
>           as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm));
>           return;
>         }
> 
>       /* Check for explicit REX2 prefix.  */
>       if (i.rex2_encoding)
>         {
>           as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm));
>           return;
>         }

... this would overall seem to be a more logical place to have such checks,
I'd like to take back my earlier comment then: By having the check in
parse_insn(), .insn handling is then also covered right away.

Jan
  
Cui, Lili March 12, 2024, 8:51 a.m. UTC | #7
> >>>> On 04.03.2024 09:15, Cui, Lili wrote:
> >>>>> @@ -7218,6 +7229,11 @@ parse_insn (const char *line, char
> >> *mnemonic,
> >>>> bool prefix_only)
> >>>>>  		  /* {rex2} */
> >>>>>  		  i.rex2_encoding = true;
> >>>>>  		  break;
> >>>>> +		case Prefix_NF:
> >>>>> +		  /* {nf} */
> >>>>> +		  i.has_nf = true;
> >>>>> +		  i.encoding = encoding_evex;
> >>>>> +		  break;
> >>>>
> >>>> It's not quite as easy, I'm afraid: Have you thought of the "{vex} {nf} ..."
> >>>> case? (I think I previously indicated that their combination,
> >>>> actually in either order, needs properly rejecting.) Without having
> >>>> spent much thought on it, perhaps it would suffice to check here
> >>>> that the field is still encoding_default, and leave the value alone
> >>>> otherwise (in order to reject bad combinations elsewhere).
> >>>>
> >>> Oh, good point. Do you think it's ok to report bad outside of "switch"?
> >>>
> >>>                 case Prefix_NF:
> >>>                   /* {nf} */
> >>>                   i.has_nf = true;
> >>> -                 i.encoding = encoding_evex;
> >>> +                 if (i.encoding == encoding_default)
> >>> +                   i.encoding = encoding_evex;
> >>>                   break;
> >>>                 case Prefix_NoOptimize:
> >>>                   /* {nooptimize} */
> >>>                   i.no_optimize = true;
> >>>                   break;
> >>>                 default:
> >>>                   abort ();
> >>>                 }
> >>> +             if (i.has_nf && i.encoding != encoding_evex)
> >>> +               {
> >>> +                 as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
> >>> +                 return NULL;
> >>> +               }
> >>
> >> Where the checking is done is secondary to me. My primary point is
> >> that the above isn't correct: There are more encoding variants than
> >> just vex, vex3, and evex.
> >>
> >> That said, reporting the error right here may lead to multiple
> >> identical errors being reported for a single line of input. This
> >> wants avoiding, at which point placing the check here is ruled out.
> >>
> >
> > Sorry,  I didn’t get you here, do you think the current implementation
> > is wrong? I think for parse_insn stage i.encodin only has those
> > encoding variants,
> 
> Hmm, you're right - operands weren't parsed yet at this point. While ...
> 
> > do you think we need to move further back? Maybe put them together with
> REX/REX2 prefix checking?
> >
> >       /* Check for explicit REX prefix.  */
> >       if (i.prefix[REX_PREFIX] || i.rex_encoding)
> >         {
> >           as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm));
> >           return;
> >         }
> >
> >       /* Check for explicit REX2 prefix.  */
> >       if (i.rex2_encoding)
> >         {
> >           as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm));
> >           return;
> >         }
> 
> ... this would overall seem to be a more logical place to have such checks, I'd
> like to take back my earlier comment then: By having the check in
> parse_insn(), .insn handling is then also covered right away.
> 
> Jan

Ok.

Thanks,
Lili.
  
Cui, Lili March 12, 2024, 1:22 p.m. UTC | #8
> > @@ -10564,6 +10583,29 @@ putop (instr_info *ins, const char
> *in_template, int sizeflag)
> >  	    }
> >  	  else if (l == 1 && last[0] == 'C')
> >  	    break;
> > +	  else if (l == 1 && last[0] == 'N')
> > +	    {
> > +	      ins->has_nf = true;
> > +
> > +	      if (ins->vex.nf == true)
> > +		{
> > +		  *ins->obufp++ = '{';
> > +		  *ins->obufp++ = 'n';
> > +		  *ins->obufp++ = 'f';
> > +		  *ins->obufp++ = '}';
> > +		  *ins->obufp++ = ' ';
> > +		}
> > +	      else if (ins->evex_type == evex_from_legacy && !ins->vex.b)
> > +		{
> > +		  *ins->obufp++ = '{';
> > +		  *ins->obufp++ = 'e';
> > +		  *ins->obufp++ = 'v';
> > +		  *ins->obufp++ = 'e';
> > +		  *ins->obufp++ = 'x';
> > +		  *ins->obufp++ = '}';
> > +		  *ins->obufp++ = ' ';
> > +		}
> 
> This looks unrelated (by the title perhaps more related to the other patch you
> sent subsequently), and is also not tested anywhere if I'm not mistaken.
> I don't mind it being kept here, but besides needing at least minimal testing
> this is then also something that wants mentioning in the description (for going
> beyond the basic purpose of the patch). Plus this effect also needs mentioning
> above in the documentation of "NF".
> 
> Finally for both parts: Why not oappend() or even oappend_with_style()? I
> realize we have other similar pieces of code, but I question their correctness
> the latest after styling was added.
> 

Change it to oappend() and move it to another patch.

> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -310,32 +310,42 @@ sti, 0xfb, 0, NoSuf, {}  // Arithmetic.
> >  add, 0x0, APX_F,
> > D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Reg8|Reg16|Reg32|Reg64 }  add, 0x0, 0,
> > D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +add, 0x0, APX_F,
> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +}
> >  add, 0x83/0, APX_F,
> > Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF,
> { Imm8S,
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }  add,
> > 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S,
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S,
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >  add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S,
> > Acc|Byte|Word|Dword|Qword }  add, 0x80/0, APX_F,
> > W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, {
> > Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Reg8|Reg16|Reg32|Reg64}  add, 0x80/0, 0,
> > W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> > +Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +}
> 
> As before, this (and similar new ones) can also be picked up without use of
> {nf}, which will want testing. If you deliberately defer adding such a test, this
> needs saying in the description.
> 

Ok.

> One further remark: In the course of adding APX support the set of templates
> for ADD and its sibling ALU ops was bumped from 4 to 10. There was quite a
> bit of redundancy between these 7 groups before, but it's growing much
> worse now. Did you consider templatizing them up front? This may even be
> worthwhile for just the ...
> 

I try to add something like this, but it doesn't work. Seems that it only supports differentiation based on mnemonic.

+<cpu1:attr, 0:HLEPrefixLock, APX_F:EVexMap4|NF>
+<cpu2:attr, 0:HLEPrefixLock|Optimize, APX_F:EVexMap4|NF>
+
 // Arithmetic.
 add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-add, 0x0, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+add<cpu1>, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

> >  inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }  inc,
> > 0xfe/0, APX_F,
> W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF,
> > {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64}
> > inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> 
> ... pair of INC/DEC as well, despite it their number only going from 2 to 4.
> And quite certainly also for others below.
> 
> > @@ -434,24 +464,34 @@ imul, 0x69, i186,
> > Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S,
> Reg16|R
> >
> >  div, 0xf6/6, 0, W|Modrm|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  div, 0xf6/6, 0,
> > W|CheckOperandSize|Modrm|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Acc|Byte|Word|Dword|Qword }
> > +div, 0xf6/6, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >  idiv, 0xf6/7, 0, W|Modrm|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  idiv, 0xf6/7, 0,
> > W|CheckOperandSize|Modrm|No_sSuf, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Acc|Byte|Word|Dword|Qword }
> > +idiv, 0xf6/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> 
> What about the secondary forms with an explicit destination operand?
> 

The doc does not extend the second format. Maybe it is related to Acc. I found that basically all instructions involving Acc are not extended, except SHA.

> > @@ -2027,6 +2090,7 @@ blsi, 0xf3/3, APX_F(BMI),
> > Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVV
> >  blsmsk, 0xf3/2, APX_F(BMI),
> >
> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSu
> f|No_wSu
> > f|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
> > blsr, 0xf3/1, APX_F(BMI),
> >
> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSu
> f|No_wSu
> > f|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
> > tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, {
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > +tzcnt, 0xf4, BMI&APX_F,
> > +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> 
> Like e.g. here, ...
> 
> > @@ -2104,9 +2168,11 @@ insertq, 0xf20f78, SSE4a, Modrm|NoSuf,
> { Imm8,
> > Imm8, RegXMM, RegXMM }
> >
> >  // LZCNT instruction
> >  lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, {
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > +lzcnt, 0xf5, LZCNT|APX_F,
> > +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> 
> ... I think you mean LZCNT&APX_F here.
> 
> >  // POPCNT instruction
> >  popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf,
> {
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > +popcnt, 0x88, POPCNT|APX_F,
> > +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> 
> Whereas here it ought to be just APX_F if the doc is to be trusted.
> 

I think they should be LZCNT&APX_F and POPCNT&APX_F, why do you think POPCNT is special? I suspect I've missed something.

Thanks,
Lili.
  
Jan Beulich March 12, 2024, 1:53 p.m. UTC | #9
On 12.03.2024 14:22, Cui, Lili wrote:
>>> --- a/opcodes/i386-opc.tbl
>>> +++ b/opcodes/i386-opc.tbl
>>> @@ -310,32 +310,42 @@ sti, 0xfb, 0, NoSuf, {}  // Arithmetic.
>>>  add, 0x0, APX_F,
>>> D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
>>> Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
>>> Reg8|Reg16|Reg32|Reg64 }  add, 0x0, 0,
>>> D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
>>> Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>> +add, 0x0, APX_F,
>> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
>>> +Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
>>> +}
>>>  add, 0x83/0, APX_F,
>>> Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF,
>> { Imm8S,
>>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }  add,
>>> 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S,
>>> Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>> +add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S,
>>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>>  add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S,
>>> Acc|Byte|Word|Dword|Qword }  add, 0x80/0, APX_F,
>>> W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, {
>>> Imm8|Imm16|Imm32|Imm32S,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
>>> Reg8|Reg16|Reg32|Reg64}  add, 0x80/0, 0,
>>> W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S,
>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>> +add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
>>> +Imm8|Imm16|Imm32|Imm32S,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
>>> +}
>>
>> As before, this (and similar new ones) can also be picked up without use of
>> {nf}, which will want testing. If you deliberately defer adding such a test, this
>> needs saying in the description.
>>
> 
> Ok.
> 
>> One further remark: In the course of adding APX support the set of templates
>> for ADD and its sibling ALU ops was bumped from 4 to 10. There was quite a
>> bit of redundancy between these 7 groups before, but it's growing much
>> worse now. Did you consider templatizing them up front? This may even be
>> worthwhile for just the ...
>>
> 
> I try to add something like this, but it doesn't work. Seems that it only supports differentiation based on mnemonic.
> 
> +<cpu1:attr, 0:HLEPrefixLock, APX_F:EVexMap4|NF>
> +<cpu2:attr, 0:HLEPrefixLock|Optimize, APX_F:EVexMap4|NF>
> +
>  // Arithmetic.
>  add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -add, 0x0, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +add<cpu1>, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }

Differentiating on other than the mnemonic is possible (see e.g. the
mmx and sse templates, which append nothing to the mnemonics) but not
wanted here. The goal of the suggested template is to have something
that covers all 7 mnemonics in one go, including their legacy forms.

>>> @@ -434,24 +464,34 @@ imul, 0x69, i186,
>>> Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S,
>> Reg16|R
>>>
>>>  div, 0xf6/6, 0, W|Modrm|No_sSuf, {
>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  div, 0xf6/6, 0,
>>> W|CheckOperandSize|Modrm|No_sSuf, {
>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
>>> Acc|Byte|Word|Dword|Qword }
>>> +div, 0xf6/6, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
>>> +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>>  idiv, 0xf6/7, 0, W|Modrm|No_sSuf, {
>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  idiv, 0xf6/7, 0,
>>> W|CheckOperandSize|Modrm|No_sSuf, {
>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
>>> Acc|Byte|Word|Dword|Qword }
>>> +idiv, 0xf6/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
>>> +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>
>> What about the secondary forms with an explicit destination operand?
> 
> The doc does not extend the second format. Maybe it is related to Acc.
It certainly is.

> I found that basically all instructions involving Acc are not extended, except SHA.

Well, the SDM doesn't specify DIV or IDIV with a second operand.
Therefore the issue here isn't conformance with the documentation,
but consistency with the pre-existing gas extensions.

>>> @@ -2027,6 +2090,7 @@ blsi, 0xf3/3, APX_F(BMI),
>>> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVV
>>>  blsmsk, 0xf3/2, APX_F(BMI),
>>>
>> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSu
>> f|No_wSu
>>> f|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
>>> blsr, 0xf3/1, APX_F(BMI),
>>>
>> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSu
>> f|No_wSu
>>> f|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
>>> tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, {
>>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>>> +tzcnt, 0xf4, BMI&APX_F,
>>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
>>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>>
>> Like e.g. here, ...
>>
>>> @@ -2104,9 +2168,11 @@ insertq, 0xf20f78, SSE4a, Modrm|NoSuf,
>> { Imm8,
>>> Imm8, RegXMM, RegXMM }
>>>
>>>  // LZCNT instruction
>>>  lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, {
>>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>>> +lzcnt, 0xf5, LZCNT|APX_F,
>>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
>>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>>
>> ... I think you mean LZCNT&APX_F here.
>>
>>>  // POPCNT instruction
>>>  popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf,
>> {
>>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>>> +popcnt, 0x88, POPCNT|APX_F,
>>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
>>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
>>
>> Whereas here it ought to be just APX_F if the doc is to be trusted.
> 
> I think they should be LZCNT&APX_F and POPCNT&APX_F, why do you think POPCNT is special? I suspect I've missed something.

Unless you're looking at a newer version of the APX spec than me,
you'll observe the difference when looking at the respective insn
pages: For LZCNT both CPUID bits are mentioned, while for POPCNT
only APX_F is there.

Jan
  
Cui, Lili March 13, 2024, 2:54 a.m. UTC | #10
> On 12.03.2024 14:22, Cui, Lili wrote:
> >>> --- a/opcodes/i386-opc.tbl
> >>> +++ b/opcodes/i386-opc.tbl
> >>> @@ -310,32 +310,42 @@ sti, 0xfb, 0, NoSuf, {}  // Arithmetic.
> >>>  add, 0x0, APX_F,
> >>> D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
> >>> Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> >>> Reg8|Reg16|Reg32|Reg64 }  add, 0x0, 0,
> >>> D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
> >>> Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>> +add, 0x0, APX_F,
> >> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
> >>> +Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> >>> +}
> >>>  add, 0x83/0, APX_F,
> >>> Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF,
> >> { Imm8S,
> >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> add,
> >>> 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S,
> >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>> +add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF,
> { Imm8S,
> >>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>>  add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S,
> >>> Acc|Byte|Word|Dword|Qword }  add, 0x80/0, APX_F,
> >>> W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, {
> >>> Imm8|Imm16|Imm32|Imm32S,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> >>> Reg8|Reg16|Reg32|Reg64}  add, 0x80/0, 0,
> >>> W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S,
> >>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>> +add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> >>> +Imm8|Imm16|Imm32|Imm32S,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> >>> +}
> >>
> >> As before, this (and similar new ones) can also be picked up without
> >> use of {nf}, which will want testing. If you deliberately defer
> >> adding such a test, this needs saying in the description.
> >>
> >
> > Ok.
> >
> >> One further remark: In the course of adding APX support the set of
> >> templates for ADD and its sibling ALU ops was bumped from 4 to 10.
> >> There was quite a bit of redundancy between these 7 groups before,
> >> but it's growing much worse now. Did you consider templatizing them
> >> up front? This may even be worthwhile for just the ...
> >>
> >
> > I try to add something like this, but it doesn't work. Seems that it only
> supports differentiation based on mnemonic.
> >
> > +<cpu1:attr, 0:HLEPrefixLock, APX_F:EVexMap4|NF> <cpu2:attr,
> > +0:HLEPrefixLock|Optimize, APX_F:EVexMap4|NF>
> > +
> >  // Arithmetic.
> >  add, 0x0, APX_F,
> > D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Reg8|Reg16|Reg32|Reg64 } -add, 0x0, 0,
> > D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > -add, 0x0, APX_F,
> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +add<cpu1>, 0x0, 0,
> D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> > +}
> 
> Differentiating on other than the mnemonic is possible (see e.g. the mmx and
> sse templates, which append nothing to the mnemonics) but not wanted
> here. The goal of the suggested template is to have something that covers all 7
> mnemonics in one go, including their legacy forms.
> 

The handling of <mmx/<sse are clever. The current templates are indeed redundant. Do you mind I create a separate patch to clean up all APX templates instead of in this patch.

> >>> @@ -434,24 +464,34 @@ imul, 0x69, i186,
> >>> Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S,
> >> Reg16|R
> >>>
> >>>  div, 0xf6/6, 0, W|Modrm|No_sSuf, {
> >>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  div, 0xf6/6, 0,
> >>> W|CheckOperandSize|Modrm|No_sSuf, {
> >>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> >>> Acc|Byte|Word|Dword|Qword }
> >>> +div, 0xf6/6, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> >>> +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>>  idiv, 0xf6/7, 0, W|Modrm|No_sSuf, {
> >>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }  idiv, 0xf6/7, 0,
> >>> W|CheckOperandSize|Modrm|No_sSuf, {
> >>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> >>> Acc|Byte|Word|Dword|Qword }
> >>> +idiv, 0xf6/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> >>> +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>
> >> What about the secondary forms with an explicit destination operand?
> >
> > The doc does not extend the second format. Maybe it is related to Acc.
> It certainly is.
> 
> > I found that basically all instructions involving Acc are not extended, except
> SHA.
> 
> Well, the SDM doesn't specify DIV or IDIV with a second operand.
> Therefore the issue here isn't conformance with the documentation, but
> consistency with the pre-existing gas extensions.
>
 
Yes, it is special, and we should extend the second format.

> >>> @@ -2027,6 +2090,7 @@ blsi, 0xf3/3, APX_F(BMI),
> >>> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVV
> >>>  blsmsk, 0xf3/2, APX_F(BMI),
> >>>
> >>
> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSu
> >> f|No_wSu
> >>> f|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
> >>> blsr, 0xf3/1, APX_F(BMI),
> >>>
> >>
> Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSu
> >> f|No_wSu
> >>> f|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
> >>> tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, {
> >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> >>> +tzcnt, 0xf4, BMI&APX_F,
> >>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> >>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> >>
> >> Like e.g. here, ...
> >>
> >>> @@ -2104,9 +2168,11 @@ insertq, 0xf20f78, SSE4a, Modrm|NoSuf,
> >> { Imm8,
> >>> Imm8, RegXMM, RegXMM }
> >>>
> >>>  // LZCNT instruction
> >>>  lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, {
> >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> >>> +lzcnt, 0xf5, LZCNT|APX_F,
> >>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> >>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> >>
> >> ... I think you mean LZCNT&APX_F here.
> >>
> >>>  // POPCNT instruction
> >>>  popcnt, 0xf30fb8, POPCNT,
> Modrm|CheckOperandSize|No_bSuf|No_sSuf,
> >> {
> >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> >>> +popcnt, 0x88, POPCNT|APX_F,
> >>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> >>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> >>
> >> Whereas here it ought to be just APX_F if the doc is to be trusted.
> >
> > I think they should be LZCNT&APX_F and POPCNT&APX_F, why do you think
> POPCNT is special? I suspect I've missed something.
> 
> Unless you're looking at a newer version of the APX spec than me, you'll
> observe the difference when looking at the respective insn
> pages: For LZCNT both CPUID bits are mentioned, while for POPCNT only
> APX_F is there.
> 
You are right. I will double confirm it with doc.

Thanks,
Lili.
  
Jan Beulich March 13, 2024, 7:36 a.m. UTC | #11
On 13.03.2024 03:54, Cui, Lili wrote:
>> On 12.03.2024 14:22, Cui, Lili wrote:
>>>  // Arithmetic.
>>>  add, 0x0, APX_F,
>>> D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
>>> Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
>>> Reg8|Reg16|Reg32|Reg64 } -add, 0x0, 0,
>>> D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
>>> Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>> -add, 0x0, APX_F,
>> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
>>> Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>> +add<cpu1>, 0x0, 0,
>> D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, {
>>> +Reg8|Reg16|Reg32|Reg64,
>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
>>> +}
>>
>> Differentiating on other than the mnemonic is possible (see e.g. the mmx and
>> sse templates, which append nothing to the mnemonics) but not wanted
>> here. The goal of the suggested template is to have something that covers all 7
>> mnemonics in one go, including their legacy forms.
>>
> 
> The handling of <mmx/<sse are clever. The current templates are indeed redundant. Do you mind I create a separate patch to clean up all APX templates instead of in this patch.

Well - it explicitly ought to be a separate patch. Yet FTAOD - afaict such
a new (set of) template(s) should not follow mmx/sse, but rather e.g. fma
or pseudopfx (covering the entire mnemonic then).

Jan
  
Cui, Lili March 18, 2024, 11:21 a.m. UTC | #12
> On 13.03.2024 03:54, Cui, Lili wrote:
> >> On 12.03.2024 14:22, Cui, Lili wrote:
> >>>  // Arithmetic.
> >>>  add, 0x0, APX_F,
> >>> D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
> >>> Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> >>> Reg8|Reg16|Reg32|Reg64 } -add, 0x0, 0,
> >>> D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
> >>> Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>> -add, 0x0, APX_F,
> >> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
> >>> Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>> +add<cpu1>, 0x0, 0,
> >> D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, {
> >>> +Reg8|Reg16|Reg32|Reg64,
> >> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> >>> +}
> >>
> >> Differentiating on other than the mnemonic is possible (see e.g. the
> >> mmx and sse templates, which append nothing to the mnemonics) but not
> >> wanted here. The goal of the suggested template is to have something
> >> that covers all 7 mnemonics in one go, including their legacy forms.
> >>
> >
> > The handling of <mmx/<sse are clever. The current templates are indeed
> redundant. Do you mind I create a separate patch to clean up all APX
> templates instead of in this patch.
> 
> Well - it explicitly ought to be a separate patch. Yet FTAOD - afaict such a new
> (set of) template(s) should not follow mmx/sse, but rather e.g. fma or
> pseudopfx (covering the entire mnemonic then).
> 

Hi Jan, 

Below are two examples of merging, does it meet expectations?

--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c

@@ -1904,11 +1904,15 @@ process_i386_opcodes (FILE *table)
        case '<':
          parse_template (p, lineno);
          continue;
+       case '@':
+         p++;
+         break;
        default:
          if (!marker)
            continue;
          break;
        }

rol and ror can be merged.

-rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-
-ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+<extend10:cpu:attr:reg, +
+       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
+       $legacy:0::, +
+       $nf:APX_F:EVexMap4|NF:>
+
+<extend11:cpu:attr:reg, +
+       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
+       $legacy:i186::, +
+       $nf:APX_F:EVexMap4|NF:>
+
+<extend12:cpu:attr, +
+       $legacy:0:, +
+       $nf:APX_F:EVexMap4|NF>
+
+<mn:opcode, rol:0, ror:1>
+
+@<mn><extend10>, 0xd0/0|<mn:opcode>, <extend10:cpu>, W|Modrm|No_sSuf|<extend10:attr>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }
+
+@<mn><extend11>, 0xc0/0|<mn:opcode>, <extend11:cpu>, W|Modrm|No_sSuf|<extend11:attr>, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend11:reg> }
+
+@<mn><extend10>, 0xd2/0|<mn:opcode>, <extend10:cpu>, W|Modrm|No_sSuf|<extend10:attr>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }
+
+@<mn><extend12>, 0xd0/0|<mn:opcode>, <extend12:cpu>, W|Modrm|No_sSuf|<extend12:attr>, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+
...

The same instruction as add structure was not found. There are always some subtle differences.

+<extend1:cpu:attr:reg, +
+       $ndd:APX_F:C|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
+       $legacy:0:HLEPrefixLock:, +
+       $nf:APX_F:EVexMap4|NF:>
+
+<extend2:cpu:attr:reg, +
+       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg16|Reg32|Reg64, +
+       $legacy:0:HLEPrefixLock:, +
+       $nf:APX_F:EVexMap4|NF:>
+
+<extend3:cpu:attr:reg, +
+       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
+       $legacy:0:HLEPrefixLock:, +
+       $nf:APX_F:EVexMap4|NF:>
+
-add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-add, 0x0, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-add, 0x83/0, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+add<extend1>, 0x0, <extend1:cpu>, D|W|CheckOperandSize|Modrm|No_sSuf|<extend1:attr>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend1:reg> }
+add<extend2>, 0x83/0, <extend2:cpu>, Modrm|No_bSuf|No_sSuf|<extend2:attr>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend2:reg> }
 add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-add, 0x80/0, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
-add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+add<extend3>, 0x80/0, <extend3:cpu>, W|Modrm|No_sSuf|<extend3:attr>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend3:reg> }


Thanks,
Lili.
  
Jan Beulich March 18, 2024, 11:50 a.m. UTC | #13
On 18.03.2024 12:21, Cui, Lili wrote:
>> On 13.03.2024 03:54, Cui, Lili wrote:
>>>> On 12.03.2024 14:22, Cui, Lili wrote:
>>>>>  // Arithmetic.
>>>>>  add, 0x0, APX_F,
>>>>> D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
>>>>> Reg8|Reg16|Reg32|Reg64,
>>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
>>>>> Reg8|Reg16|Reg32|Reg64 } -add, 0x0, 0,
>>>>> D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
>>>>> Reg8|Reg16|Reg32|Reg64,
>>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>>>> -add, 0x0, APX_F,
>>>> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
>>>>> Reg8|Reg16|Reg32|Reg64,
>>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
>>>>> +add<cpu1>, 0x0, 0,
>>>> D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, {
>>>>> +Reg8|Reg16|Reg32|Reg64,
>>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
>>>>> +}
>>>>
>>>> Differentiating on other than the mnemonic is possible (see e.g. the
>>>> mmx and sse templates, which append nothing to the mnemonics) but not
>>>> wanted here. The goal of the suggested template is to have something
>>>> that covers all 7 mnemonics in one go, including their legacy forms.
>>>>
>>>
>>> The handling of <mmx/<sse are clever. The current templates are indeed
>> redundant. Do you mind I create a separate patch to clean up all APX
>> templates instead of in this patch.
>>
>> Well - it explicitly ought to be a separate patch. Yet FTAOD - afaict such a new
>> (set of) template(s) should not follow mmx/sse, but rather e.g. fma or
>> pseudopfx (covering the entire mnemonic then).
>>
> 
> Hi Jan, 
> 
> Below are two examples of merging, does it meet expectations?
> 
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> 
> @@ -1904,11 +1904,15 @@ process_i386_opcodes (FILE *table)
>         case '<':
>           parse_template (p, lineno);
>           continue;
> +       case '@':
> +         p++;
> +         break;
>         default:
>           if (!marker)
>             continue;
>           break;
>         }
> 
> rol and ror can be merged.
> 
> -rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -
> -ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +<extend10:cpu:attr:reg, +
> +       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
> +       $legacy:0::, +
> +       $nf:APX_F:EVexMap4|NF:>
> +
> +<extend11:cpu:attr:reg, +
> +       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
> +       $legacy:i186::, +
> +       $nf:APX_F:EVexMap4|NF:>
> +
> +<extend12:cpu:attr, +
> +       $legacy:0:, +
> +       $nf:APX_F:EVexMap4|NF>

I don't understand these three. I'd have expected all attributes to be
specified ...

> +<mn:opcode, rol:0, ror:1>

... here. Same then for add, where I'd have expected a similar template as the
one above, e.g.

<alu:opcode, add:0, sub:...>

(but of course with more than just "opcode" specified).

> +@<mn><extend10>, 0xd0/0|<mn:opcode>, <extend10:cpu>, W|Modrm|No_sSuf|<extend10:attr>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }
> +
> +@<mn><extend11>, 0xc0/0|<mn:opcode>, <extend11:cpu>, W|Modrm|No_sSuf|<extend11:attr>, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend11:reg> }
> +
> +@<mn><extend10>, 0xd2/0|<mn:opcode>, <extend10:cpu>, W|Modrm|No_sSuf|<extend10:attr>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }
> +
> +@<mn><extend12>, 0xd0/0|<mn:opcode>, <extend12:cpu>, W|Modrm|No_sSuf|<extend12:attr>, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +
> ...
> 
> The same instruction as add structure was not found. There are always some subtle differences.

I expect the issue is with you using just a single "attr", trying to put all
attributes in there. When split (see e.g. <sdh>), folding ought to be possible.

I'd also prefer if we could avoid the need for the leading @.

Anyway - feel free to leave this to me. While not overly nice, I guess we can
live with the growing volume due to what NF wants to add.

Jan

> +<extend1:cpu:attr:reg, +
> +       $ndd:APX_F:C|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
> +       $legacy:0:HLEPrefixLock:, +
> +       $nf:APX_F:EVexMap4|NF:>
> +
> +<extend2:cpu:attr:reg, +
> +       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg16|Reg32|Reg64, +
> +       $legacy:0:HLEPrefixLock:, +
> +       $nf:APX_F:EVexMap4|NF:>
> +
> +<extend3:cpu:attr:reg, +
> +       $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
> +       $legacy:0:HLEPrefixLock:, +
> +       $nf:APX_F:EVexMap4|NF:>
> +
> -add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
> -add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -add, 0x0, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -add, 0x83/0, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> -add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +add<extend1>, 0x0, <extend1:cpu>, D|W|CheckOperandSize|Modrm|No_sSuf|<extend1:attr>, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend1:reg> }
> +add<extend2>, 0x83/0, <extend2:cpu>, Modrm|No_bSuf|No_sSuf|<extend2:attr>, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend2:reg> }
>  add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
> -add, 0x80/0, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
> -add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> -add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> +add<extend3>, 0x80/0, <extend3:cpu>, W|Modrm|No_sSuf|<extend3:attr>, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend3:reg> }
> 
> 
> Thanks,
> Lili.
  
Cui, Lili March 18, 2024, 1:43 p.m. UTC | #14
> On 18.03.2024 12:21, Cui, Lili wrote:
> >> On 13.03.2024 03:54, Cui, Lili wrote:
> >>>> On 12.03.2024 14:22, Cui, Lili wrote:
> >>>>>  // Arithmetic.
> >>>>>  add, 0x0, APX_F,
> >>>>>
> D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
> >>>>> Reg8|Reg16|Reg32|Reg64,
> >>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> >>>>> Reg8|Reg16|Reg32|Reg64 } -add, 0x0, 0,
> >>>>> D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
> >>>>> Reg8|Reg16|Reg32|Reg64,
> >>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>>>> -add, 0x0, APX_F,
> >>>> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
> >>>>> Reg8|Reg16|Reg32|Reg64,
> >>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> >>>>> +add<cpu1>, 0x0, 0,
> >>>> D|W|CheckOperandSize|Modrm|No_sSuf|<cpu1:attr>, {
> >>>>> +Reg8|Reg16|Reg32|Reg64,
> >>>> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex
> >>>>> +}
> >>>>
> >>>> Differentiating on other than the mnemonic is possible (see e.g.
> >>>> the mmx and sse templates, which append nothing to the mnemonics)
> >>>> but not wanted here. The goal of the suggested template is to have
> >>>> something that covers all 7 mnemonics in one go, including their legacy
> forms.
> >>>>
> >>>
> >>> The handling of <mmx/<sse are clever. The current templates are
> >>> indeed
> >> redundant. Do you mind I create a separate patch to clean up all APX
> >> templates instead of in this patch.
> >>
> >> Well - it explicitly ought to be a separate patch. Yet FTAOD - afaict
> >> such a new (set of) template(s) should not follow mmx/sse, but rather
> >> e.g. fma or pseudopfx (covering the entire mnemonic then).
> >>
> >
> > Hi Jan,
> >
> > Below are two examples of merging, does it meet expectations?
> >
> > --- a/opcodes/i386-gen.c
> > +++ b/opcodes/i386-gen.c
> >
> > @@ -1904,11 +1904,15 @@ process_i386_opcodes (FILE *table)
> >         case '<':
> >           parse_template (p, lineno);
> >           continue;
> > +       case '@':
> > +         p++;
> > +         break;
> >         default:
> >           if (!marker)
> >             continue;
> >           break;
> >         }
> >
> > rol and ror can be merged.
> >
> > -rol, 0xd0/0, APX_F,
> > W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64 }
> > -rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -rol, 0xd0/0, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { Imm1,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -rol, 0xc0/0, APX_F,
> > W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF,
> { Imm8|Imm8S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64 }
> > -rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -rol, 0xc0/0, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -rol, 0xd2/0, APX_F,
> > W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF,
> { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64 }
> > -rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -rol, 0xd2/0, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -rol, 0xd0/0, 0,
> > W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > -rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > -
> > -ror, 0xd0/1, APX_F,
> > W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64 }
> > -ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -ror, 0xd0/1, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { Imm1,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -ror, 0xc0/1, APX_F,
> > W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF,
> { Imm8|Imm8S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64 }
> > -ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -ror, 0xc0/1, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -ror, 0xd2/1, APX_F,
> > W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF,
> { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> Reg8|Reg16|Reg32|Reg64 }
> > -ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -ror, 0xd2/1, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -ror, 0xd0/1, 0,
> > W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > -ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +<extend10:cpu:attr:reg, +
> > +
> $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg3
> 2|Reg64, +
> > +       $legacy:0::, +
> > +       $nf:APX_F:EVexMap4|NF:>
> > +
> > +<extend11:cpu:attr:reg, +
> > +
> $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg3
> 2|Reg64, +
> > +       $legacy:i186::, +
> > +       $nf:APX_F:EVexMap4|NF:>
> > +
> > +<extend12:cpu:attr, +
> > +       $legacy:0:, +
> > +       $nf:APX_F:EVexMap4|NF>
> 
> I don't understand these three. I'd have expected all attributes to be
> specified ...
> 
> > +<mn:opcode, rol:0, ror:1>
> 
> ... here. Same then for add, where I'd have expected a similar template as the
> one above, e.g.
> 
> <alu:opcode, add:0, sub:...>
> 
> (but of course with more than just "opcode" specified).
> 
> > +@<mn><extend10>, 0xd0/0|<mn:opcode>, <extend10:cpu>,
> > +W|Modrm|No_sSuf|<extend10:attr>, { Imm1,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }
> > +
> > +@<mn><extend11>, 0xc0/0|<mn:opcode>, <extend11:cpu>,
> > +W|Modrm|No_sSuf|<extend11:attr>, { Imm8|Imm8S,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend11:reg> }
> > +
> > +@<mn><extend10>, 0xd2/0|<mn:opcode>, <extend10:cpu>,
> > +W|Modrm|No_sSuf|<extend10:attr>, { ShiftCount,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }
> > +
> > +@<mn><extend12>, 0xd0/0|<mn:opcode>, <extend12:cpu>,
> > +W|Modrm|No_sSuf|<extend12:attr>, {
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +
> > ...
> >
> > The same instruction as add structure was not found. There are always some
> subtle differences.
> 
> I expect the issue is with you using just a single "attr", trying to put all
> attributes in there. When split (see e.g. <sdh>), folding ought to be possible.
> 

Oh, get you. It can merge more templates.

> I'd also prefer if we could avoid the need for the leading @.
> 

Since they all start with '<', i386-gen.c needs to use '<' to distinguish them, we need to add something before the second '<' ,  so I added @ as a temporary workaround. We really need a more reasonable logo.

<mn:opcode, rol:0, ror:1>
<mn><extend10>, 0xd0/0|<mn:opcode>, <extend10:cpu>, W|Modrm|No_sSuf|<extend10:attr>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend10:reg> }

> Anyway - feel free to leave this to me. While not overly nice, I guess we can live
> with the growing volume due to what NF wants to add.
> 
> Jan

Ok, thanks.

Lili.
> 
> > +<extend1:cpu:attr:reg, +
> > +       $ndd:APX_F:C|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg32|Reg64, +
> > +       $legacy:0:HLEPrefixLock:, +
> > +       $nf:APX_F:EVexMap4|NF:>
> > +
> > +<extend2:cpu:attr:reg, +
> > +
> $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg16|Reg32|Reg
> 64, +
> > +       $legacy:0:HLEPrefixLock:, +
> > +       $nf:APX_F:EVexMap4|NF:>
> > +
> > +<extend3:cpu:attr:reg, +
> > +
> $ndd:APX_F:CheckOperandSize|DstVVVV|EVexMap4|NF:Reg8|Reg16|Reg3
> 2|Reg64, +
> > +       $legacy:0:HLEPrefixLock:, +
> > +       $nf:APX_F:EVexMap4|NF:>
> > +
> > -add, 0x0, APX_F,
> > D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Reg8|Reg16|Reg32|Reg64 } -add, 0x0, 0,
> > D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > -add, 0x0, APX_F,
> D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, {
> > Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > -add, 0x83/0, APX_F,
> > Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF,
> { Imm8S,
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -add,
> > 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S,
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex } -add, 0x83/0, APX_F,
> > Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S,
> > Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +add<extend1>, 0x0, <extend1:cpu>,
> > +D|W|CheckOperandSize|Modrm|No_sSuf|<extend1:attr>, {
> > +Reg8|Reg16|Reg32|Reg64,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > +<extend1:reg> } add<extend2>, 0x83/0, <extend2:cpu>,
> > +Modrm|No_bSuf|No_sSuf|<extend2:attr>, { Imm8S,
> > +Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend2:reg> }
> >  add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S,
> > Acc|Byte|Word|Dword|Qword } -add, 0x80/0, APX_F,
> > W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, {
> > Imm8|Imm16|Imm32|Imm32S,
> Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex,
> > Reg8|Reg16|Reg32|Reg64} -add, 0x80/0, 0,
> > W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -add, 0x80/0, APX_F,
> > W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S,
> > Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
> > +add<extend3>, 0x80/0, <extend3:cpu>,
> W|Modrm|No_sSuf|<extend3:attr>,
> > +{ Imm8|Imm16|Imm32|Imm32S,
> > +Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, <extend3:reg> }
> >
> >
> > Thanks,
> > Lili.
  
Cui, Lili March 19, 2024, 1:24 a.m. UTC | #15
> > >>>  // LZCNT instruction
> > >>>  lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf,
> {
> > >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > >>> +lzcnt, 0xf5, LZCNT|APX_F,
> > >>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> > >>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > >>
> > >> ... I think you mean LZCNT&APX_F here.
> > >>
> > >>>  // POPCNT instruction
> > >>>  popcnt, 0xf30fb8, POPCNT,
> > Modrm|CheckOperandSize|No_bSuf|No_sSuf,
> > >> {
> > >>> Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > >>> +popcnt, 0x88, POPCNT|APX_F,
> > >>> +Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, {
> > >>> +Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
> > >>
> > >> Whereas here it ought to be just APX_F if the doc is to be trusted.
> > >
> > > I think they should be LZCNT&APX_F and POPCNT&APX_F, why do you
> > > think
> > POPCNT is special? I suspect I've missed something.
> >
> > Unless you're looking at a newer version of the APX spec than me,
> > you'll observe the difference when looking at the respective insn
> > pages: For LZCNT both CPUID bits are mentioned, while for POPCNT only
> > APX_F is there.
> >
> You are right. I will double confirm it with doc.
> 

The CPUID of POPCNT should be POPCNT and APX_F, and the APX spec should update it in the next release. Thanks.

Lili.
  

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 5d2a3645a88..ddfe99e5430 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Support the NF feature in Intel APX.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fecb25a3fe2..6eed5d82436 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -242,6 +242,7 @@  enum i386_error
     unsupported_with_intel_mnemonic,
     unsupported_syntax,
     unsupported_EGPR_for_addressing,
+    unsupported_nf,
     unsupported,
     unsupported_on_arch,
     unsupported_64bit,
@@ -439,6 +440,9 @@  struct _i386_insn
     /* Prefer the REX2 prefix in encoding.  */
     bool rex2_encoding;
 
+    /* No CSPAZO flags update.  */
+    bool has_nf;
+
     /* Disable instruction size optimization.  */
     bool no_optimize;
 
@@ -3954,7 +3958,7 @@  is_any_vex_encoding (const insn_template *t)
 static INLINE bool
 is_apx_evex_encoding (void)
 {
-  return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4
+  return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 || i.has_nf
     || (i.vex.register_specifier
 	&& (i.vex.register_specifier->reg_flags & RegRex2));
 }
@@ -4261,6 +4265,10 @@  build_apx_evex_prefix (void)
      space.  */
   if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
     i.vex.bytes[3] |= 0x10;
+
+  /* Encode the NF bit.  */
+  if (i.has_nf)
+    i.vex.bytes[3] |= 0x04;
 }
 
 static void establish_rex (void)
@@ -6655,6 +6663,9 @@  md_assemble (char *line)
 	case unsupported_EGPR_for_addressing:
 	  err_msg = _("extended GPR cannot be used as base/index");
 	  break;
+	case unsupported_nf:
+	  err_msg = _("unsupported NF");
+	  break;
 	case unsupported:
 	  as_bad (_("unsupported instruction `%s'"),
 		  pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
@@ -7218,6 +7229,11 @@  parse_insn (const char *line, char *mnemonic, bool prefix_only)
 		  /* {rex2} */
 		  i.rex2_encoding = true;
 		  break;
+		case Prefix_NF:
+		  /* {nf} */
+		  i.has_nf = true;
+		  i.encoding = encoding_evex;
+		  break;
 		case Prefix_NoOptimize:
 		  /* {nooptimize} */
 		  i.no_optimize = true;
@@ -8475,8 +8491,7 @@  can_convert_NDD_to_legacy (const insn_template *t)
 {
   unsigned int match_dest_op = ~0;
 
-  if (!i.tm.opcode_modifier.nf
-      && i.reg_operands >= 2)
+  if (!i.has_nf && i.reg_operands >= 2)
     {
       unsigned int dest = i.operands - 1;
       unsigned int src1 = i.operands - 2;
@@ -8557,6 +8572,11 @@  match_template (char mnem_suffix)
 	   : t->opcode_modifier.dialect == INTEL_SYNTAX)
 	continue;
 
+      /* Check NF support.  */
+      specific_error = progress (unsupported_nf);
+      if (i.has_nf && !t->opcode_modifier.nf)
+	continue;
+
       /* Check Intel64/AMD64 ISA.   */
       switch (isa64)
 	{
@@ -8900,7 +8920,8 @@  match_template (char mnem_suffix)
 		  found_reverse_match = Opcode_VexW;
 		  goto check_operands_345;
 		}
-	      else if (is_cpu (t, CpuAPX_F) && i.operands == 3)
+	      else if (t->opcode_space == SPACE_EVEXMAP4
+		       && t->opcode_modifier.w)
 		{
 		  found_reverse_match = Opcode_D;
 		  goto check_operands_345;
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
index 57bdf64c858..43ddee34e93 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d
@@ -20,14 +20,12 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:[ 	]+62 fc 7d[ 	]+\(bad\).*
 [ 	]*[a-f0-9]+:[ 	]+28 60 c7[ 	]+.*
 [ 	]*[a-f0-9]+:[ 	]+62 fc 7d[ 	]+\(bad\).*
-[ 	]*[a-f0-9]+:[ 	]+8f[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+60[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+c7[ 	]+\(bad\)
+[ 	]*[a-f0-9]+:[ 	]+8b 60 c7[ 	]+.*
 [ 	]*[a-f0-9]+:[ 	]+62 f2 fc 09 f5[ 	]+\(bad\).*
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
 [ 	]*[a-f0-9]+:[ 	]+62 f2 fc 28 f5[ 	]+\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
-[ 	]*[a-f0-9]+:[ 	]+62 f2 fc 8f f5[ 	]+\(bad\).*
+[ 	]*[a-f0-9]+:[ 	]+62 f2 fc 8b f5[ 	]+\(bad\).*
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
 [ 	]*[a-f0-9]+:[ 	]+62 f2 fc 18 f5[ 	]+\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+0c 18[ 	]+or.*
@@ -38,5 +36,6 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:[ 	]+08 8f c0 ff ff ff[ 	]+or.*
 [ 	]*[a-f0-9]+:[ 	]+62 74 7c 18 8f c0[ 	]+pop2   %rax,\(bad\)
 [ 	]*[a-f0-9]+:[ 	]+62 d4 3c 18 8f[ 	]+\(bad\)
-[ 	]*[a-f0-9]+:[ 	]+c0[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+c0 ff ff[ 	]+.*
+[ 	]*[a-f0-9]+:[ 	]+62 fc 7d 0c 60 c7[ 	]+movbe\{bad\} %r23w,%ax
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
index 61ed8824428..68b0b4b5ad4 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s
@@ -23,7 +23,7 @@  _start:
 	.insn EVEX.L1.66.M12.W0 0x60, %di, %ax
 
 	#EVEX_MAP4 movbe %r18w,%ax set EVEX.z == 0b1.
-	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k7}{z}
+	.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k3}{z}
 
 	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.aaa[1:0] (P[17:16])
 	#== 0b01
@@ -33,17 +33,25 @@  _start:
 	.insn EVEX.L1.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx
 
 	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[23](EVEX.z) == 0b1
-	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k7}{z}
+	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx), %rcx {%k3}{z}
 
 	#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[20](EVEX.b) == 0b1
 	.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx){1to8}, %rcx
 
 	#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
 	.byte 0x62, 0xf4, 0xe4, 0x08, 0xff, 0x04, 0x08
+
 	# pop2 %rax, %r8 set EVEX.ND=0.
 	.byte 0x62, 0xf4, 0x3c, 0x08, 0x8f, 0xc0
 	.byte 0xff, 0xff, 0xff
+
 	# pop2 %rax, %r8 set EVEX.vvvv = 1111.
 	.insn EVEX.L0.M4.W0 0x8f,  %rax, {rn-sae},%r8
+
 	# pop2 %r8, %r8.
 	.byte 0x62, 0xd4, 0x3c, 0x18, 0x8f, 0xc0
+	.byte 0xff, 0xff
+
+	#EVEX_MAP4 movbe %r18w,%ax set EVEX.nf = 1.
+        .insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k4}
+
diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.l b/gas/testsuite/gas/i386/x86-64-apx-inval.l
index 6c1a346fcbf..262a399bfc1 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-apx-inval.l
@@ -1,3 +1,10 @@ 
 .*: Assembler messages:
 .*:3: Error: instruction length of 16 bytes exceeds the limit of 15
 .*:4: Error: instruction length of 16 bytes exceeds the limit of 15
+.*:5: Error: unsupported NF for `adc'
+.*:6: Error: unsupported NF for `not'
+.*:7: Error: unsupported NF for `rcl'
+.*:8: Error: unsupported NF for `rcr'
+.*:9: Error: unsupported NF for `sbb'
+.*:10: Error: unsupported NF for `pop2'
+.*:11: Error: unsupported NF for `push2'
diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.s b/gas/testsuite/gas/i386/x86-64-apx-inval.s
index bb57817bc8a..3d9de743231 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-inval.s
@@ -2,3 +2,10 @@ 
 	.text
 	addq $0xe0, %fs:0, %rdx
 	xorq $0xe0, foo(%eax,%edx), %rdx
+	{nf} adc $1, (%rax)
+	{nf} not %r15
+	{nf} rcl $0x7b,%r15
+	{nf} rcr $0x7b,%r15
+	{nf} sbb $0x7b,%r15
+	{nf} pop2 %rax, %rbx
+	{nf} push2 %rbx, %rax
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
new file mode 100644
index 00000000000..ed8b53ae5a9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
@@ -0,0 +1,1315 @@ 
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 APX_F insns (Intel disassembly)
+#source: x86-64-apx-nf.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn r11,r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr r11,r31,r9
+\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi r11,r31,r9
+\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} dec BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} dec bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} dec WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} dec dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} dec DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} dec ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} dec QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} dec r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} div BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} div WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} div DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} div QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idiv BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul dx
+\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul r9w,ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul ecx
+\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul r9
+\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul r31,r9
+\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul r11,r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imul BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imul WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imul DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imul QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c 6b c2 7b\s+\{nf\} imul ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 6b d1 7b\s+\{nf\} imul edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 6b f9 7b\s+\{nf\} imul r15,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 6b 94 80 23 01 00 00 7b\s+\{nf\} imul dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 6b 8c 80 23 01 00 00 7b\s+\{nf\} imul ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 6b 8c 80 23 01 00 00 7b\s+\{nf\} imul r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 6b c2 90\s+\{nf\} imul ax,dx,0xff90
+\s*[a-f0-9]+:\s*62 f4 7c 0c 69 d1 90 ff 00 00\s+\{nf\} imul edx,ecx,0xff90
+\s*[a-f0-9]+:\s*62 54 fc 0c 69 f9 90 ff 00 00\s+\{nf\} imul r15,r9,0xff90
+\s*[a-f0-9]+:\s*62 d4 7d 0c 6b 94 80 23 01 00 00 90\s+\{nf\} imul dx,WORD PTR \[r8\+rax\*4\+0x123\],0xff90
+\s*[a-f0-9]+:\s*62 d4 7c 0c 69 8c 80 23 01 00 00 90 ff 00 00\s+\{nf\} imul ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0xff90
+\s*[a-f0-9]+:\s*62 54 fc 0c 69 8c 80 23 01 00 00 90 ff 00 00\s+\{nf\} imul r9,QWORD PTR \[r8\+rax\*4\+0x123\],0xff90
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} inc BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} inc bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} inc WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} inc dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} inc DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} inc ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} inc QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} inc r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mul BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mul WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mul DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mul QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg r9
+\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} neg BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} neg bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} neg WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} neg dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} neg DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} neg ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} neg QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} neg r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld r9w,ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld r10d,edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld r11,r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld r9w,ax,dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld edx,ecx,cl
+\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld r10d,edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld r31,r9,cl
+\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld r11,r31,r9,cl
+\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd r9w,ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd r10d,edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd r11,r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd r9w,ax,dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd edx,ecx,cl
+\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd r10d,edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd r31,r9,cl
+\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd r11,r31,r9,cl
+\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn r11,r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr r11,r31,r9
+\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi r11,r31,r9
+\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} dec BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} dec bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} dec WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} dec dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} dec DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} dec ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} dec QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} dec r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} div BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} div WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} div DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} div QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idiv BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul dx
+\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul r9w,ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul ecx
+\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul r9
+\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul r31,r9
+\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul r11,r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imul BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imul WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imul DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imul QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} inc BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} inc bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} inc WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} inc dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} inc DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} inc ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} inc QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} inc r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mul BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mul WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mul DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mul QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg r9
+\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} neg BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} neg bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} neg WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} neg dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} neg DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} neg ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} neg QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} neg r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld r9w,ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld r10d,edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld r11,r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld r9w,ax,dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld edx,ecx,cl
+\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld r10d,edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld r31,r9,cl
+\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld r11,r31,r9,cl
+\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd r9w,ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd r10d,edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd r11,r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd r9w,ax,dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd edx,ecx,cl
+\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd r10d,edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd r31,r9,cl
+\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd r11,r31,r9,cl
+\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.d b/gas/testsuite/gas/i386/x86-64-apx-nf.d
new file mode 100644
index 00000000000..fbd057fd8e9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf.d
@@ -0,0 +1,1315 @@ 
+#as:
+#objdump: -dw
+#name: x86_64 APX_F insns
+#source: x86-64-apx-nf.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} addb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} andb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} decb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} decw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} decl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} decq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} divb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} divw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} divl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} divq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idivb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idivw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idivl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idivq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul %dx
+\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul %ecx
+\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul %r9
+\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul %r9,%r31
+\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imulb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imulw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imull 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imulq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c 6b c2 7b\s+\{nf\} imul \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 6b d1 7b\s+\{nf\} imul \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 6b f9 7b\s+\{nf\} imul \$0x7b,%r9,%r15
+\s*[a-f0-9]+:\s*62 d4 7d 0c 6b 94 80 23 01 00 00 7b\s+\{nf\} imul \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 6b 8c 80 23 01 00 00 7b\s+\{nf\} imul \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c 6b 8c 80 23 01 00 00 7b\s+\{nf\} imul \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 6b c2 90\s+\{nf\} imul \$0xff90,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 69 d1 90 ff 00 00\s+\{nf\} imul \$0xff90,%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 69 f9 90 ff 00 00\s+\{nf\} imul \$0xff90,%r9,%r15
+\s*[a-f0-9]+:\s*62 d4 7d 0c 6b 94 80 23 01 00 00 90\s+\{nf\} imul \$0xff90,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 69 8c 80 23 01 00 00 90 ff 00 00\s+\{nf\} imul \$0xff90,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c 69 8c 80 23 01 00 00 90 ff 00 00\s+\{nf\} imul \$0xff90,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} incb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} incw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} incl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} incq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mulb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mulw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mull 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mulq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} negb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} negw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} negl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} negq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} orb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rolb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rolw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} roll\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rolq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rolb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} roll\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rolb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rolw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} roll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rolq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} rorb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} rorw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} rorl\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} rorq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} rorb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} rorb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} rorw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} rorl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} rorq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sarb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sarw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sarl\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sarq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sarb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sarb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sarw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sarl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sarq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shlb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shlw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shll\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shlq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shlb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shlw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shll\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shlq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld\s+\$0x7b,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld\s+\$0x7b,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld\s+\$0x7b,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld %cl,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld %cl,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld %cl,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shrb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shrw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shrl\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shrq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shrb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shrb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shrw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shrl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shrq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd\s+\$0x7b,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd\s+\$0x7b,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd %cl,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd %cl,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd %cl,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} subb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xorb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} addb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} andb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} decb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} decw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} decl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} decq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} dec 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} divb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} divw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} divl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} divq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idivb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idivw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idivl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idivq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul %dx
+\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul %ecx
+\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul %r9
+\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul %r9,%r31
+\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imulb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imulw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imull 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imulq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} incb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} incw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} incl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} incq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} inc 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mulb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mulw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mull 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mulq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} negb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} negw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} negl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} negq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} neg 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} orb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rolb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rolw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} roll\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rolq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rol\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rolb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} roll\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rolb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rolw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} roll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rolq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rol %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} rorb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} rorw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} rorl\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} rorq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} ror\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} rorb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} rorb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} rorw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} rorl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} rorq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} ror %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sarb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sarw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sarl\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sarq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sar\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sarb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sarb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sarw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sarl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sarq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sar %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shlb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shlw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shll\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shlq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld\s+\$0x7b,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld\s+\$0x7b,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld\s+\$0x7b,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld\s+\$0x7b,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld %cl,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld %cl,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld %cl,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr\s+\$1,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr\s+\$1,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr\s+\$1,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr\s+\$1,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr\s+\$1,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr\s+\$1,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr\s+\$1,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr\s+\$1,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shrb\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shrw\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shrl\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shrq\s+\$1,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shr\s+\$1,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shrb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shrb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shrw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shrl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shrq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shr %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd\s+\$0x7b,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd\s+\$0x7b,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd\s+\$0x7b,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd %cl,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd %cl,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd %cl,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} subb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor\s+\$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor\s+\$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor\s+\$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor\s+\$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor\s+\$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xorb\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorw\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorl\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorq\s+\$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor\s+\$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9,%r31
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.s b/gas/testsuite/gas/i386/x86-64-apx-nf.s
new file mode 100644
index 00000000000..0a44fab762a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s
@@ -0,0 +1,1310 @@ 
+# Check 64bit APX_F instructions
+
+        .text
+_start:
+	{nf}	add	$123, %bl
+	{nf}	add	$123, %bl, %dl
+	{nf}	add	$123, %dx
+	{nf}	add	$123, %dx, %ax
+	{nf}	add	$123, %ecx
+	{nf}	add	$123, %ecx, %edx
+	{nf}	add	$123, %r9
+	{nf}	add	$123, %r9, %r31
+	{nf}	addb	$123, 291(%r8, %rax, 4)
+	{nf}	add	$123, 291(%r8, %rax, 4), %bl
+	{nf}	addw	$123, 291(%r8, %rax, 4)
+	{nf}	add	$123, 291(%r8, %rax, 4), %dx
+	{nf}	addl	$123, 291(%r8, %rax, 4)
+	{nf}	add	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	addq	$123, 291(%r8, %rax, 4)
+	{nf}	add	$123, 291(%r8, %rax, 4), %r9
+	{nf}	add	%bl, %dl
+	{nf}	add	%bl, %dl, %r8b
+	{nf}	add	%bl, 291(%r8, %rax, 4)
+	{nf}	add	%bl, 291(%r8, %rax, 4), %dl
+	{nf}	add	%dx, %ax
+	{nf}	add	%dx, %ax, %r9w
+	{nf}	add	%dx, 291(%r8, %rax, 4)
+	{nf}	add	%dx, 291(%r8, %rax, 4), %ax
+	{nf}	add	%ecx, %edx
+	{nf}	add	%ecx, %edx, %r10d
+	{nf}	add	%ecx, 291(%r8, %rax, 4)
+	{nf}	add	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	add	%r9, %r31
+	{nf}	add	%r9, %r31, %r11
+	{nf}	add	%r9, 291(%r8, %rax, 4)
+	{nf}	add	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	add	291(%r8, %rax, 4), %bl
+	{nf}	add	291(%r8, %rax, 4), %bl, %dl
+	{nf}	add	291(%r8, %rax, 4), %dx
+	{nf}	add	291(%r8, %rax, 4), %dx, %ax
+	{nf}	add	291(%r8, %rax, 4), %ecx
+	{nf}	add	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	add	291(%r8, %rax, 4), %r9
+	{nf}	add	291(%r8, %rax, 4), %r9, %r31
+	{nf}	and	$123, %bl
+	{nf}	and	$123, %bl, %dl
+	{nf}	and	$123, %dx
+	{nf}	and	$123, %dx, %ax
+	{nf}	and	$123, %ecx
+	{nf}	and	$123, %ecx, %edx
+	{nf}	and	$123, %r9
+	{nf}	and	$123, %r9, %r31
+	{nf}	andb	$123, 291(%r8, %rax, 4)
+	{nf}	and	$123, 291(%r8, %rax, 4), %bl
+	{nf}	andw	$123, 291(%r8, %rax, 4)
+	{nf}	and	$123, 291(%r8, %rax, 4), %dx
+	{nf}	andl	$123, 291(%r8, %rax, 4)
+	{nf}	and	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	andq	$123, 291(%r8, %rax, 4)
+	{nf}	and	$123, 291(%r8, %rax, 4), %r9
+	{nf}	and	%bl, %dl
+	{nf}	and	%bl, %dl, %r8b
+	{nf}	and	%bl, 291(%r8, %rax, 4)
+	{nf}	and	%bl, 291(%r8, %rax, 4), %dl
+	{nf}	and	%dx, %ax
+	{nf}	and	%dx, %ax, %r9w
+	{nf}	and	%dx, 291(%r8, %rax, 4)
+	{nf}	and	%dx, 291(%r8, %rax, 4), %ax
+	{nf}	and	%ecx, %edx
+	{nf}	and	%ecx, %edx, %r10d
+	{nf}	and	%ecx, 291(%r8, %rax, 4)
+	{nf}	and	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	and	%r9, %r31
+	{nf}	and	%r9, %r31, %r11
+	{nf}	and	%r9, 291(%r8, %rax, 4)
+	{nf}	and	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	and	291(%r8, %rax, 4), %bl
+	{nf}	and	291(%r8, %rax, 4), %bl, %dl
+	{nf}	and	291(%r8, %rax, 4), %dx
+	{nf}	and	291(%r8, %rax, 4), %dx, %ax
+	{nf}	and	291(%r8, %rax, 4), %ecx
+	{nf}	and	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	and	291(%r8, %rax, 4), %r9
+	{nf}	and	291(%r8, %rax, 4), %r9, %r31
+	{nf}	andn	%ecx, %edx, %r10d
+	{nf}	andn	%r9, %r31, %r11
+	{nf}	andn	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	andn	291(%r8, %rax, 4), %r9, %r31
+	{nf}	bextr	%ecx, %edx, %r10d
+	{nf}	bextr	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	bextr	%r9, %r31, %r11
+	{nf}	bextr	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	blsi	%ecx, %edx
+	{nf}	blsi	%r9, %r31
+	{nf}	blsi	291(%r8, %rax, 4), %ecx
+	{nf}	blsi	291(%r8, %rax, 4), %r9
+	{nf}	blsmsk	%ecx, %edx
+	{nf}	blsmsk	%r9, %r31
+	{nf}	blsmsk	291(%r8, %rax, 4), %ecx
+	{nf}	blsmsk	291(%r8, %rax, 4), %r9
+	{nf}	blsr	%ecx, %edx
+	{nf}	blsr	%r9, %r31
+	{nf}	blsr	291(%r8, %rax, 4), %ecx
+	{nf}	blsr	291(%r8, %rax, 4), %r9
+	{nf}	bzhi	%ecx, %edx, %r10d
+	{nf}	bzhi	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	bzhi	%r9, %r31, %r11
+	{nf}	bzhi	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	dec	%bl
+	{nf}	dec	%bl, %dl
+	{nf}	dec	%dx
+	{nf}	dec	%dx, %ax
+	{nf}	dec	%ecx
+	{nf}	dec	%ecx, %edx
+	{nf}	dec	%r9
+	{nf}	dec	%r9, %r31
+	{nf}	decb	291(%r8, %rax, 4)
+	{nf}	dec	291(%r8, %rax, 4), %bl
+	{nf}	decw	291(%r8, %rax, 4)
+	{nf}	dec	291(%r8, %rax, 4), %dx
+	{nf}	decl	291(%r8, %rax, 4)
+	{nf}	dec	291(%r8, %rax, 4), %ecx
+	{nf}	decq	291(%r8, %rax, 4)
+	{nf}	dec	291(%r8, %rax, 4), %r9
+	{nf}	div	%bl
+	{nf}	div	%dx
+	{nf}	div	%ecx
+	{nf}	div	%r9
+	{nf}	divb	291(%r8, %rax, 4)
+	{nf}	divw	291(%r8, %rax, 4)
+	{nf}	divl	291(%r8, %rax, 4)
+	{nf}	divq	291(%r8, %rax, 4)
+	{nf}	idiv	%bl
+	{nf}	idiv	%dx
+	{nf}	idiv	%ecx
+	{nf}	idiv	%r9
+	{nf}	idivb	291(%r8, %rax, 4)
+	{nf}	idivw	291(%r8, %rax, 4)
+	{nf}	idivl	291(%r8, %rax, 4)
+	{nf}	idivq	291(%r8, %rax, 4)
+	{nf}	imul	%bl
+	{nf}	imul	%dx
+	{nf}	imul	%dx, %ax
+	{nf}	imul	%dx, %ax, %r9w
+	{nf}	imul	%ecx
+	{nf}	imul	%ecx, %edx
+	{nf}	imul	%ecx, %edx, %r10d
+	{nf}	imul	%r9
+	{nf}	imul	%r9, %r31
+	{nf}	imul	%r9, %r31, %r11
+	{nf}	imulb	291(%r8, %rax, 4)
+	{nf}	imulw	291(%r8, %rax, 4)
+	{nf}	imul	291(%r8, %rax, 4), %dx
+	{nf}	imul	291(%r8, %rax, 4), %dx, %ax
+	{nf}	imull	291(%r8, %rax, 4)
+	{nf}	imul	291(%r8, %rax, 4), %ecx
+	{nf}	imul	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	imulq	291(%r8, %rax, 4)
+	{nf}	imul	291(%r8, %rax, 4), %r9
+	{nf}	imul	291(%r8, %rax, 4), %r9, %r31
+	{nf}	imul	$0x7b, %dx, %ax
+	{nf}	imul	$0x7b, %ecx, %edx
+	{nf}	imul	$0x7b, %r9, %r15
+	{nf}	imul	$0x7b, 291(%r8, %rax, 4), %dx
+	{nf}	imul	$0x7b, 291(%r8, %rax, 4), %ecx
+	{nf}	imul	$0x7b, 291(%r8, %rax, 4), %r9
+	{nf}	imul	$0xff90, %dx, %ax
+	{nf}	imul	$0xff90, %ecx, %edx
+	{nf}	imul	$0xff90, %r9, %r15
+	{nf}	imul	$0xff90, 291(%r8, %rax, 4), %dx
+	{nf}	imul	$0xff90, 291(%r8, %rax, 4), %ecx
+	{nf}	imul	$0xff90, 291(%r8, %rax, 4), %r9
+	{nf}	inc	%bl
+	{nf}	inc	%bl, %dl
+	{nf}	inc	%dx
+	{nf}	inc	%dx, %ax
+	{nf}	inc	%ecx
+	{nf}	inc	%ecx, %edx
+	{nf}	inc	%r9
+	{nf}	inc	%r9, %r31
+	{nf}	incb	291(%r8, %rax, 4)
+	{nf}	inc	291(%r8, %rax, 4), %bl
+	{nf}	incw	291(%r8, %rax, 4)
+	{nf}	inc	291(%r8, %rax, 4), %dx
+	{nf}	incl	291(%r8, %rax, 4)
+	{nf}	inc	291(%r8, %rax, 4), %ecx
+	{nf}	incq	291(%r8, %rax, 4)
+	{nf}	inc	291(%r8, %rax, 4), %r9
+	{nf}	lzcnt	%dx, %ax
+	{nf}	lzcnt	%ecx, %edx
+	{nf}	lzcnt	%r9, %r31
+	{nf}	lzcnt	291(%r8, %rax, 4), %dx
+	{nf}	lzcnt	291(%r8, %rax, 4), %ecx
+	{nf}	lzcnt	291(%r8, %rax, 4), %r9
+	{nf}	mul	%bl
+	{nf}	mul	%dx
+	{nf}	mul	%ecx
+	{nf}	mul	%r9
+	{nf}	mulb	291(%r8, %rax, 4)
+	{nf}	mulw	291(%r8, %rax, 4)
+	{nf}	mull	291(%r8, %rax, 4)
+	{nf}	mulq	291(%r8, %rax, 4)
+	{nf}	neg	%bl
+	{nf}	neg	%bl, %dl
+	{nf}	neg	%dx
+	{nf}	neg	%dx, %ax
+	{nf}	neg	%ecx
+	{nf}	neg	%ecx, %edx
+	{nf}	neg	%r9
+	{nf}	neg	%r9, %r31
+	{nf}	negb	291(%r8, %rax, 4)
+	{nf}	neg	291(%r8, %rax, 4), %bl
+	{nf}	negw	291(%r8, %rax, 4)
+	{nf}	neg	291(%r8, %rax, 4), %dx
+	{nf}	negl	291(%r8, %rax, 4)
+	{nf}	neg	291(%r8, %rax, 4), %ecx
+	{nf}	negq	291(%r8, %rax, 4)
+	{nf}	neg	291(%r8, %rax, 4), %r9
+	{nf}	or	$123, %bl
+	{nf}	or	$123, %bl, %dl
+	{nf}	or	$123, %dx
+	{nf}	or	$123, %dx, %ax
+	{nf}	or	$123, %ecx
+	{nf}	or	$123, %ecx, %edx
+	{nf}	or	$123, %r9
+	{nf}	or	$123, %r9, %r31
+	{nf}	orb	$123, 291(%r8, %rax, 4)
+	{nf}	or	$123, 291(%r8, %rax, 4), %bl
+	{nf}	orw	$123, 291(%r8, %rax, 4)
+	{nf}	or	$123, 291(%r8, %rax, 4), %dx
+	{nf}	orl	$123, 291(%r8, %rax, 4)
+	{nf}	or	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	orq	$123, 291(%r8, %rax, 4)
+	{nf}	or	$123, 291(%r8, %rax, 4), %r9
+	{nf}	or	%bl, %dl
+	{nf}	or	%bl, %dl, %r8b
+	{nf}	or	%bl, 291(%r8, %rax, 4)
+	{nf}	or	%bl, 291(%r8, %rax, 4), %dl
+	{nf}	or	%dx, %ax
+	{nf}	or	%dx, %ax, %r9w
+	{nf}	or	%dx, 291(%r8, %rax, 4)
+	{nf}	or	%dx, 291(%r8, %rax, 4), %ax
+	{nf}	or	%ecx, %edx
+	{nf}	or	%ecx, %edx, %r10d
+	{nf}	or	%ecx, 291(%r8, %rax, 4)
+	{nf}	or	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	or	%r9, %r31
+	{nf}	or	%r9, %r31, %r11
+	{nf}	or	%r9, 291(%r8, %rax, 4)
+	{nf}	or	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	or	291(%r8, %rax, 4), %bl
+	{nf}	or	291(%r8, %rax, 4), %bl, %dl
+	{nf}	or	291(%r8, %rax, 4), %dx
+	{nf}	or	291(%r8, %rax, 4), %dx, %ax
+	{nf}	or	291(%r8, %rax, 4), %ecx
+	{nf}	or	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	or	291(%r8, %rax, 4), %r9
+	{nf}	or	291(%r8, %rax, 4), %r9, %r31
+	{nf}	popcnt	%dx, %ax
+	{nf}	popcnt	%ecx, %edx
+	{nf}	popcnt	%r9, %r31
+	{nf}	popcnt	291(%r8, %rax, 4), %dx
+	{nf}	popcnt	291(%r8, %rax, 4), %ecx
+	{nf}	popcnt	291(%r8, %rax, 4), %r9
+	{nf}	rol	$1, %bl
+	{nf}	rol	$1, %bl, %dl
+	{nf}	rol	$1, %dx
+	{nf}	rol	$1, %dx, %ax
+	{nf}	rol	$1, %ecx
+	{nf}	rol	$1, %ecx, %edx
+	{nf}	rol	$1, %r9
+	{nf}	rol	$1, %r9, %r31
+	{nf}	rolb	$1, 291(%r8, %rax, 4)
+	{nf}	rol	$1, 291(%r8, %rax, 4), %bl
+	{nf}	rolw	$1, 291(%r8, %rax, 4)
+	{nf}	rol	$1, 291(%r8, %rax, 4), %dx
+	{nf}	roll	$1, 291(%r8, %rax, 4)
+	{nf}	rol	$1, 291(%r8, %rax, 4), %ecx
+	{nf}	rolq	$1, 291(%r8, %rax, 4)
+	{nf}	rol	$1, 291(%r8, %rax, 4), %r9
+	{nf}	rol	$123, %bl
+	{nf}	rol	$123, %bl, %dl
+	{nf}	rol	$123, %dx
+	{nf}	rol	$123, %dx, %ax
+	{nf}	rol	$123, %ecx
+	{nf}	rol	$123, %ecx, %edx
+	{nf}	rol	$123, %r9
+	{nf}	rol	$123, %r9, %r31
+	{nf}	rolb	$123, 291(%r8, %rax, 4)
+	{nf}	rol	$123, 291(%r8, %rax, 4), %bl
+	{nf}	rolw	$123, 291(%r8, %rax, 4)
+	{nf}	rol	$123, 291(%r8, %rax, 4), %dx
+	{nf}	roll	$123, 291(%r8, %rax, 4)
+	{nf}	rol	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	rolq	$123, 291(%r8, %rax, 4)
+	{nf}	rol	$123, 291(%r8, %rax, 4), %r9
+	{nf}	rol	%cl, %bl
+	{nf}	rol	%cl, %bl, %dl
+	{nf}	rol	%cl, %dx
+	{nf}	rol	%cl, %dx, %ax
+	{nf}	rol	%cl, %ecx
+	{nf}	rol	%cl, %ecx, %edx
+	{nf}	rol	%cl, %r9
+	{nf}	rol	%cl, %r9, %r31
+	{nf}	rolb	%cl, 291(%r8, %rax, 4)
+	{nf}	rol	%cl, 291(%r8, %rax, 4), %bl
+	{nf}	rolw	%cl, 291(%r8, %rax, 4)
+	{nf}	rol	%cl, 291(%r8, %rax, 4), %dx
+	{nf}	roll	%cl, 291(%r8, %rax, 4)
+	{nf}	rol	%cl, 291(%r8, %rax, 4), %ecx
+	{nf}	rolq	%cl, 291(%r8, %rax, 4)
+	{nf}	rol	%cl, 291(%r8, %rax, 4), %r9
+	{nf}	ror	$1, %bl
+	{nf}	ror	$1, %bl, %dl
+	{nf}	ror	$1, %dx
+	{nf}	ror	$1, %dx, %ax
+	{nf}	ror	$1, %ecx
+	{nf}	ror	$1, %ecx, %edx
+	{nf}	ror	$1, %r9
+	{nf}	ror	$1, %r9, %r31
+	{nf}	rorb	$1, 291(%r8, %rax, 4)
+	{nf}	ror	$1, 291(%r8, %rax, 4), %bl
+	{nf}	rorw	$1, 291(%r8, %rax, 4)
+	{nf}	ror	$1, 291(%r8, %rax, 4), %dx
+	{nf}	rorl	$1, 291(%r8, %rax, 4)
+	{nf}	ror	$1, 291(%r8, %rax, 4), %ecx
+	{nf}	rorq	$1, 291(%r8, %rax, 4)
+	{nf}	ror	$1, 291(%r8, %rax, 4), %r9
+	{nf}	ror	$123, %bl
+	{nf}	ror	$123, %bl, %dl
+	{nf}	ror	$123, %dx
+	{nf}	ror	$123, %dx, %ax
+	{nf}	ror	$123, %ecx
+	{nf}	ror	$123, %ecx, %edx
+	{nf}	ror	$123, %r9
+	{nf}	ror	$123, %r9, %r31
+	{nf}	rorb	$123, 291(%r8, %rax, 4)
+	{nf}	ror	$123, 291(%r8, %rax, 4), %bl
+	{nf}	rorw	$123, 291(%r8, %rax, 4)
+	{nf}	ror	$123, 291(%r8, %rax, 4), %dx
+	{nf}	rorl	$123, 291(%r8, %rax, 4)
+	{nf}	ror	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	rorq	$123, 291(%r8, %rax, 4)
+	{nf}	ror	$123, 291(%r8, %rax, 4), %r9
+	{nf}	ror	%cl, %bl
+	{nf}	ror	%cl, %bl, %dl
+	{nf}	ror	%cl, %dx
+	{nf}	ror	%cl, %dx, %ax
+	{nf}	ror	%cl, %ecx
+	{nf}	ror	%cl, %ecx, %edx
+	{nf}	ror	%cl, %r9
+	{nf}	ror	%cl, %r9, %r31
+	{nf}	rorb	%cl, 291(%r8, %rax, 4)
+	{nf}	ror	%cl, 291(%r8, %rax, 4), %bl
+	{nf}	rorw	%cl, 291(%r8, %rax, 4)
+	{nf}	ror	%cl, 291(%r8, %rax, 4), %dx
+	{nf}	rorl	%cl, 291(%r8, %rax, 4)
+	{nf}	ror	%cl, 291(%r8, %rax, 4), %ecx
+	{nf}	rorq	%cl, 291(%r8, %rax, 4)
+	{nf}	ror	%cl, 291(%r8, %rax, 4), %r9
+	{nf}	sar	$1, %bl
+	{nf}	sar	$1, %bl, %dl
+	{nf}	sar	$1, %dx
+	{nf}	sar	$1, %dx, %ax
+	{nf}	sar	$1, %ecx
+	{nf}	sar	$1, %ecx, %edx
+	{nf}	sar	$1, %r9
+	{nf}	sar	$1, %r9, %r31
+	{nf}	sarb	$1, 291(%r8, %rax, 4)
+	{nf}	sar	$1, 291(%r8, %rax, 4), %bl
+	{nf}	sarw	$1, 291(%r8, %rax, 4)
+	{nf}	sar	$1, 291(%r8, %rax, 4), %dx
+	{nf}	sarl	$1, 291(%r8, %rax, 4)
+	{nf}	sar	$1, 291(%r8, %rax, 4), %ecx
+	{nf}	sarq	$1, 291(%r8, %rax, 4)
+	{nf}	sar	$1, 291(%r8, %rax, 4), %r9
+	{nf}	sar	$123, %bl
+	{nf}	sar	$123, %bl, %dl
+	{nf}	sar	$123, %dx
+	{nf}	sar	$123, %dx, %ax
+	{nf}	sar	$123, %ecx
+	{nf}	sar	$123, %ecx, %edx
+	{nf}	sar	$123, %r9
+	{nf}	sar	$123, %r9, %r31
+	{nf}	sarb	$123, 291(%r8, %rax, 4)
+	{nf}	sar	$123, 291(%r8, %rax, 4), %bl
+	{nf}	sarw	$123, 291(%r8, %rax, 4)
+	{nf}	sar	$123, 291(%r8, %rax, 4), %dx
+	{nf}	sarl	$123, 291(%r8, %rax, 4)
+	{nf}	sar	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	sarq	$123, 291(%r8, %rax, 4)
+	{nf}	sar	$123, 291(%r8, %rax, 4), %r9
+	{nf}	sar	%cl, %bl
+	{nf}	sar	%cl, %bl, %dl
+	{nf}	sar	%cl, %dx
+	{nf}	sar	%cl, %dx, %ax
+	{nf}	sar	%cl, %ecx
+	{nf}	sar	%cl, %ecx, %edx
+	{nf}	sar	%cl, %r9
+	{nf}	sar	%cl, %r9, %r31
+	{nf}	sarb	%cl, 291(%r8, %rax, 4)
+	{nf}	sar	%cl, 291(%r8, %rax, 4), %bl
+	{nf}	sarw	%cl, 291(%r8, %rax, 4)
+	{nf}	sar	%cl, 291(%r8, %rax, 4), %dx
+	{nf}	sarl	%cl, 291(%r8, %rax, 4)
+	{nf}	sar	%cl, 291(%r8, %rax, 4), %ecx
+	{nf}	sarq	%cl, 291(%r8, %rax, 4)
+	{nf}	sar	%cl, 291(%r8, %rax, 4), %r9
+	{nf}	sal	$1, %bl
+	{nf}	sal	$1, %bl, %dl
+	{nf}	sal	$1, %dx
+	{nf}	sal	$1, %dx, %ax
+	{nf}	sal	$1, %ecx
+	{nf}	sal	$1, %ecx, %edx
+	{nf}	sal	$1, %r9
+	{nf}	sal	$1, %r9, %r31
+	{nf}	salb	$1, 291(%r8, %rax, 4)
+	{nf}	sal	$1, 291(%r8, %rax, 4), %bl
+	{nf}	salw	$1, 291(%r8, %rax, 4)
+	{nf}	sal	$1, 291(%r8, %rax, 4), %dx
+	{nf}	sall	$1, 291(%r8, %rax, 4)
+	{nf}	sal	$1, 291(%r8, %rax, 4), %ecx
+	{nf}	salq	$1, 291(%r8, %rax, 4)
+	{nf}	sal	$1, 291(%r8, %rax, 4), %r9
+	{nf}	sal	$123, %bl
+	{nf}	sal	$123, %bl, %dl
+	{nf}	sal	$123, %dx
+	{nf}	sal	$123, %dx, %ax
+	{nf}	sal	$123, %ecx
+	{nf}	sal	$123, %ecx, %edx
+	{nf}	sal	$123, %r9
+	{nf}	sal	$123, %r9, %r31
+	{nf}	salb	$123, 291(%r8, %rax, 4)
+	{nf}	sal	$123, 291(%r8, %rax, 4), %bl
+	{nf}	salw	$123, 291(%r8, %rax, 4)
+	{nf}	sal	$123, 291(%r8, %rax, 4), %dx
+	{nf}	sall	$123, 291(%r8, %rax, 4)
+	{nf}	sal	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	salq	$123, 291(%r8, %rax, 4)
+	{nf}	sal	$123, 291(%r8, %rax, 4), %r9
+	{nf}	sal	%cl, %bl
+	{nf}	sal	%cl, %bl, %dl
+	{nf}	sal	%cl, %dx
+	{nf}	sal	%cl, %dx, %ax
+	{nf}	sal	%cl, %ecx
+	{nf}	sal	%cl, %ecx, %edx
+	{nf}	sal	%cl, %r9
+	{nf}	sal	%cl, %r9, %r31
+	{nf}	salb	%cl, 291(%r8, %rax, 4)
+	{nf}	sal	%cl, 291(%r8, %rax, 4), %bl
+	{nf}	salw	%cl, 291(%r8, %rax, 4)
+	{nf}	sal	%cl, 291(%r8, %rax, 4), %dx
+	{nf}	sall	%cl, 291(%r8, %rax, 4)
+	{nf}	sal	%cl, 291(%r8, %rax, 4), %ecx
+	{nf}	salq	%cl, 291(%r8, %rax, 4)
+	{nf}	sal	%cl, 291(%r8, %rax, 4), %r9
+	{nf}	shl	$1, %bl
+	{nf}	shl	$1, %bl, %dl
+	{nf}	shl	$1, %dx
+	{nf}	shl	$1, %dx, %ax
+	{nf}	shl	$1, %ecx
+	{nf}	shl	$1, %ecx, %edx
+	{nf}	shl	$1, %r9
+	{nf}	shl	$1, %r9, %r31
+	{nf}	shlb	$1, 291(%r8, %rax, 4)
+	{nf}	shl	$1, 291(%r8, %rax, 4), %bl
+	{nf}	shlw	$1, 291(%r8, %rax, 4)
+	{nf}	shl	$1, 291(%r8, %rax, 4), %dx
+	{nf}	shll	$1, 291(%r8, %rax, 4)
+	{nf}	shl	$1, 291(%r8, %rax, 4), %ecx
+	{nf}	shlq	$1, 291(%r8, %rax, 4)
+	{nf}	shl	$1, 291(%r8, %rax, 4), %r9
+	{nf}	shl	$123, %bl
+	{nf}	shl	$123, %bl, %dl
+	{nf}	shl	$123, %dx
+	{nf}	shl	$123, %dx, %ax
+	{nf}	shl	$123, %ecx
+	{nf}	shl	$123, %ecx, %edx
+	{nf}	shl	$123, %r9
+	{nf}	shl	$123, %r9, %r31
+	{nf}	shlb	$123, 291(%r8, %rax, 4)
+	{nf}	shl	$123, 291(%r8, %rax, 4), %bl
+	{nf}	shlw	$123, 291(%r8, %rax, 4)
+	{nf}	shl	$123, 291(%r8, %rax, 4), %dx
+	{nf}	shll	$123, 291(%r8, %rax, 4)
+	{nf}	shl	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	shlq	$123, 291(%r8, %rax, 4)
+	{nf}	shl	$123, 291(%r8, %rax, 4), %r9
+	{nf}	shl	%cl, %bl
+	{nf}	shl	%cl, %bl, %dl
+	{nf}	shl	%cl, %dx
+	{nf}	shl	%cl, %dx, %ax
+	{nf}	shl	%cl, %ecx
+	{nf}	shl	%cl, %ecx, %edx
+	{nf}	shl	%cl, %r9
+	{nf}	shl	%cl, %r9, %r31
+	{nf}	shlb	%cl, 291(%r8, %rax, 4)
+	{nf}	shl	%cl, 291(%r8, %rax, 4), %bl
+	{nf}	shlw	%cl, 291(%r8, %rax, 4)
+	{nf}	shl	%cl, 291(%r8, %rax, 4), %dx
+	{nf}	shll	%cl, 291(%r8, %rax, 4)
+	{nf}	shl	%cl, 291(%r8, %rax, 4), %ecx
+	{nf}	shlq	%cl, 291(%r8, %rax, 4)
+	{nf}	shl	%cl, 291(%r8, %rax, 4), %r9
+	{nf}	shld	$123, %dx, %ax
+	{nf}	shld	$123, %dx, %ax, %r9w
+	{nf}	shld	$123, %dx, 291(%r8, %rax, 4)
+	{nf}	shld	$123, %dx, 291(%r8, %rax, 4), %ax
+	{nf}	shld	$123, %ecx, %edx
+	{nf}	shld	$123, %ecx, %edx, %r10d
+	{nf}	shld	$123, %ecx, 291(%r8, %rax, 4)
+	{nf}	shld	$123, %ecx, 291(%r8, %rax, 4), %edx
+	{nf}	shld	$123, %r9, %r31
+	{nf}	shld	$123, %r9, %r31, %r11
+	{nf}	shld	$123, %r9, 291(%r8, %rax, 4)
+	{nf}	shld	$123, %r9, 291(%r8, %rax, 4), %r31
+	{nf}	shld	%cl, %dx, %ax
+	{nf}	shld	%cl, %dx, %ax, %r9w
+	{nf}	shld	%cl, %dx, 291(%r8, %rax, 4)
+	{nf}	shld	%cl, %dx, 291(%r8, %rax, 4), %ax
+	{nf}	shld	%cl, %ecx, %edx
+	{nf}	shld	%cl, %ecx, %edx, %r10d
+	{nf}	shld	%cl, %ecx, 291(%r8, %rax, 4)
+	{nf}	shld	%cl, %ecx, 291(%r8, %rax, 4), %edx
+	{nf}	shld	%cl, %r9, %r31
+	{nf}	shld	%cl, %r9, %r31, %r11
+	{nf}	shld	%cl, %r9, 291(%r8, %rax, 4)
+	{nf}	shld	%cl, %r9, 291(%r8, %rax, 4), %r31
+	{nf}	shr	$1, %bl
+	{nf}	shr	$1, %bl, %dl
+	{nf}	shr	$1, %dx
+	{nf}	shr	$1, %dx, %ax
+	{nf}	shr	$1, %ecx
+	{nf}	shr	$1, %ecx, %edx
+	{nf}	shr	$1, %r9
+	{nf}	shr	$1, %r9, %r31
+	{nf}	shrb	$1, 291(%r8, %rax, 4)
+	{nf}	shr	$1, 291(%r8, %rax, 4), %bl
+	{nf}	shrw	$1, 291(%r8, %rax, 4)
+	{nf}	shr	$1, 291(%r8, %rax, 4), %dx
+	{nf}	shrl	$1, 291(%r8, %rax, 4)
+	{nf}	shr	$1, 291(%r8, %rax, 4), %ecx
+	{nf}	shrq	$1, 291(%r8, %rax, 4)
+	{nf}	shr	$1, 291(%r8, %rax, 4), %r9
+	{nf}	shr	$123, %bl
+	{nf}	shr	$123, %bl, %dl
+	{nf}	shr	$123, %dx
+	{nf}	shr	$123, %dx, %ax
+	{nf}	shr	$123, %ecx
+	{nf}	shr	$123, %ecx, %edx
+	{nf}	shr	$123, %r9
+	{nf}	shr	$123, %r9, %r31
+	{nf}	shrb	$123, 291(%r8, %rax, 4)
+	{nf}	shr	$123, 291(%r8, %rax, 4), %bl
+	{nf}	shrw	$123, 291(%r8, %rax, 4)
+	{nf}	shr	$123, 291(%r8, %rax, 4), %dx
+	{nf}	shrl	$123, 291(%r8, %rax, 4)
+	{nf}	shr	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	shrq	$123, 291(%r8, %rax, 4)
+	{nf}	shr	$123, 291(%r8, %rax, 4), %r9
+	{nf}	shr	%cl, %bl
+	{nf}	shr	%cl, %bl, %dl
+	{nf}	shr	%cl, %dx
+	{nf}	shr	%cl, %dx, %ax
+	{nf}	shr	%cl, %ecx
+	{nf}	shr	%cl, %ecx, %edx
+	{nf}	shr	%cl, %r9
+	{nf}	shr	%cl, %r9, %r31
+	{nf}	shrb	%cl, 291(%r8, %rax, 4)
+	{nf}	shr	%cl, 291(%r8, %rax, 4), %bl
+	{nf}	shrw	%cl, 291(%r8, %rax, 4)
+	{nf}	shr	%cl, 291(%r8, %rax, 4), %dx
+	{nf}	shrl	%cl, 291(%r8, %rax, 4)
+	{nf}	shr	%cl, 291(%r8, %rax, 4), %ecx
+	{nf}	shrq	%cl, 291(%r8, %rax, 4)
+	{nf}	shr	%cl, 291(%r8, %rax, 4), %r9
+	{nf}	shrd	$123, %dx, %ax
+	{nf}	shrd	$123, %dx, %ax, %r9w
+	{nf}	shrd	$123, %dx, 291(%r8, %rax, 4)
+	{nf}	shrd	$123, %dx, 291(%r8, %rax, 4), %ax
+	{nf}	shrd	$123, %ecx, %edx
+	{nf}	shrd	$123, %ecx, %edx, %r10d
+	{nf}	shrd	$123, %ecx, 291(%r8, %rax, 4)
+	{nf}	shrd	$123, %ecx, 291(%r8, %rax, 4), %edx
+	{nf}	shrd	$123, %r9, %r31
+	{nf}	shrd	$123, %r9, %r31, %r11
+	{nf}	shrd	$123, %r9, 291(%r8, %rax, 4)
+	{nf}	shrd	$123, %r9, 291(%r8, %rax, 4), %r31
+	{nf}	shrd	%cl, %dx, %ax
+	{nf}	shrd	%cl, %dx, %ax, %r9w
+	{nf}	shrd	%cl, %dx, 291(%r8, %rax, 4)
+	{nf}	shrd	%cl, %dx, 291(%r8, %rax, 4), %ax
+	{nf}	shrd	%cl, %ecx, %edx
+	{nf}	shrd	%cl, %ecx, %edx, %r10d
+	{nf}	shrd	%cl, %ecx, 291(%r8, %rax, 4)
+	{nf}	shrd	%cl, %ecx, 291(%r8, %rax, 4), %edx
+	{nf}	shrd	%cl, %r9, %r31
+	{nf}	shrd	%cl, %r9, %r31, %r11
+	{nf}	shrd	%cl, %r9, 291(%r8, %rax, 4)
+	{nf}	shrd	%cl, %r9, 291(%r8, %rax, 4), %r31
+	{nf}	sub	$123, %bl
+	{nf}	sub	$123, %bl, %dl
+	{nf}	sub	$123, %dx
+	{nf}	sub	$123, %dx, %ax
+	{nf}	sub	$123, %ecx
+	{nf}	sub	$123, %ecx, %edx
+	{nf}	sub	$123, %r9
+	{nf}	sub	$123, %r9, %r31
+	{nf}	subb	$123, 291(%r8, %rax, 4)
+	{nf}	sub	$123, 291(%r8, %rax, 4), %bl
+	{nf}	subw	$123, 291(%r8, %rax, 4)
+	{nf}	sub	$123, 291(%r8, %rax, 4), %dx
+	{nf}	subl	$123, 291(%r8, %rax, 4)
+	{nf}	sub	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	subq	$123, 291(%r8, %rax, 4)
+	{nf}	sub	$123, 291(%r8, %rax, 4), %r9
+	{nf}	sub	%bl, %dl
+	{nf}	sub	%bl, %dl, %r8b
+	{nf}	sub	%bl, 291(%r8, %rax, 4)
+	{nf}	sub	%bl, 291(%r8, %rax, 4), %dl
+	{nf}	sub	%dx, %ax
+	{nf}	sub	%dx, %ax, %r9w
+	{nf}	sub	%dx, 291(%r8, %rax, 4)
+	{nf}	sub	%dx, 291(%r8, %rax, 4), %ax
+	{nf}	sub	%ecx, %edx
+	{nf}	sub	%ecx, %edx, %r10d
+	{nf}	sub	%ecx, 291(%r8, %rax, 4)
+	{nf}	sub	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	sub	%r9, %r31
+	{nf}	sub	%r9, %r31, %r11
+	{nf}	sub	%r9, 291(%r8, %rax, 4)
+	{nf}	sub	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	sub	291(%r8, %rax, 4), %bl
+	{nf}	sub	291(%r8, %rax, 4), %bl, %dl
+	{nf}	sub	291(%r8, %rax, 4), %dx
+	{nf}	sub	291(%r8, %rax, 4), %dx, %ax
+	{nf}	sub	291(%r8, %rax, 4), %ecx
+	{nf}	sub	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	sub	291(%r8, %rax, 4), %r9
+	{nf}	sub	291(%r8, %rax, 4), %r9, %r31
+	{nf}	tzcnt	%dx, %ax
+	{nf}	tzcnt	%ecx, %edx
+	{nf}	tzcnt	%r9, %r31
+	{nf}	tzcnt	291(%r8, %rax, 4), %dx
+	{nf}	tzcnt	291(%r8, %rax, 4), %ecx
+	{nf}	tzcnt	291(%r8, %rax, 4), %r9
+	{nf}	xor	$123, %bl
+	{nf}	xor	$123, %bl, %dl
+	{nf}	xor	$123, %dx
+	{nf}	xor	$123, %dx, %ax
+	{nf}	xor	$123, %ecx
+	{nf}	xor	$123, %ecx, %edx
+	{nf}	xor	$123, %r9
+	{nf}	xor	$123, %r9, %r31
+	{nf}	xorb	$123, 291(%r8, %rax, 4)
+	{nf}	xor	$123, 291(%r8, %rax, 4), %bl
+	{nf}	xorw	$123, 291(%r8, %rax, 4)
+	{nf}	xor	$123, 291(%r8, %rax, 4), %dx
+	{nf}	xorl	$123, 291(%r8, %rax, 4)
+	{nf}	xor	$123, 291(%r8, %rax, 4), %ecx
+	{nf}	xorq	$123, 291(%r8, %rax, 4)
+	{nf}	xor	$123, 291(%r8, %rax, 4), %r9
+	{nf}	xor	%bl, %dl
+	{nf}	xor	%bl, %dl, %r8b
+	{nf}	xor	%bl, 291(%r8, %rax, 4)
+	{nf}	xor	%bl, 291(%r8, %rax, 4), %dl
+	{nf}	xor	%dx, %ax
+	{nf}	xor	%dx, %ax, %r9w
+	{nf}	xor	%dx, 291(%r8, %rax, 4)
+	{nf}	xor	%dx, 291(%r8, %rax, 4), %ax
+	{nf}	xor	%ecx, %edx
+	{nf}	xor	%ecx, %edx, %r10d
+	{nf}	xor	%ecx, 291(%r8, %rax, 4)
+	{nf}	xor	%ecx, 291(%r8, %rax, 4), %edx
+	{nf}	xor	%r9, %r31
+	{nf}	xor	%r9, %r31, %r11
+	{nf}	xor	%r9, 291(%r8, %rax, 4)
+	{nf}	xor	%r9, 291(%r8, %rax, 4), %r31
+	{nf}	xor	291(%r8, %rax, 4), %bl
+	{nf}	xor	291(%r8, %rax, 4), %bl, %dl
+	{nf}	xor	291(%r8, %rax, 4), %dx
+	{nf}	xor	291(%r8, %rax, 4), %dx, %ax
+	{nf}	xor	291(%r8, %rax, 4), %ecx
+	{nf}	xor	291(%r8, %rax, 4), %ecx, %edx
+	{nf}	xor	291(%r8, %rax, 4), %r9
+	{nf}	xor	291(%r8, %rax, 4), %r9, %r31
+
+.intel_syntax noprefix
+	{nf}	add	bl, 123
+	{nf}	add	dl, bl, 123
+	{nf}	add	dx, 123
+	{nf}	add	ax, dx, 123
+	{nf}	add	ecx, 123
+	{nf}	add	edx, ecx, 123
+	{nf}	add	r9, 123
+	{nf}	add	r31, r9, 123
+	{nf}	add	BYTE PTR [r8+rax*4+291], 123
+	{nf}	add	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	add	WORD PTR [r8+rax*4+291], 123
+	{nf}	add	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	add	DWORD PTR [r8+rax*4+291], 123
+	{nf}	add	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	add	QWORD PTR [r8+rax*4+291], 123
+	{nf}	add	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	add	dl, bl
+	{nf}	add	r8b, dl, bl
+	{nf}	add	BYTE PTR [r8+rax*4+291], bl
+	{nf}	add	dl, BYTE PTR [r8+rax*4+291], bl
+	{nf}	add	ax, dx
+	{nf}	add	r9w, ax, dx
+	{nf}	add	WORD PTR [r8+rax*4+291], dx
+	{nf}	add	ax, WORD PTR [r8+rax*4+291], dx
+	{nf}	add	edx, ecx
+	{nf}	add	r10d, edx, ecx
+	{nf}	add	DWORD PTR [r8+rax*4+291], ecx
+	{nf}	add	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	add	r31, r9
+	{nf}	add	r11, r31, r9
+	{nf}	add	QWORD PTR [r8+rax*4+291], r9
+	{nf}	add	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	add	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	add	dl, bl, BYTE PTR [r8+rax*4+291]
+	{nf}	add	dx, WORD PTR [r8+rax*4+291]
+	{nf}	add	ax, dx, WORD PTR [r8+rax*4+291]
+	{nf}	add	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	add	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	add	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	add	r31, r9, QWORD PTR [r8+rax*4+291]
+	{nf}	and	bl, 123
+	{nf}	and	dl, bl, 123
+	{nf}	and	dx, 123
+	{nf}	and	ax, dx, 123
+	{nf}	and	ecx, 123
+	{nf}	and	edx, ecx, 123
+	{nf}	and	r9, 123
+	{nf}	and	r31, r9, 123
+	{nf}	and	BYTE PTR [r8+rax*4+291], 123
+	{nf}	and	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	and	WORD PTR [r8+rax*4+291], 123
+	{nf}	and	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	and	DWORD PTR [r8+rax*4+291], 123
+	{nf}	and	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	and	QWORD PTR [r8+rax*4+291], 123
+	{nf}	and	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	and	dl, bl
+	{nf}	and	r8b, dl, bl
+	{nf}	and	BYTE PTR [r8+rax*4+291], bl
+	{nf}	and	dl, BYTE PTR [r8+rax*4+291], bl
+	{nf}	and	ax, dx
+	{nf}	and	r9w, ax, dx
+	{nf}	and	WORD PTR [r8+rax*4+291], dx
+	{nf}	and	ax, WORD PTR [r8+rax*4+291], dx
+	{nf}	and	edx, ecx
+	{nf}	and	r10d, edx, ecx
+	{nf}	and	DWORD PTR [r8+rax*4+291], ecx
+	{nf}	and	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	and	r31, r9
+	{nf}	and	r11, r31, r9
+	{nf}	and	QWORD PTR [r8+rax*4+291], r9
+	{nf}	and	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	and	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	and	dl, bl, BYTE PTR [r8+rax*4+291]
+	{nf}	and	dx, WORD PTR [r8+rax*4+291]
+	{nf}	and	ax, dx, WORD PTR [r8+rax*4+291]
+	{nf}	and	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	and	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	and	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	and	r31, r9, QWORD PTR [r8+rax*4+291]
+	{nf}	andn	r10d, edx, ecx
+	{nf}	andn	r11, r31, r9
+	{nf}	andn	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	andn	r31, r9, QWORD PTR [r8+rax*4+291]
+	{nf}	bextr	r10d, edx, ecx
+	{nf}	bextr	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	bextr	r11, r31, r9
+	{nf}	bextr	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	blsi	edx, ecx
+	{nf}	blsi	r31, r9
+	{nf}	blsi	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	blsi	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	blsmsk	edx, ecx
+	{nf}	blsmsk	r31, r9
+	{nf}	blsmsk	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	blsmsk	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	blsr	edx, ecx
+	{nf}	blsr	r31, r9
+	{nf}	blsr	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	blsr	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	bzhi	r10d, edx, ecx
+	{nf}	bzhi	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	bzhi	r11, r31, r9
+	{nf}	bzhi	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	dec	bl
+	{nf}	dec	dl, bl
+	{nf}	dec	dx
+	{nf}	dec	ax, dx
+	{nf}	dec	ecx
+	{nf}	dec	edx, ecx
+	{nf}	dec	r9
+	{nf}	dec	r31, r9
+	{nf}	dec	BYTE PTR [r8+rax*4+291]
+	{nf}	dec	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	dec	WORD PTR [r8+rax*4+291]
+	{nf}	dec	dx, WORD PTR [r8+rax*4+291]
+	{nf}	dec	DWORD PTR [r8+rax*4+291]
+	{nf}	dec	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	dec	QWORD PTR [r8+rax*4+291]
+	{nf}	dec	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	div	bl
+	{nf}	div	dx
+	{nf}	div	ecx
+	{nf}	div	r9
+	{nf}	div	BYTE PTR [r8+rax*4+291]
+	{nf}	div	WORD PTR [r8+rax*4+291]
+	{nf}	div	DWORD PTR [r8+rax*4+291]
+	{nf}	div	QWORD PTR [r8+rax*4+291]
+	{nf}	idiv	bl
+	{nf}	idiv	dx
+	{nf}	idiv	ecx
+	{nf}	idiv	r9
+	{nf}	idiv	BYTE PTR [r8+rax*4+291]
+	{nf}	idiv	WORD PTR [r8+rax*4+291]
+	{nf}	idiv	DWORD PTR [r8+rax*4+291]
+	{nf}	idiv	QWORD PTR [r8+rax*4+291]
+	{nf}	imul	bl
+	{nf}	imul	dx
+	{nf}	imul	ax, dx
+	{nf}	imul	r9w, ax, dx
+	{nf}	imul	ecx
+	{nf}	imul	edx, ecx
+	{nf}	imul	r10d, edx, ecx
+	{nf}	imul	r9
+	{nf}	imul	r31, r9
+	{nf}	imul	r11, r31, r9
+	{nf}	imul	BYTE PTR [r8+rax*4+291]
+	{nf}	imul	WORD PTR [r8+rax*4+291]
+	{nf}	imul	dx, WORD PTR [r8+rax*4+291]
+	{nf}	imul	ax, dx, WORD PTR [r8+rax*4+291]
+	{nf}	imul	DWORD PTR [r8+rax*4+291]
+	{nf}	imul	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	imul	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	imul	QWORD PTR [r8+rax*4+291]
+	{nf}	imul	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	imul	r31, r9, QWORD PTR [r8+rax*4+291]
+	{nf}	inc	bl
+	{nf}	inc	dl, bl
+	{nf}	inc	dx
+	{nf}	inc	ax, dx
+	{nf}	inc	ecx
+	{nf}	inc	edx, ecx
+	{nf}	inc	r9
+	{nf}	inc	r31, r9
+	{nf}	inc	BYTE PTR [r8+rax*4+291]
+	{nf}	inc	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	inc	WORD PTR [r8+rax*4+291]
+	{nf}	inc	dx, WORD PTR [r8+rax*4+291]
+	{nf}	inc	DWORD PTR [r8+rax*4+291]
+	{nf}	inc	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	inc	QWORD PTR [r8+rax*4+291]
+	{nf}	inc	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	lzcnt	ax, dx
+	{nf}	lzcnt	edx, ecx
+	{nf}	lzcnt	r31, r9
+	{nf}	lzcnt	dx, WORD PTR [r8+rax*4+291]
+	{nf}	lzcnt	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	lzcnt	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	mul	bl
+	{nf}	mul	dx
+	{nf}	mul	ecx
+	{nf}	mul	r9
+	{nf}	mul	BYTE PTR [r8+rax*4+291]
+	{nf}	mul	WORD PTR [r8+rax*4+291]
+	{nf}	mul	DWORD PTR [r8+rax*4+291]
+	{nf}	mul	QWORD PTR [r8+rax*4+291]
+	{nf}	neg	bl
+	{nf}	neg	dl, bl
+	{nf}	neg	dx
+	{nf}	neg	ax, dx
+	{nf}	neg	ecx
+	{nf}	neg	edx, ecx
+	{nf}	neg	r9
+	{nf}	neg	r31, r9
+	{nf}	neg	BYTE PTR [r8+rax*4+291]
+	{nf}	neg	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	neg	WORD PTR [r8+rax*4+291]
+	{nf}	neg	dx, WORD PTR [r8+rax*4+291]
+	{nf}	neg	DWORD PTR [r8+rax*4+291]
+	{nf}	neg	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	neg	QWORD PTR [r8+rax*4+291]
+	{nf}	neg	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	or	bl, 123
+	{nf}	or	dl, bl, 123
+	{nf}	or	dx, 123
+	{nf}	or	ax, dx, 123
+	{nf}	or	ecx, 123
+	{nf}	or	edx, ecx, 123
+	{nf}	or	r9, 123
+	{nf}	or	r31, r9, 123
+	{nf}	or	BYTE PTR [r8+rax*4+291], 123
+	{nf}	or	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	or	WORD PTR [r8+rax*4+291], 123
+	{nf}	or	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	or	DWORD PTR [r8+rax*4+291], 123
+	{nf}	or	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	or	QWORD PTR [r8+rax*4+291], 123
+	{nf}	or	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	or	dl, bl
+	{nf}	or	r8b, dl, bl
+	{nf}	or	BYTE PTR [r8+rax*4+291], bl
+	{nf}	or	dl, BYTE PTR [r8+rax*4+291], bl
+	{nf}	or	ax, dx
+	{nf}	or	r9w, ax, dx
+	{nf}	or	WORD PTR [r8+rax*4+291], dx
+	{nf}	or	ax, WORD PTR [r8+rax*4+291], dx
+	{nf}	or	edx, ecx
+	{nf}	or	r10d, edx, ecx
+	{nf}	or	DWORD PTR [r8+rax*4+291], ecx
+	{nf}	or	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	or	r31, r9
+	{nf}	or	r11, r31, r9
+	{nf}	or	QWORD PTR [r8+rax*4+291], r9
+	{nf}	or	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	or	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	or	dl, bl, BYTE PTR [r8+rax*4+291]
+	{nf}	or	dx, WORD PTR [r8+rax*4+291]
+	{nf}	or	ax, dx, WORD PTR [r8+rax*4+291]
+	{nf}	or	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	or	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	or	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	or	r31, r9, QWORD PTR [r8+rax*4+291]
+	{nf}	popcnt	ax, dx
+	{nf}	popcnt	edx, ecx
+	{nf}	popcnt	r31, r9
+	{nf}	popcnt	dx, WORD PTR [r8+rax*4+291]
+	{nf}	popcnt	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	popcnt	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	rol	bl, 1
+	{nf}	rol	dl, bl, 1
+	{nf}	rol	dx, 1
+	{nf}	rol	ax, dx, 1
+	{nf}	rol	ecx, 1
+	{nf}	rol	edx, ecx, 1
+	{nf}	rol	r9, 1
+	{nf}	rol	r31, r9, 1
+	{nf}	rol	BYTE PTR [r8+rax*4+291], 1
+	{nf}	rol	bl, BYTE PTR [r8+rax*4+291], 1
+	{nf}	rol	WORD PTR [r8+rax*4+291], 1
+	{nf}	rol	dx, WORD PTR [r8+rax*4+291], 1
+	{nf}	rol	DWORD PTR [r8+rax*4+291], 1
+	{nf}	rol	ecx, DWORD PTR [r8+rax*4+291], 1
+	{nf}	rol	QWORD PTR [r8+rax*4+291], 1
+	{nf}	rol	r9, QWORD PTR [r8+rax*4+291], 1
+	{nf}	rol	bl, 123
+	{nf}	rol	dl, bl, 123
+	{nf}	rol	dx, 123
+	{nf}	rol	ax, dx, 123
+	{nf}	rol	ecx, 123
+	{nf}	rol	edx, ecx, 123
+	{nf}	rol	r9, 123
+	{nf}	rol	r31, r9, 123
+	{nf}	rol	BYTE PTR [r8+rax*4+291], 123
+	{nf}	rol	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	rol	WORD PTR [r8+rax*4+291], 123
+	{nf}	rol	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	rol	DWORD PTR [r8+rax*4+291], 123
+	{nf}	rol	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	rol	QWORD PTR [r8+rax*4+291], 123
+	{nf}	rol	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	rol	bl, cl
+	{nf}	rol	dl, bl, cl
+	{nf}	rol	dx, cl
+	{nf}	rol	ax, dx, cl
+	{nf}	rol	ecx, cl
+	{nf}	rol	edx, ecx, cl
+	{nf}	rol	r9, cl
+	{nf}	rol	r31, r9, cl
+	{nf}	rol	BYTE PTR [r8+rax*4+291], cl
+	{nf}	rol	bl, BYTE PTR [r8+rax*4+291], cl
+	{nf}	rol	WORD PTR [r8+rax*4+291], cl
+	{nf}	rol	dx, WORD PTR [r8+rax*4+291], cl
+	{nf}	rol	DWORD PTR [r8+rax*4+291], cl
+	{nf}	rol	ecx, DWORD PTR [r8+rax*4+291], cl
+	{nf}	rol	QWORD PTR [r8+rax*4+291], cl
+	{nf}	rol	r9, QWORD PTR [r8+rax*4+291], cl
+	{nf}	ror	bl, 1
+	{nf}	ror	dl, bl, 1
+	{nf}	ror	dx, 1
+	{nf}	ror	ax, dx, 1
+	{nf}	ror	ecx, 1
+	{nf}	ror	edx, ecx, 1
+	{nf}	ror	r9, 1
+	{nf}	ror	r31, r9, 1
+	{nf}	ror	BYTE PTR [r8+rax*4+291], 1
+	{nf}	ror	bl, BYTE PTR [r8+rax*4+291], 1
+	{nf}	ror	WORD PTR [r8+rax*4+291], 1
+	{nf}	ror	dx, WORD PTR [r8+rax*4+291], 1
+	{nf}	ror	DWORD PTR [r8+rax*4+291], 1
+	{nf}	ror	ecx, DWORD PTR [r8+rax*4+291], 1
+	{nf}	ror	QWORD PTR [r8+rax*4+291], 1
+	{nf}	ror	r9, QWORD PTR [r8+rax*4+291], 1
+	{nf}	ror	bl, 123
+	{nf}	ror	dl, bl, 123
+	{nf}	ror	dx, 123
+	{nf}	ror	ax, dx, 123
+	{nf}	ror	ecx, 123
+	{nf}	ror	edx, ecx, 123
+	{nf}	ror	r9, 123
+	{nf}	ror	r31, r9, 123
+	{nf}	ror	BYTE PTR [r8+rax*4+291], 123
+	{nf}	ror	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	ror	WORD PTR [r8+rax*4+291], 123
+	{nf}	ror	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	ror	DWORD PTR [r8+rax*4+291], 123
+	{nf}	ror	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	ror	QWORD PTR [r8+rax*4+291], 123
+	{nf}	ror	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	ror	bl, cl
+	{nf}	ror	dl, bl, cl
+	{nf}	ror	dx, cl
+	{nf}	ror	ax, dx, cl
+	{nf}	ror	ecx, cl
+	{nf}	ror	edx, ecx, cl
+	{nf}	ror	r9, cl
+	{nf}	ror	r31, r9, cl
+	{nf}	ror	BYTE PTR [r8+rax*4+291], cl
+	{nf}	ror	bl, BYTE PTR [r8+rax*4+291], cl
+	{nf}	ror	WORD PTR [r8+rax*4+291], cl
+	{nf}	ror	dx, WORD PTR [r8+rax*4+291], cl
+	{nf}	ror	DWORD PTR [r8+rax*4+291], cl
+	{nf}	ror	ecx, DWORD PTR [r8+rax*4+291], cl
+	{nf}	ror	QWORD PTR [r8+rax*4+291], cl
+	{nf}	ror	r9, QWORD PTR [r8+rax*4+291], cl
+	{nf}	sar	bl, 1
+	{nf}	sar	dl, bl, 1
+	{nf}	sar	dx, 1
+	{nf}	sar	ax, dx, 1
+	{nf}	sar	ecx, 1
+	{nf}	sar	edx, ecx, 1
+	{nf}	sar	r9, 1
+	{nf}	sar	r31, r9, 1
+	{nf}	sar	BYTE PTR [r8+rax*4+291], 1
+	{nf}	sar	bl, BYTE PTR [r8+rax*4+291], 1
+	{nf}	sar	WORD PTR [r8+rax*4+291], 1
+	{nf}	sar	dx, WORD PTR [r8+rax*4+291], 1
+	{nf}	sar	DWORD PTR [r8+rax*4+291], 1
+	{nf}	sar	ecx, DWORD PTR [r8+rax*4+291], 1
+	{nf}	sar	QWORD PTR [r8+rax*4+291], 1
+	{nf}	sar	r9, QWORD PTR [r8+rax*4+291], 1
+	{nf}	sar	bl, 123
+	{nf}	sar	dl, bl, 123
+	{nf}	sar	dx, 123
+	{nf}	sar	ax, dx, 123
+	{nf}	sar	ecx, 123
+	{nf}	sar	edx, ecx, 123
+	{nf}	sar	r9, 123
+	{nf}	sar	r31, r9, 123
+	{nf}	sar	BYTE PTR [r8+rax*4+291], 123
+	{nf}	sar	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	sar	WORD PTR [r8+rax*4+291], 123
+	{nf}	sar	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	sar	DWORD PTR [r8+rax*4+291], 123
+	{nf}	sar	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	sar	QWORD PTR [r8+rax*4+291], 123
+	{nf}	sar	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	sar	bl, cl
+	{nf}	sar	dl, bl, cl
+	{nf}	sar	dx, cl
+	{nf}	sar	ax, dx, cl
+	{nf}	sar	ecx, cl
+	{nf}	sar	edx, ecx, cl
+	{nf}	sar	r9, cl
+	{nf}	sar	r31, r9, cl
+	{nf}	sar	BYTE PTR [r8+rax*4+291], cl
+	{nf}	sar	bl, BYTE PTR [r8+rax*4+291], cl
+	{nf}	sar	WORD PTR [r8+rax*4+291], cl
+	{nf}	sar	dx, WORD PTR [r8+rax*4+291], cl
+	{nf}	sar	DWORD PTR [r8+rax*4+291], cl
+	{nf}	sar	ecx, DWORD PTR [r8+rax*4+291], cl
+	{nf}	sar	QWORD PTR [r8+rax*4+291], cl
+	{nf}	sar	r9, QWORD PTR [r8+rax*4+291], cl
+	{nf}	shl	bl, 1
+	{nf}	shl	dl, bl, 1
+	{nf}	shl	dx, 1
+	{nf}	shl	ax, dx, 1
+	{nf}	shl	ecx, 1
+	{nf}	shl	edx, ecx, 1
+	{nf}	shl	r9, 1
+	{nf}	shl	r31, r9, 1
+	{nf}	shl	BYTE PTR [r8+rax*4+291], 1
+	{nf}	shl	bl, BYTE PTR [r8+rax*4+291], 1
+	{nf}	shl	WORD PTR [r8+rax*4+291], 1
+	{nf}	shl	dx, WORD PTR [r8+rax*4+291], 1
+	{nf}	shl	DWORD PTR [r8+rax*4+291], 1
+	{nf}	shl	ecx, DWORD PTR [r8+rax*4+291], 1
+	{nf}	shl	QWORD PTR [r8+rax*4+291], 1
+	{nf}	shl	r9, QWORD PTR [r8+rax*4+291], 1
+	{nf}	shl	bl, 123
+	{nf}	shl	dl, bl, 123
+	{nf}	shl	dx, 123
+	{nf}	shl	ax, dx, 123
+	{nf}	shl	ecx, 123
+	{nf}	shl	edx, ecx, 123
+	{nf}	shl	r9, 123
+	{nf}	shl	r31, r9, 123
+	{nf}	shl	BYTE PTR [r8+rax*4+291], 123
+	{nf}	shl	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	shl	WORD PTR [r8+rax*4+291], 123
+	{nf}	shl	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	shl	DWORD PTR [r8+rax*4+291], 123
+	{nf}	shl	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	shl	QWORD PTR [r8+rax*4+291], 123
+	{nf}	shl	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	shl	bl, cl
+	{nf}	shl	dl, bl, cl
+	{nf}	shl	dx, cl
+	{nf}	shl	ax, dx, cl
+	{nf}	shl	ecx, cl
+	{nf}	shl	edx, ecx, cl
+	{nf}	shl	r9, cl
+	{nf}	shl	r31, r9, cl
+	{nf}	shl	BYTE PTR [r8+rax*4+291], cl
+	{nf}	shl	bl, BYTE PTR [r8+rax*4+291], cl
+	{nf}	shl	WORD PTR [r8+rax*4+291], cl
+	{nf}	shl	dx, WORD PTR [r8+rax*4+291], cl
+	{nf}	shl	DWORD PTR [r8+rax*4+291], cl
+	{nf}	shl	ecx, DWORD PTR [r8+rax*4+291], cl
+	{nf}	shl	QWORD PTR [r8+rax*4+291], cl
+	{nf}	shl	r9, QWORD PTR [r8+rax*4+291], cl
+	{nf}	shld	ax, dx, 123
+	{nf}	shld	r9w, ax, dx, 123
+	{nf}	shld	WORD PTR [r8+rax*4+291], dx, 123
+	{nf}	shld	ax, WORD PTR [r8+rax*4+291], dx, 123
+	{nf}	shld	edx, ecx, 123
+	{nf}	shld	r10d, edx, ecx, 123
+	{nf}	shld	DWORD PTR [r8+rax*4+291], ecx, 123
+	{nf}	shld	edx, DWORD PTR [r8+rax*4+291], ecx, 123
+	{nf}	shld	r31, r9, 123
+	{nf}	shld	r11, r31, r9, 123
+	{nf}	shld	QWORD PTR [r8+rax*4+291], r9, 123
+	{nf}	shld	r31, QWORD PTR [r8+rax*4+291], r9, 123
+	{nf}	shld	ax, dx, cl
+	{nf}	shld	r9w, ax, dx, cl
+	{nf}	shld	WORD PTR [r8+rax*4+291], dx, cl
+	{nf}	shld	ax, WORD PTR [r8+rax*4+291], dx, cl
+	{nf}	shld	edx, ecx, cl
+	{nf}	shld	r10d, edx, ecx, cl
+	{nf}	shld	DWORD PTR [r8+rax*4+291], ecx, cl
+	{nf}	shld	edx, DWORD PTR [r8+rax*4+291], ecx, cl
+	{nf}	shld	r31, r9, cl
+	{nf}	shld	r11, r31, r9, cl
+	{nf}	shld	QWORD PTR [r8+rax*4+291], r9, cl
+	{nf}	shld	r31, QWORD PTR [r8+rax*4+291], r9, cl
+	{nf}	shr	bl, 1
+	{nf}	shr	dl, bl, 1
+	{nf}	shr	dx, 1
+	{nf}	shr	ax, dx, 1
+	{nf}	shr	ecx, 1
+	{nf}	shr	edx, ecx, 1
+	{nf}	shr	r9, 1
+	{nf}	shr	r31, r9, 1
+	{nf}	shr	BYTE PTR [r8+rax*4+291], 1
+	{nf}	shr	bl, BYTE PTR [r8+rax*4+291], 1
+	{nf}	shr	WORD PTR [r8+rax*4+291], 1
+	{nf}	shr	dx, WORD PTR [r8+rax*4+291], 1
+	{nf}	shr	DWORD PTR [r8+rax*4+291], 1
+	{nf}	shr	ecx, DWORD PTR [r8+rax*4+291], 1
+	{nf}	shr	QWORD PTR [r8+rax*4+291], 1
+	{nf}	shr	r9, QWORD PTR [r8+rax*4+291], 1
+	{nf}	shr	bl, 123
+	{nf}	shr	dl, bl, 123
+	{nf}	shr	dx, 123
+	{nf}	shr	ax, dx, 123
+	{nf}	shr	ecx, 123
+	{nf}	shr	edx, ecx, 123
+	{nf}	shr	r9, 123
+	{nf}	shr	r31, r9, 123
+	{nf}	shr	BYTE PTR [r8+rax*4+291], 123
+	{nf}	shr	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	shr	WORD PTR [r8+rax*4+291], 123
+	{nf}	shr	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	shr	DWORD PTR [r8+rax*4+291], 123
+	{nf}	shr	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	shr	QWORD PTR [r8+rax*4+291], 123
+	{nf}	shr	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	shr	bl, cl
+	{nf}	shr	dl, bl, cl
+	{nf}	shr	dx, cl
+	{nf}	shr	ax, dx, cl
+	{nf}	shr	ecx, cl
+	{nf}	shr	edx, ecx, cl
+	{nf}	shr	r9, cl
+	{nf}	shr	r31, r9, cl
+	{nf}	shr	BYTE PTR [r8+rax*4+291], cl
+	{nf}	shr	bl, BYTE PTR [r8+rax*4+291], cl
+	{nf}	shr	WORD PTR [r8+rax*4+291], cl
+	{nf}	shr	dx, WORD PTR [r8+rax*4+291], cl
+	{nf}	shr	DWORD PTR [r8+rax*4+291], cl
+	{nf}	shr	ecx, DWORD PTR [r8+rax*4+291], cl
+	{nf}	shr	QWORD PTR [r8+rax*4+291], cl
+	{nf}	shr	r9, QWORD PTR [r8+rax*4+291], cl
+	{nf}	shrd	ax, dx, 123
+	{nf}	shrd	r9w, ax, dx, 123
+	{nf}	shrd	WORD PTR [r8+rax*4+291], dx, 123
+	{nf}	shrd	ax, WORD PTR [r8+rax*4+291], dx, 123
+	{nf}	shrd	edx, ecx, 123
+	{nf}	shrd	r10d, edx, ecx, 123
+	{nf}	shrd	DWORD PTR [r8+rax*4+291], ecx, 123
+	{nf}	shrd	edx, DWORD PTR [r8+rax*4+291], ecx, 123
+	{nf}	shrd	r31, r9, 123
+	{nf}	shrd	r11, r31, r9, 123
+	{nf}	shrd	QWORD PTR [r8+rax*4+291], r9, 123
+	{nf}	shrd	r31, QWORD PTR [r8+rax*4+291], r9, 123
+	{nf}	shrd	ax, dx, cl
+	{nf}	shrd	r9w, ax, dx, cl
+	{nf}	shrd	WORD PTR [r8+rax*4+291], dx, cl
+	{nf}	shrd	ax, WORD PTR [r8+rax*4+291], dx, cl
+	{nf}	shrd	edx, ecx, cl
+	{nf}	shrd	r10d, edx, ecx, cl
+	{nf}	shrd	DWORD PTR [r8+rax*4+291], ecx, cl
+	{nf}	shrd	edx, DWORD PTR [r8+rax*4+291], ecx, cl
+	{nf}	shrd	r31, r9, cl
+	{nf}	shrd	r11, r31, r9, cl
+	{nf}	shrd	QWORD PTR [r8+rax*4+291], r9, cl
+	{nf}	shrd	r31, QWORD PTR [r8+rax*4+291], r9, cl
+	{nf}	sub	bl, 123
+	{nf}	sub	dl, bl, 123
+	{nf}	sub	dx, 123
+	{nf}	sub	ax, dx, 123
+	{nf}	sub	ecx, 123
+	{nf}	sub	edx, ecx, 123
+	{nf}	sub	r9, 123
+	{nf}	sub	r31, r9, 123
+	{nf}	sub	BYTE PTR [r8+rax*4+291], 123
+	{nf}	sub	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	sub	WORD PTR [r8+rax*4+291], 123
+	{nf}	sub	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	sub	DWORD PTR [r8+rax*4+291], 123
+	{nf}	sub	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	sub	QWORD PTR [r8+rax*4+291], 123
+	{nf}	sub	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	sub	dl, bl
+	{nf}	sub	r8b, dl, bl
+	{nf}	sub	BYTE PTR [r8+rax*4+291], bl
+	{nf}	sub	dl, BYTE PTR [r8+rax*4+291], bl
+	{nf}	sub	ax, dx
+	{nf}	sub	r9w, ax, dx
+	{nf}	sub	WORD PTR [r8+rax*4+291], dx
+	{nf}	sub	ax, WORD PTR [r8+rax*4+291], dx
+	{nf}	sub	edx, ecx
+	{nf}	sub	r10d, edx, ecx
+	{nf}	sub	DWORD PTR [r8+rax*4+291], ecx
+	{nf}	sub	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	sub	r31, r9
+	{nf}	sub	r11, r31, r9
+	{nf}	sub	QWORD PTR [r8+rax*4+291], r9
+	{nf}	sub	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	sub	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	sub	dl, bl, BYTE PTR [r8+rax*4+291]
+	{nf}	sub	dx, WORD PTR [r8+rax*4+291]
+	{nf}	sub	ax, dx, WORD PTR [r8+rax*4+291]
+	{nf}	sub	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	sub	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	sub	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	sub	r31, r9, QWORD PTR [r8+rax*4+291]
+	{nf}	tzcnt	ax, dx
+	{nf}	tzcnt	edx, ecx
+	{nf}	tzcnt	r31, r9
+	{nf}	tzcnt	dx, WORD PTR [r8+rax*4+291]
+	{nf}	tzcnt	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	tzcnt	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	xor	bl, 123
+	{nf}	xor	dl, bl, 123
+	{nf}	xor	dx, 123
+	{nf}	xor	ax, dx, 123
+	{nf}	xor	ecx, 123
+	{nf}	xor	edx, ecx, 123
+	{nf}	xor	r9, 123
+	{nf}	xor	r31, r9, 123
+	{nf}	xor	BYTE PTR [r8+rax*4+291], 123
+	{nf}	xor	bl, BYTE PTR [r8+rax*4+291], 123
+	{nf}	xor	WORD PTR [r8+rax*4+291], 123
+	{nf}	xor	dx, WORD PTR [r8+rax*4+291], 123
+	{nf}	xor	DWORD PTR [r8+rax*4+291], 123
+	{nf}	xor	ecx, DWORD PTR [r8+rax*4+291], 123
+	{nf}	xor	QWORD PTR [r8+rax*4+291], 123
+	{nf}	xor	r9, QWORD PTR [r8+rax*4+291], 123
+	{nf}	xor	dl, bl
+	{nf}	xor	r8b, dl, bl
+	{nf}	xor	BYTE PTR [r8+rax*4+291], bl
+	{nf}	xor	dl, BYTE PTR [r8+rax*4+291], bl
+	{nf}	xor	ax, dx
+	{nf}	xor	r9w, ax, dx
+	{nf}	xor	WORD PTR [r8+rax*4+291], dx
+	{nf}	xor	ax, WORD PTR [r8+rax*4+291], dx
+	{nf}	xor	edx, ecx
+	{nf}	xor	r10d, edx, ecx
+	{nf}	xor	DWORD PTR [r8+rax*4+291], ecx
+	{nf}	xor	edx, DWORD PTR [r8+rax*4+291], ecx
+	{nf}	xor	r31, r9
+	{nf}	xor	r11, r31, r9
+	{nf}	xor	QWORD PTR [r8+rax*4+291], r9
+	{nf}	xor	r31, QWORD PTR [r8+rax*4+291], r9
+	{nf}	xor	bl, BYTE PTR [r8+rax*4+291]
+	{nf}	xor	dl, bl, BYTE PTR [r8+rax*4+291]
+	{nf}	xor	dx, WORD PTR [r8+rax*4+291]
+	{nf}	xor	ax, dx, WORD PTR [r8+rax*4+291]
+	{nf}	xor	ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	xor	edx, ecx, DWORD PTR [r8+rax*4+291]
+	{nf}	xor	r9, QWORD PTR [r8+rax*4+291]
+	{nf}	xor	r31, r9, QWORD PTR [r8+rax*4+291]
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index f5a92098fe6..de38cdfe172 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -386,6 +386,8 @@  run_dump_test "x86-64-apx-ndd-wig"
 run_dump_test "x86-64-apx-jmpabs"
 run_dump_test "x86-64-apx-jmpabs-intel"
 run_dump_test "x86-64-apx-jmpabs-inval"
+run_dump_test "x86-64-apx-nf"
+run_dump_test "x86-64-apx-nf-intel"
 run_dump_test "x86-64-avx512f-rcigrz-intel"
 run_dump_test "x86-64-avx512f-rcigrz"
 run_dump_test "x86-64-clwb"
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h
index 81bb41646c5..a3c671697d7 100644
--- a/opcodes/i386-dis-evex-reg.h
+++ b/opcodes/i386-dis-evex-reg.h
@@ -51,33 +51,33 @@ 
   },
   /* REG_EVEX_MAP4_80 */
   {
-    { "addA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "orA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFaddA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NForA",	{ VexGb, Eb, Ib }, NO_PREFIX },
     { "adcA",	{ VexGb, Eb, Ib }, NO_PREFIX },
     { "sbbA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "andA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "subA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "xorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFandA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFsubA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFxorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
   },
   /* REG_EVEX_MAP4_81 */
   {
-    { "addQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
-    { "orQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NFaddQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NForQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
     { "adcQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
     { "sbbQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
-    { "andQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
-    { "subQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
-    { "xorQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NFandQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NFsubQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
+    { "%NFxorQ",	{ VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
   },
   /* REG_EVEX_MAP4_83 */
   {
-    { "addQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
-    { "orQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
+    { "%NFaddQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
+    { "%NForQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
     { "adcQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
     { "sbbQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
-    { "andQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
-    { "subQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
-    { "xorQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
+    { "%NFandQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
+    { "%NFsubQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
+    { "%NFxorQ",	{ VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
   },
   /* REG_EVEX_MAP4_8F */
   {
@@ -87,25 +87,33 @@ 
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "notA",	{ VexGb, Eb }, NO_PREFIX },
-    { "negA",	{ VexGb, Eb }, NO_PREFIX },
+    { "%NFnotA",	{ VexGb, Eb }, NO_PREFIX },
+    { "%NFnegA",	{ VexGb, Eb }, NO_PREFIX },
+    { "%NFmulA",	{ Eb }, NO_PREFIX },
+    { "%NFimulA",	{ Eb }, NO_PREFIX },
+    { "%NFdivA",	{ Eb }, NO_PREFIX },
+    { "%NFidivA",	{ Eb }, NO_PREFIX },
   },
   /* REG_EVEX_MAP4_F7 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "notQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
-    { "negQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFnotQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFnegQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFmulQ",	{ Ev }, PREFIX_NP_OR_DATA },
+    { "%NFimulQ",	{ Ev }, PREFIX_NP_OR_DATA },
+    { "%NFdivQ",	{ Ev }, PREFIX_NP_OR_DATA },
+    { "%NFidivQ",	{ Ev }, PREFIX_NP_OR_DATA },
   },
   /* REG_EVEX_MAP4_FE */
   {
-    { "incA",	{ VexGb, Eb }, NO_PREFIX },
-    { "decA",	{ VexGb, Eb }, NO_PREFIX },
+    { "%NFincA",	{ VexGb, Eb }, NO_PREFIX },
+    { "%NFdecA",	{ VexGb, Eb }, NO_PREFIX },
   },
   /* REG_EVEX_MAP4_FF */
   {
-    { "incQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
-    { "decQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFincQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFdecQ",	{ VexGv, Ev }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 45b52653808..dff5b8b1fa9 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -875,19 +875,19 @@  static const struct dis386 evex_table[][256] = {
   /* EVEX_MAP4_ */
   {
     /* 00 */
-    { "addB",             { VexGb, Eb, Gb }, NO_PREFIX },
-    { "addS",             { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
-    { "addB",             { VexGb, Gb, EbS }, NO_PREFIX },
-    { "addS",             { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
+    { "%NFaddB",		{ VexGb, Eb, Gb }, NO_PREFIX },
+    { "%NFaddS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
+    { "%NFaddB",		{ VexGb, Gb, EbS }, NO_PREFIX },
+    { "%NFaddS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 08 */
-    { "orB",		{ VexGb, Eb, Gb }, NO_PREFIX },
-    { "orS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
-    { "orB",		{ VexGb, Gb, EbS }, NO_PREFIX },
-    { "orS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
+    { "%NForB",		{ VexGb, Eb, Gb }, NO_PREFIX },
+    { "%NForS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
+    { "%NForB",		{ VexGb, Gb, EbS }, NO_PREFIX },
+    { "%NForS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -911,28 +911,28 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 20 */
-    { "andB",		{ VexGb, Eb, Gb }, NO_PREFIX },
-    { "andS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
-    { "andB",		{ VexGb, Gb, EbS }, NO_PREFIX },
-    { "andS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
-    { "shldS",		{ VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFandB",		{ VexGb, Eb, Gb }, NO_PREFIX },
+    { "%NFandS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
+    { "%NFandB",		{ VexGb, Gb, EbS }, NO_PREFIX },
+    { "%NFandS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
+    { "%NFshldS",		{ VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 28 */
-    { "subB",		{ VexGb, Eb, Gb }, NO_PREFIX },
-    { "subS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
-    { "subB",		{ VexGb, Gb, EbS }, NO_PREFIX },
-    { "subS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
-    { "shrdS",		{ VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFsubB",		{ VexGb, Eb, Gb }, NO_PREFIX },
+    { "%NFsubS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
+    { "%NFsubB",		{ VexGb, Gb, EbS }, NO_PREFIX },
+    { "%NFsubS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
+    { "%NFshrdS",		{ VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 30 */
-    { "xorB",		{ VexGb, Eb, Gb }, NO_PREFIX },
-    { "xorS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
-    { "xorB",		{ VexGb, Gb, EbS }, NO_PREFIX },
-    { "xorS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
+    { "%NFxorB",		{ VexGb, Eb, Gb }, NO_PREFIX },
+    { "%NFxorS",		{ VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
+    { "%NFxorB",		{ VexGb, Gb, EbS }, NO_PREFIX },
+    { "%NFxorS",		{ VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -993,9 +993,9 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     /* 68 */
     { Bad_Opcode },
+    { "%NFimulS",	{ Gv, Ev, Iv }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "%NFimulS",	{ Gv, Ev, sIb }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -1028,7 +1028,7 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 88 */
-    { Bad_Opcode },
+    { "%NFpopcntS",	{ Gv, Ev }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -1060,7 +1060,7 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "shldS",	{ VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
+    { "%NFshldS",	{ VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     /* A8 */
@@ -1069,9 +1069,9 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "shrdS",	{ VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
+    { "%NFshrdS",	{ VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
     { Bad_Opcode },
-    { "imulS",	{ VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFimulS",	{ VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
     /* B0 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -1149,8 +1149,8 @@  static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) },
     { PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "%NFtzcntS",	{ Gv, Ev }, PREFIX_NP_OR_DATA },
+    { "%NFlzcntS",	{ Gv, Ev }, PREFIX_NP_OR_DATA },
     { REG_TABLE (REG_EVEX_MAP4_F6) },
     { REG_TABLE (REG_EVEX_MAP4_F7) },
     /* F8 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 31afa9c9fbc..3686b585bc1 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -162,6 +162,7 @@  struct instr_info
   bool need_modrm;
   unsigned char need_vex;
   bool has_sib;
+  bool has_nf;
 
   /* Flags for ins->prefixes which we somehow handled when printing the
      current instruction.  */
@@ -225,6 +226,7 @@  struct instr_info
     bool zeroing;
     bool b;
     bool no_broadcast;
+    bool nf;
   }
   vex;
 
@@ -1815,6 +1817,8 @@  struct dis386 {
    "XV" => print "{vex} " pseudo prefix
    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
 	   is used by an EVEX-encoded (AVX512VL) instruction.
+   "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1.
+	   a valid encoding.
    "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
    "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
@@ -2619,25 +2623,25 @@  static const struct dis386 reg_table[][8] = {
   },
   /* REG_C0 */
   {
-    { "rolA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "rorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "rclA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "rcrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "shlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "shrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "shlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
-    { "sarA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFrolA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFrorA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFrclA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFrcrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFshlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFshrA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFshlA",	{ VexGb, Eb, Ib }, NO_PREFIX },
+    { "%NFsarA",	{ VexGb, Eb, Ib }, NO_PREFIX },
   },
   /* REG_C1 */
   {
-    { "rolQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "rorQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "rclQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "rcrQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "shlQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "shrQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "shlQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
-    { "sarQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFrolQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFrorQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFrclQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFrcrQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFshlQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFshrQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFshlQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
+    { "%NFsarQ",	{ VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
   },
   /* REG_C6 */
   {
@@ -2663,47 +2667,47 @@  static const struct dis386 reg_table[][8] = {
   },
   /* REG_D0 */
   {
-    { "rolA",	{ VexGb, Eb, I1 }, NO_PREFIX },
-    { "rorA",	{ VexGb, Eb, I1 }, NO_PREFIX },
+    { "%NFrolA",	{ VexGb, Eb, I1 }, NO_PREFIX },
+    { "%NFrorA",	{ VexGb, Eb, I1 }, NO_PREFIX },
     { "rclA",	{ VexGb, Eb, I1 }, NO_PREFIX },
     { "rcrA",	{ VexGb, Eb, I1 }, NO_PREFIX },
-    { "shlA",	{ VexGb, Eb, I1 }, NO_PREFIX },
-    { "shrA",	{ VexGb, Eb, I1 }, NO_PREFIX },
-    { "shlA",	{ VexGb, Eb, I1 }, NO_PREFIX },
-    { "sarA",	{ VexGb, Eb, I1 }, NO_PREFIX },
+    { "%NFshlA",	{ VexGb, Eb, I1 }, NO_PREFIX },
+    { "%NFshrA",	{ VexGb, Eb, I1 }, NO_PREFIX },
+    { "%NFshlA",	{ VexGb, Eb, I1 }, NO_PREFIX },
+    { "%NFsarA",	{ VexGb, Eb, I1 }, NO_PREFIX },
   },
   /* REG_D1 */
   {
-    { "rolQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
-    { "rorQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
+    { "%NFrolQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
+    { "%NFrorQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
     { "rclQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
     { "rcrQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
-    { "shlQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
-    { "shrQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
-    { "shlQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
-    { "sarQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
+    { "%NFshlQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
+    { "%NFshrQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
+    { "%NFshlQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
+    { "%NFsarQ",	{ VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
   },
   /* REG_D2 */
   {
-    { "rolA",	{ VexGb, Eb, CL }, NO_PREFIX },
-    { "rorA",	{ VexGb, Eb, CL }, NO_PREFIX },
+    { "%NFrolA",	{ VexGb, Eb, CL }, NO_PREFIX },
+    { "%NFrorA",	{ VexGb, Eb, CL }, NO_PREFIX },
     { "rclA",	{ VexGb, Eb, CL }, NO_PREFIX },
     { "rcrA",	{ VexGb, Eb, CL }, NO_PREFIX },
-    { "shlA",	{ VexGb, Eb, CL }, NO_PREFIX },
-    { "shrA",	{ VexGb, Eb, CL }, NO_PREFIX },
-    { "shlA",	{ VexGb, Eb, CL }, NO_PREFIX },
-    { "sarA",	{ VexGb, Eb, CL }, NO_PREFIX },
+    { "%NFshlA",	{ VexGb, Eb, CL }, NO_PREFIX },
+    { "%NFshrA",	{ VexGb, Eb, CL }, NO_PREFIX },
+    { "%NFshlA",	{ VexGb, Eb, CL }, NO_PREFIX },
+    { "%NFsarA",	{ VexGb, Eb, CL }, NO_PREFIX },
   },
   /* REG_D3 */
   {
-    { "rolQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
-    { "rorQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
+    { "%NFrolQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
+    { "%NFrorQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
     { "rclQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
     { "rcrQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
-    { "shlQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
-    { "shrQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
-    { "shlQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
-    { "sarQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
+    { "%NFshlQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
+    { "%NFshrQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
+    { "%NFshlQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
+    { "%NFsarQ",	{ VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
   },
   /* REG_F6 */
   {
@@ -2944,9 +2948,9 @@  static const struct dis386 reg_table[][8] = {
   /* REG_VEX_0F38F3_L_0_P_0 */
   {
     { Bad_Opcode },
-    { "blsrS",		{ VexGdq, Edq }, 0 },
-    { "blsmskS",	{ VexGdq, Edq }, 0 },
-    { "blsiS",		{ VexGdq, Edq }, 0 },
+    { "%NFblsrS",		{ VexGdq, Edq }, 0 },
+    { "%NFblsmskS",		{ VexGdq, Edq }, 0 },
+    { "%NFblsiS",		{ VexGdq, Edq }, 0 },
   },
   /* REG_VEX_MAP7_F8_L_0_W_0 */
   {
@@ -4096,7 +4100,7 @@  static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F38F2_L_0 */
   {
-    { "andnS",          { Gdq, VexGdq, Edq }, 0 },
+    { "%NFandnS",          { Gdq, VexGdq, Edq }, 0 },
   },
 
   /* PREFIX_VEX_0F38F3_L_0 */
@@ -4106,7 +4110,7 @@  static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F38F5_L_0 */
   {
-    { "bzhiS",		{ Gdq, Edq, VexGdq }, 0 },
+    { "%NFbzhiS",	{ Gdq, Edq, VexGdq }, 0 },
     { "pextS",		{ Gdq, VexGdq, Edq }, 0 },
     { Bad_Opcode },
     { "pdepS",		{ Gdq, VexGdq, Edq }, 0 },
@@ -4122,7 +4126,7 @@  static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F38F7_L_0 */
   {
-    { "bextrS",		{ Gdq, Edq, VexGdq }, 0 },
+    { "%NFbextrS",	{ Gdq, Edq, VexGdq }, 0 },
     { "sarxS",		{ Gdq, Edq, VexGdq }, 0 },
     { "shlxS",		{ Gdq, Edq, VexGdq }, 0 },
     { "shrxS",		{ Gdq, Edq, VexGdq }, 0 },
@@ -9147,6 +9151,10 @@  get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
       ins->vex.v = *ins->codep & 0x8;
       ins->vex.mask_register_specifier = *ins->codep & 0x7;
       ins->vex.zeroing = *ins->codep & 0x80;
+      /* Set the NF bit for the EVEX instruction extended from the legacy or
+	 vex instruction, this bit will be cleared when it can be confirmed
+	 that its defaut type is evex.  */
+      ins->vex.nf = *ins->codep & 0x4;
 
       if (ins->address_mode != mode_64bit)
 	{
@@ -9600,10 +9608,21 @@  print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
 	  && ins.vex.prefix == DATA_PREFIX_OPCODE)
 	sizeflag ^= DFLAG;
 
+      if(ins.evex_type == evex_default)
+	ins.vex.nf = false;
+      else
+	/* For EVEX-promoted formats, we need to clear EVEX.NF (For ccmp and
+	   ctest, they will be cleared separately.) in mask_register_specifier
+	   and keep the low 2 bits of mask_register_specifier to report errors
+	   for invalid cases.*/
+	ins.vex.mask_register_specifier &= 0x3;
+
       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
 	{
 	  if (!get_sib (&ins, sizeflag))
 	    goto fetch_error_out;
+	  if (!ins.has_nf && ins.vex.nf)
+	    oappend (&ins, "{bad}");
 	  for (i = 0; i < MAX_OPERANDS; ++i)
 	    {
 	      ins.obufp = ins.op_out[i];
@@ -10564,6 +10583,29 @@  putop (instr_info *ins, const char *in_template, int sizeflag)
 	    }
 	  else if (l == 1 && last[0] == 'C')
 	    break;
+	  else if (l == 1 && last[0] == 'N')
+	    {
+	      ins->has_nf = true;
+
+	      if (ins->vex.nf == true)
+		{
+		  *ins->obufp++ = '{';
+		  *ins->obufp++ = 'n';
+		  *ins->obufp++ = 'f';
+		  *ins->obufp++ = '}';
+		  *ins->obufp++ = ' ';
+		}
+	      else if (ins->evex_type == evex_from_legacy && !ins->vex.b)
+		{
+		  *ins->obufp++ = '{';
+		  *ins->obufp++ = 'e';
+		  *ins->obufp++ = 'v';
+		  *ins->obufp++ = 'e';
+		  *ins->obufp++ = 'x';
+		  *ins->obufp++ = '}';
+		  *ins->obufp++ = ' ';
+		}
+	    }
 	  else
 	    abort ();
 	  break;
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0a2c44a9d64..ce54c9d8d26 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1018,6 +1018,7 @@  typedef struct insn_template
 #define Prefix_REX		8	/* {rex} */
 #define Prefix_REX2		9	/* {rex2} */
 #define Prefix_NoOptimize	10	/* {nooptimize} */
+#define Prefix_NF		11	/* {nf} */
 
   /* the bits in opcode_modifier are used to generate the final opcode from
      the base_opcode.  These bits also are used to detect alternate forms of
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1c770e27507..8e0442dfdfd 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -310,32 +310,42 @@  sti, 0xfb, 0, NoSuf, {}
 // Arithmetic.
 add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+add, 0x0, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 add, 0x83/0, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+add, 0x83/0, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 add, 0x80/0, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
 add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+add, 0x80/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
 inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
 inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, }
 sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sub, 0x83/5, APX_F, Modrm|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sub, 0x83/5, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 sub, 0x80/5, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sub, 0x80/5, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
 dec, 0xfe/1, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+dec, 0xfe/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 sbb, 0x18, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sbb, 0x18, APX_F, D|W|CheckOperandSize|Modrm|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sbb, 0x83/3, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sbb, 0x83/3, APX_F, Modrm|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 sbb, 0x80/3, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
@@ -352,44 +362,59 @@  test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16
 
 and, 0x20, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 and, 0x20, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+and, 0x20, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 and, 0x83/4, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+and, 0x83/4, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 and, 0x80/4, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+and, 0x80/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 or, 0x8, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 or, 0x8, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+or, 0x8, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 or, 0x83/1, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+or, 0x83/1, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 or, 0x80/1, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+or, 0x80/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 xor, 0x30, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+xor, 0x30, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 xor, 0x83/6, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+xor, 0x83/6, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 xor, 0x80/6, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+xor, 0x80/6, 0, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 // clr with 1 operand is really xor with 2 operands.
 clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
+clr, 0x30, APX_F, W|Modrm|No_sSuf|RegKludge|EVexMap4, { Reg8|Reg16|Reg32|Reg64 }
 
 adc, 0x10, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 adc, 0x10, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+adc, 0x10, APX_F, D|W|CheckOperandSize|Modrm|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 adc, 0x83/2, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+adc, 0x83/2, APX_F, Modrm|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 adc, 0x80/2, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+adc, 0x80/2, APX_F, W|Modrm|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 neg, 0xf6/3, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+neg, 0xf6/3, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 not, 0xf6/2, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+not, 0xf6/2, APX_F, W|Modrm|No_sSuf|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 aaa, 0x37, No64, NoSuf, {}
 aas, 0x3f, No64, NoSuf, {}
@@ -421,11 +446,16 @@  cqto, 0x99, x64, Size64|NoSuf, {}
 // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
 // These multiplies can only be selected with single operand forms.
 mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+mul, 0xf6/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+imul, 0xf6/5, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 imul, 0xaf, APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
 imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0xaf, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x6b, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x69, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 // imul with 2 operands mimics imul with 3 by putting the register in
 // both i.rm.reg & i.rm.regmem fields.  RegKludge enables this
 // transformation.
@@ -434,24 +464,34 @@  imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|R
 
 div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 div, 0xf6/6, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+div, 0xf6/6, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+idiv, 0xf6/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 rcl, 0xd0/2, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
@@ -479,49 +519,71 @@  rcr, 0xd0/3, APX_F, W|Modrm|No_sSuf|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecifi
 
 sal, 0xd0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sal, 0xd0/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sal, 0xc0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sal, 0xc0/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sal, 0xd2/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sal, 0xd2/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sal, 0xd0/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 shl, 0xd0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shl, 0xd0/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shl, 0xc0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shl, 0xc0/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shl, 0xd2/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shl, 0xd2/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shl, 0xd0/4, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 shr, 0xd0/5, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shr, 0xd0/5, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shr, 0xc0/5, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shr, 0xc0/5, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shr, 0xd2/5, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shr, 0xd2/5, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shr, 0xd0/5, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 sar, 0xd0/7, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sar, 0xd0/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sar, 0xc0/7, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sar, 0xc0/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sar, 0xd2/7, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sar, 0xd2/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+sar, 0xd0/7, APX_F, W|Modrm|No_sSuf|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 shld, 0x24, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 shld, 0xfa4, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shld, 0x24, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shld, 0xa5, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shld, 0xa5, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shld, 0xa5, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shld, 0xa5, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 shrd, 0x2c, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 shrd, 0xfac, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shrd, 0x2c, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shrd, 0xad, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shrd, 0xad, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 shrd, 0xad, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+shrd, 0xad, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 // Control transfer instructions.
 call, 0xe8, No64, JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
@@ -979,7 +1041,8 @@  rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {}
 <pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:No64, disp32:Disp32:i386, +
                       load:Load:0, store:Store:0, +
                       vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, +
-                      rex:REX:x64, rex2:REX2:APX_F, nooptimize:NoOptimize:0>
+                      rex:REX:x64, rex2:REX2:APX_F, nf:NF:APX_F, +
+                      nooptimize:NoOptimize:0>
 
 {<pseudopfx>}, PSEUDO_PREFIX/Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, NoSuf|IsPrefix, {}
 
@@ -2027,6 +2090,7 @@  blsi, 0xf3/3, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVV
 blsmsk, 0xf3/2, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
 blsr, 0xf3/1, APX_F(BMI), Modrm|CheckOperandSize|Vex128|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf|NF, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
 tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+tzcnt, 0xf4, BMI&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 
 // TBM instructions
 
@@ -2104,9 +2168,11 @@  insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM }
 
 // LZCNT instruction
 lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lzcnt, 0xf5, LZCNT|APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 
 // POPCNT instruction
 popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+popcnt, 0x88, POPCNT|APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 
 // VIA PadLock extensions.
 xstore-rng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}