[2/2] LoongArch: update test cases about TLS

Message ID 20240127131211.795952-2-cailulu@loongson.cn
State New
Headers
Series [1/2] LoongArch: Fix incorrect type transition under extreme cmodel |

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Commit Message

Lulu Cai Jan. 27, 2024, 1:12 p.m. UTC
  ---
 gas/testsuite/gas/loongarch/macro_op.d        |  2 ++
 gas/testsuite/gas/loongarch/macro_op_32.d     |  2 ++
 .../gas/loongarch/macro_op_extreme_abs.d      |  2 --
 gas/testsuite/gas/loongarch/tlsdesc_32.d      |  2 ++
 gas/testsuite/gas/loongarch/tlsdesc_32.s      |  2 +-
 gas/testsuite/gas/loongarch/tlsdesc_64.d      |  2 ++
 gas/testsuite/gas/loongarch/tlsdesc_64.s      |  2 +-
 ld/testsuite/ld-loongarch-elf/desc-ie.d       | 29 ++++++++++++++-----
 ld/testsuite/ld-loongarch-elf/desc-ie.s       | 11 ++++---
 ld/testsuite/ld-loongarch-elf/desc-le.d       | 19 ++++++++----
 ld/testsuite/ld-loongarch-elf/desc-le.s       |  8 ++---
 ld/testsuite/ld-loongarch-elf/ie-le.d         | 13 ++++++---
 ld/testsuite/ld-loongarch-elf/ie-le.s         |  7 +++--
 ld/testsuite/ld-loongarch-elf/macro_op.d      |  2 ++
 ld/testsuite/ld-loongarch-elf/macro_op_32.d   |  2 ++
 15 files changed, 70 insertions(+), 35 deletions(-)
  

Patch

diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 47f8f45c663..9d696437a28 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -57,8 +57,10 @@  Disassembly of section .text:
 			4c: R_LARCH_TLS_LE_LO12	TLS1
   50:	1a000004 	pcalau12i   	\$a0, 0
 			50: R_LARCH_TLS_IE_PC_HI20	TLS1
+			50: R_LARCH_RELAX	\*ABS\*
   54:	28c00084 	ld.d        	\$a0, \$a0, 0
 			54: R_LARCH_TLS_IE_PC_LO12	TLS1
+			54: R_LARCH_RELAX	\*ABS\*
   58:	1a000004 	pcalau12i   	\$a0, 0
 			58: R_LARCH_TLS_LD_PC_HI20	TLS1
 			58: R_LARCH_RELAX	\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index a7349aa8dc0..f8aaacda345 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -53,8 +53,10 @@  Disassembly of section .text:
 			44: R_LARCH_TLS_LE_LO12	TLS1
   48:	1a000004 	pcalau12i   	\$a0, 0
 			48: R_LARCH_TLS_IE_PC_HI20	TLS1
+			48: R_LARCH_RELAX	\*ABS\*
   4c:	28800084 	ld.w        	\$a0, \$a0, 0
 			4c: R_LARCH_TLS_IE_PC_LO12	TLS1
+			4c: R_LARCH_RELAX	\*ABS\*
   50:	1a000004 	pcalau12i   	\$a0, 0
 			50: R_LARCH_TLS_LD_PC_HI20	TLS1
 			50: R_LARCH_RELAX	\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
index 5c823ba0302..6a81e82e93e 100644
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
@@ -28,10 +28,8 @@  Disassembly of section .text:
 			1c: R_LARCH_ABS64_HI12	.L1
   20:	1a000004 	pcalau12i   	\$a0, 0
 			20: R_LARCH_PCALA_HI20	.L1
-			20: R_LARCH_RELAX	\*ABS\*
   24:	02c00084 	addi.d      	\$a0, \$a0, 0
 			24: R_LARCH_PCALA_LO12	.L1
-			24: R_LARCH_RELAX	\*ABS\*
   28:	14000004 	lu12i.w     	\$a0, 0
 			28: R_LARCH_GOT_HI20	.L1
   2c:	03800084 	ori         	\$a0, \$a0, 0x0
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d
index eddcc5ed0e8..6c9558d7454 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_32.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.d
@@ -23,5 +23,7 @@  Disassembly of section .text:
 			14: R_LARCH_RELAX	\*ABS\*
   18:	28800081 	ld.w        	\$ra, \$a0, 0
 			18: R_LARCH_TLS_DESC_LD	var
+			18: R_LARCH_RELAX	\*ABS\*
   1c:	4c000021 	jirl        	\$ra, \$ra, 0
 			1c: R_LARCH_TLS_DESC_CALL	var
+			1c: R_LARCH_RELAX	\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s
index 2a139c041b1..2180146a41d 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_32.s
+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s
@@ -8,5 +8,5 @@ 
 	# R_LARCH_TLS_DESC_CALL var
 	jirl    $ra,$ra,%desc_call(var)
 
-	# test macro, pcalau12i + addi.w => pcaddi
+	# with R_LARCH_RELAX
 	la.tls.desc	$a0,var
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d
index 2a2829c9b44..8fc9e883a4a 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_64.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d
@@ -24,5 +24,7 @@  Disassembly of section .text:
 			14: R_LARCH_RELAX	\*ABS\*
   18:	28c00081 	ld.d        	\$ra, \$a0, 0
 			18: R_LARCH_TLS_DESC_LD	var
+			18: R_LARCH_RELAX	\*ABS\*
   1c:	4c000021 	jirl        	\$ra, \$ra, 0
 			1c: R_LARCH_TLS_DESC_CALL	var
+			1c: R_LARCH_RELAX	\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s
index 9850940ef93..d63b17261db 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_64.s
+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s
@@ -8,5 +8,5 @@ 
 	# R_LARCH_TLS_DESC_CALL var
 	jirl    $ra,$ra,%desc_call(var)
 
-	# test macro, pcalau12i + addi.d => pcaddi
+	# with R_LARCH_RELAX
 	la.tls.desc	$a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d
index 32e350507db..8b184a6da38 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d
@@ -1,16 +1,29 @@ 
 #as:
-#ld: -shared -z norelro -e 0x0 --hash-style=both
+#ld: -shared -z norelro -e0 --hash-style=both
 #objdump: -dr
 #skip: loongarch32-*-*
 
 .*:     file format .*
 
+
 Disassembly of section .text:
 
-0+230 <fn1>:
- 230:	1a000084 	pcalau12i   	\$a0, 4
- 234:	28cd6084 	ld.d        	\$a0, \$a0, 856
- 238:	03400000 	nop.*
- 23c:	03400000 	nop.*
- 240:	1a000084 	pcalau12i   	\$a0, 4
- 244:	28cd6081 	ld.d        	\$ra, \$a0, 856
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+:	1a000084 	pcalau12i   	\$a0, .*
+ +[0-9a-f]+:	28ce2084 	ld.d        	\$a0, \$a0, .*
+ +[0-9a-f]+:	03400000 	nop
+ +[0-9a-f]+:	03400000 	nop
+ +[0-9a-f]+:	1a000084 	pcalau12i   	\$a0, .*
+ +[0-9a-f]+:	28ce2084 	ld.d        	\$a0, \$a0, .*
+ +[0-9a-f]+:	1a000084 	pcalau12i   	\$a0, .*
+ +[0-9a-f]+:	02ce2005 	li.d        	\$a1, .*
+ +[0-9a-f]+:	16000005 	lu32i.d     	\$a1, 0
+ +[0-9a-f]+:	030000a5 	lu52i.d     	\$a1, \$a1, .*
+ +[0-9a-f]+:	00109484 	add.d       	\$a0, \$a0, \$a1
+ +[0-9a-f]+:	28c00081 	ld.d        	\$ra, \$a0, 0
+ +[0-9a-f]+:	4c000021 	jirl        	\$ra, \$ra, 0
+ +[0-9a-f]+:	1a000084 	pcalau12i   	\$a0, .*
+ +[0-9a-f]+:	02ce2005 	li.d        	\$a1, .*
+ +[0-9a-f]+:	16000005 	lu32i.d     	\$a1, .*
+ +[0-9a-f]+:	030000a5 	lu52i.d     	\$a1, \$a1, .*
+ +[0-9a-f]+:	380c1484 	ldx.d       	\$a0, \$a0, \$a1
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s
index 7f5772bcf23..e85a16d5fcb 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s
@@ -9,10 +9,9 @@  fn1:
 
 	# Use DESC and IE to access the same symbol,
 	# DESC will relax to IE.
-	pcalau12i       $a0,%desc_pc_hi20(var)
-	addi.d  $a0,$a0,%desc_pc_lo12(var)
-	ld.d    $ra,$a0,%desc_ld(var)
-	jirl    $ra,$ra,%desc_call(var)
+	la.tls.desc $a0,var
+	la.tls.ie   $a0,var
 
-	pcalau12i       $a0,%ie_pc_hi20(var)
-	ld.d		$ra,$a0,%ie_pc_lo12(var)
+	# extreme cmodel do not do transition.
+	la.tls.desc $a0,$a1,var
+	la.tls.ie   $a0,$a1,var
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d
index b4ca9f82eb3..688701f7fee 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-le.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-le.d
@@ -1,5 +1,5 @@ 
 #as:
-#ld: -z norelro -e 0x0
+#ld: -z norelro -e0
 #objdump: -dr
 #skip: loongarch32-*-*
 
@@ -8,8 +8,15 @@ 
 
 Disassembly of section .text:
 
-0+1200000e8 <fn1>:
-   1200000e8:	14000004 	lu12i.w     	\$a0, 0
-   1200000ec:	03800084 	ori         	\$a0, \$a0, 0x0
-   1200000f0:	03400000 	nop.*
-   1200000f4:	03400000 	nop.*
+[0-9a-f]+ <fn1>:
+   +[0-9a-f]+:	14000004 	lu12i.w     	\$a0, .*
+   +[0-9a-f]+:	03800084 	ori         	\$a0, \$a0, .*
+   +[0-9a-f]+:	03400000 	nop
+   +[0-9a-f]+:	03400000 	nop
+   +[0-9a-f]+:	1a000084 	pcalau12i   	\$a0, .*
+   +[0-9a-f]+:	02c4e005 	li.d        	\$a1, .*
+   +[0-9a-f]+:	16000005 	lu32i.d     	\$a1, .*
+   +[0-9a-f]+:	030000a5 	lu52i.d     	\$a1, \$a1, .*
+   +[0-9a-f]+:	00109484 	add.d       	\$a0, \$a0, \$a1
+   +[0-9a-f]+:	28c00081 	ld.d        	\$ra, \$a0, 0
+   +[0-9a-f]+:	4c000021 	jirl        	\$ra, \$ra, 0
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s
index 9ffaa2d668d..de6ab41f3eb 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-le.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-le.s
@@ -8,7 +8,7 @@  var:
 fn1:
 
 	# DESC will relax to LE.
-	pcalau12i       $a0,%desc_pc_hi20(var)
-	addi.d  $a0,$a0,%desc_pc_lo12(var)
-	ld.d    $ra,$a0,%desc_ld(var)
-	jirl    $ra,$ra,%desc_call(var)
+	la.tls.desc $a0,var
+
+	# extreme cmodel do not do transition.
+	la.tls.desc $a0,$a1,var
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d
index 42694d7f9f0..28f3a660a2e 100644
--- a/ld/testsuite/ld-loongarch-elf/ie-le.d
+++ b/ld/testsuite/ld-loongarch-elf/ie-le.d
@@ -1,5 +1,5 @@ 
 #as:
-#ld: -z norelro -e 0x0
+#ld: -z norelro -e0
 #objdump: -dr
 #skip: loongarch32-*-*
 
@@ -8,6 +8,11 @@ 
 
 Disassembly of section .text:
 
-0+1200000e8 <fn1>:
-   1200000e8:	14000004 	lu12i.w     	\$a0, 0
-   1200000ec:	03800084 	ori         	\$a0, \$a0, 0x0
+[0-9a-f]+ <fn1>:
+   +[0-9a-f]+:	14000004 	lu12i.w     	\$a0, .*
+   +[0-9a-f]+:	03800084 	ori         	\$a0, \$a0, .*
+   +[0-9a-f]+:	1a000084 	pcalau12i   	\$a0, .*
+   +[0-9a-f]+:	02c44005 	li.d        	\$a1, .*
+   +[0-9a-f]+:	16000005 	lu32i.d     	\$a1, .*
+   +[0-9a-f]+:	030000a5 	lu52i.d     	\$a1, \$a1, .*
+   +[0-9a-f]+:	380c1484 	ldx.d       	\$a0, \$a0, \$a1
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le.s
index 795c7ce49cf..e582a2de528 100644
--- a/ld/testsuite/ld-loongarch-elf/ie-le.s
+++ b/ld/testsuite/ld-loongarch-elf/ie-le.s
@@ -6,6 +6,7 @@  var:
 	.global	fn1
 	.type	gn1,@function
 fn1:
-	# expect IE to relax LE.
-	pcalau12i       $a0,%ie_pc_hi20(var)
-	ld.d    	$a0,$a0,%ie_pc_lo12(var)
+	# expect IE to relax LE in nomal cmodel.
+	la.tls.ie	$a0,var
+	# extreme cmodel do not do transition.
+	la.tls.ie	$a0,$a1,var
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index c9493918a93..46b849a9c33 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -144,8 +144,10 @@  Disassembly of section .text:
 [ 	]+f8: R_LARCH_TLS_LE_LO12[ 	]+TLS1
 [ 	]+fc:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0, 0
 [ 	]+fc: R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
+[ 	]+fc: R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+100:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0, \$a0, 0
 [ 	]+100: R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
+[ 	]+100: R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+104:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0, 0
 [ 	]+104: R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
 [ 	]+108:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1, 0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index a7349aa8dc0..f8aaacda345 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -53,8 +53,10 @@  Disassembly of section .text:
 			44: R_LARCH_TLS_LE_LO12	TLS1
   48:	1a000004 	pcalau12i   	\$a0, 0
 			48: R_LARCH_TLS_IE_PC_HI20	TLS1
+			48: R_LARCH_RELAX	\*ABS\*
   4c:	28800084 	ld.w        	\$a0, \$a0, 0
 			4c: R_LARCH_TLS_IE_PC_LO12	TLS1
+			4c: R_LARCH_RELAX	\*ABS\*
   50:	1a000004 	pcalau12i   	\$a0, 0
 			50: R_LARCH_TLS_LD_PC_HI20	TLS1
 			50: R_LARCH_RELAX	\*ABS\*