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Wed, 3 Jan 2024 01:17:42 +0000 From: Victor Do Nascimento To: CC: , , Victor Do Nascimento Subject: [PATCH 01/12] aarch64: Add +d128 architectural feature support Date: Wed, 3 Jan 2024 01:17:15 +0000 Message-ID: <20240103011739.2444792-2-victor.donascimento@arm.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240103011739.2444792-1-victor.donascimento@arm.com> References: <20240103011739.2444792-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00025F99:EE_|GV2PR08MB8170:EE_|DB1PEPF00039230:EE_|AM9PR08MB6721:EE_ X-MS-Office365-Filtering-Correlation-Id: 29778507-7b7a-47ea-a87f-08dc0bf9d1ba X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: s4B9x3+/9zzonT9UPLmluQzR9PcOuryXKuWTGvTxalUxHxgumxQE/SSGJiUWar601Yw8Hfs73Bk68nD3MEcYG0hoJs307873ag3Bu7bMvEOHG248/JoNs1fBi2GIdsLaMEKgwq7XMHUMqWsuNgcG14zxbliT3aqde5yqMJi7Eegjp4jKGNV3/vH7UPEE3Ogochq1iAViaRc30uiWpS9AIyJbeQoD8eEcgfll03qT/aCm64DaY3A3Qp6sK3ebGydmaJKdEwxo0Rd7sHAeXK6ApfgvYeYL/PYqnluu+lx4chOlROj//AZ6Z4Lro0txvLkyLN2huOHP7qOWY6EnCc+1f57R4YPsd6ggRG4/NBI0XT72hBBBl86ldXH95sy/HsUohn5f1Z9Mo/WL7g8vvBELWO+9yMhvpXUdIzz3qdwFusKS3I1PTfnZMrMokzi/dU4gOJ5H38/sCjKEnUCdITeJl/iPn26wSS6JGf22DC8PecDAxLR5VDniXnzgvbASyRP2/7tluXfL8EAMBNLJrAFTvnsGJQFm3b1gSYsg6ZtFeM31ShyX75uuocIO0RLWspxoFgiQaK440Qi4HoWwKuyr4prrkxsu+IRQMncMYcTQRaBfsUg57F/W2AofUVI72QXBuzlb+bRTDIKtRwIxLF5dj9ECshRSIGMChzNuUh0BYWyj1ihFriKjRRzHLKvPi16FGRgvZLhHwV9DhkAYDJM0F51KYQi77U+epiHm9PqrJcGTSyP2KEJgNOC28v/2amUd1/88GrEYBmFcm634gTbSsg== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF00039230.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6721 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Indicating the presence of the Armv9.4-a features concerning 128-bit Page Table Descriptors, 128-bit System Registers and Instructions, the "+d128" architectural extension flag is added to the list of possible -march options in Binutils, together with the necessary macro for encoding d128 instructions. --- gas/config/tc-aarch64.c | 2 ++ gas/doc/c-aarch64.texi | 2 ++ include/opcode/aarch64.h | 3 +++ opcodes/aarch64-tbl.h | 5 +++++ 4 files changed, 12 insertions(+) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c10d8201f5e..bfe91c90139 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10297,6 +10297,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"the", AARCH64_FEATURE (THE), AARCH64_NO_FEATURES}, {"rasv2", AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)}, {"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES}, + {"d128", AARCH64_FEATURE (D128), + AARCH64_FEATURE (LSE128)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 209d20fa832..7383343d167 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -274,6 +274,8 @@ automatically cause those extensions to be disabled. @tab Enable Prediction instructions. @item @code{ite} @tab N/A @tab no @tab Enable TRCIT instruction. +@item @code{d128} @tab Armv9.4-A @tab No + @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}. @end multitable @node AArch64 Syntax diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 1da337aaa58..9fc7643ffa1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -201,6 +201,9 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PREDRES2, /* Instrumentation Extension. */ AARCH64_FEATURE_ITE, + /* 128-bit page table descriptor, system registers + and isntructions. */ + AARCH64_FEATURE_D128, AARCH64_NUM_FEATURES }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5dd0864c0ab..3be6daeb3b0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_gcs = AARCH64_FEATURE (GCS); static const aarch64_feature_set aarch64_feature_ite = AARCH64_FEATURE (ITE); +static const aarch64_feature_set aarch64_feature_d128 = + AARCH64_FEATURE (D128); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_ite = #define CHK &aarch64_feature_chk #define GCS &aarch64_feature_gcs #define ITE &aarch64_feature_ite +#define D128 &aarch64_feature_d128 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2798,6 +2801,8 @@ static const aarch64_feature_set aarch64_feature_ite = { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } #define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } +#define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \