From patchwork Thu Dec 7 03:12:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 81572 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5E9213857400 for ; Thu, 7 Dec 2023 03:13:11 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id 9B96538582BD for ; Thu, 7 Dec 2023 03:12:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9B96538582BD Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9B96538582BD Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=207.46.229.174 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701918777; cv=none; b=MgWz4neiA8etuQ9wdN/7AL4ydgs3f7tFe/p2wW9mBMjL8wbuz41QlVAvH1LCLtKKF+PDnFl8Zpo+czZHYHq5gKY4AyxJq/9LmZ43C1Lng54Om5aDk8WUhz/8anyQFq1FNWBK9uKl2uSaGYJnT2ZJvKGs40qrjhLHpJI413kh/rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701918777; c=relaxed/simple; bh=r4JWNBETfM2W5I4YRZlZT6nv+Z1PE3cPpdegR6ocEIY=; h=From:To:Subject:Date:Message-Id; b=JVWZHyqukaP5ZBD1B6d+NchDKTESSuVHW2XNWqsWuAwUxF+PSdYGzuwBZOs3RONN6VfDc9z1AzUZGg/ONMhzP7SY/MhkrdJ64oV8XE0OKS9oi/SJFg2lwWsttV0rp+4+8fKISieVhk7BB/CuF+7SnZlKorASlTYqZTBmEeHdr7o= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgBHxvvuN3FlVogAAA--.1351S4; Thu, 07 Dec 2023 11:11:42 +0800 (CST) From: Xiao Zeng To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, nelson@rivosinc.com, Xiao Zeng Subject: [PING^1][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' Date: Thu, 7 Dec 2023 11:12:03 +0800 Message-Id: <20231207031203.14734-1-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TAJkCgBHxvvuN3FlVogAAA--.1351S4 X-Coremail-Antispam: 1UD129KBjvJXoWxZw4fWFWrWF4kCr48JFWUurg_yoWrWF18pF WruFy0krWrXF17tanrGry7X3W7Ww1rur909r40y3W2yr4ft39rJr1ktw1FyF43XF4DCwn3 Zw4fXrW3ZFyYgF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org This commit adds support for ratified extensions: 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'. This is based on: bfd/ChangeLog: * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'. (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list. gas/ChangeLog: * testsuite/gas/riscv/attribute-15.d: New test. * testsuite/gas/riscv/attribute-15.s: New test. * testsuite/gas/riscv/attribute-16.d: New test. * testsuite/gas/riscv/attribute-16.s: New test. --- bfd/elfxx-riscv.c | 4 ++++ gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++ gas/testsuite/gas/riscv/attribute-15.s | 1 + gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++ gas/testsuite/gas/riscv/attribute-16.s | 1 + 5 files changed, 18 insertions(+) create mode 100644 gas/testsuite/gas/riscv/attribute-15.d create mode 100644 gas/testsuite/gas/riscv/attribute-15.s create mode 100644 gas/testsuite/gas/riscv/attribute-16.d create mode 100644 gas/testsuite/gas/riscv/attribute-16.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 567631e7d96..4c91081acd1 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvl256b", "zvl128b", check_implicit_always}, {"zvl128b", "zvl64b", check_implicit_always}, {"zvl64b", "zvl32b", check_implicit_always}, + {"zicntr", "zicsr", check_implicit_always}, + {"zihpm", "zicsr", check_implicit_always}, {"zcd", "d", check_implicit_always}, {"zcf", "f", check_implicit_always}, {"zfa", "f", check_implicit_always}, @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d new file mode 100644 index 00000000000..a17e82c8508 --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-15.d @@ -0,0 +1,6 @@ +#as: -march-attr -misa-spec=20191213 +#readelf: -A +#source: attribute-15.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0" diff --git a/gas/testsuite/gas/riscv/attribute-15.s b/gas/testsuite/gas/riscv/attribute-15.s new file mode 100644 index 00000000000..ecb10a298fd --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-15.s @@ -0,0 +1 @@ + .attribute arch,"rv32i_zicntr_zihpm" diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d new file mode 100644 index 00000000000..6ca3b5351f8 --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-16.d @@ -0,0 +1,6 @@ +#as: -march-attr -misa-spec=20191213 +#readelf: -A +#source: attribute-16.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0" diff --git a/gas/testsuite/gas/riscv/attribute-16.s b/gas/testsuite/gas/riscv/attribute-16.s new file mode 100644 index 00000000000..8757bb5181b --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-16.s @@ -0,0 +1 @@ + .attribute arch,"rv64i_zicntr_zihpm"