diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9acf124626..1f04ac6d9be 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1374,6 +1374,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadmempair",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadv",    ISA_SPEC_CLASS_DRAFT, 0, 7, 1},
   {NULL, 0, 0, 0, 0}
 };
 
@@ -1994,7 +1995,8 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
 	  && strncmp (s->name, "zve", 3) == 0)
 	support_zve = true;
       if (!support_zvl
-	  && strncmp (s->name, "zvl", 3) == 0)
+	  && strncmp (s->name, "zvl", 3) == 0
+    && strncmp (s->name, "zvls", 4) != 0)
 	support_zvl = true;
       if (support_zve && support_zvl)
 	break;
@@ -2514,14 +2516,19 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZKSH:
       return riscv_subset_supports (rps, "zksh");
     case INSN_CLASS_V:
-      return (riscv_subset_supports (rps, "v")
+      return ((riscv_subset_supports (rps, "v")
 	      || riscv_subset_supports (rps, "zve64x")
-	      || riscv_subset_supports (rps, "zve32x"));
+	      || riscv_subset_supports (rps, "zve32x"))
+	      && !riscv_subset_supports (rps, "zvamo"));
     case INSN_CLASS_ZVEF:
       return (riscv_subset_supports (rps, "v")
 	      || riscv_subset_supports (rps, "zve64d")
 	      || riscv_subset_supports (rps, "zve64f")
 	      || riscv_subset_supports (rps, "zve32f"));
+    case INSN_CLASS_V_OR_XTHEADV:
+    case INSN_CLASS_ZVEF_OR_XTHEADV:
+      return riscv_subset_supports (rps, "v")
+        || riscv_subset_supports(rps, "xtheadv");
     case INSN_CLASS_ZVBB:
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
@@ -2556,6 +2563,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmac");
     case INSN_CLASS_XCVALU:
       return riscv_subset_supports (rps, "xcvalu");
+    case INSN_CLASS_XTHEADV:
+      return riscv_subset_supports(rps, "xtheadv");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2768,8 +2777,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zksh";
     case INSN_CLASS_V:
       return _("v' or `zve64x' or `zve32x");
+    case INSN_CLASS_XTHEADV:
+      return _("v' or `zvlsseg' or `zvamo");
     case INSN_CLASS_ZVEF:
-      return _("v' or `zve64d' or `zve64f' or `zve32f");
+      return _("v");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
     case INSN_CLASS_ZVBC:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 402c46ad753..d1752eacc08 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2298,56 +2298,104 @@ my_getVsetvliExpression (expressionS *ep, char *str)
 {
   unsigned int vsew_value = 0, vlmul_value = 0;
   unsigned int vta_value = 0, vma_value = 0;
+  unsigned int vlen_value = 0, vediv_value = 0; /* RVV 0.7. */
   bfd_boolean vsew_found = FALSE, vlmul_found = FALSE;
   bfd_boolean vta_found = FALSE, vma_found = FALSE;
+  bfd_boolean vlen_found = FALSE, vediv_found = FALSE; /* RVV 0.7. */
 
-  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
+  if(riscv_subset_supports (&riscv_rps_as, "zve32x"))
+  {
+    if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
     {
       if (*str == ',')
-	++str;
+		++str;
       if (vsew_found)
-	as_bad (_("multiple vsew constants"));
+		as_bad (_("multiple vsew constants"));
       vsew_found = TRUE;
     }
-  if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
+    if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
     {
       if (*str == ',')
-	++str;
+		++str;
       if (vlmul_found)
-	as_bad (_("multiple vlmul constants"));
-      vlmul_found = TRUE;
+		as_bad (_("multiple vlmul constants"));
+      vlmul_found = TRUE;	
     }
-  if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
+    if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
     {
       if (*str == ',')
-	++str;
+		++str;
       if (vta_found)
-	as_bad (_("multiple vta constants"));
-      vta_found = TRUE;
+		as_bad (_("multiple vta constants"));
+      	vta_found = TRUE;
     }
-  if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
+    if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
     {
       if (*str == ',')
-	++str;
+		++str;
       if (vma_found)
-	as_bad (_("multiple vma constants"));
+		as_bad (_("multiple vma constants"));
       vma_found = TRUE;
     }
 
-  if (vsew_found || vlmul_found || vta_found || vma_found)
+    if (vsew_found || vlmul_found || vta_found || vma_found)
     {
       ep->X_op = O_constant;
       ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
-			 | (vsew_value << OP_SH_VSEW)
-			 | (vta_value << OP_SH_VTA)
-			 | (vma_value << OP_SH_VMA);
+	      | (vsew_value << OP_SH_VSEW)
+	      | (vta_value << OP_SH_VTA)
+	      | (vma_value << OP_SH_VMA);
       expr_parse_end = str;
     }
+    else
+    {
+      my_getExpression (ep, str);
+      str = expr_parse_end;
+    }
+  }
   else
+  {
+    /* RVV 0.7. */
+    if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vsew_found)
+	as_bad (_("multiple vsew constants"));
+      vsew_found = TRUE;
+    }
+
+    if (arg_lookup (&str, riscv_vlen, ARRAY_SIZE (riscv_vlen), &vlen_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vlen_found)
+	as_bad (_("multiple vlen constants"));
+      vlen_found = TRUE;
+    }
+    if (arg_lookup (&str, riscv_vediv, ARRAY_SIZE (riscv_vediv), &vediv_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vediv_found)
+	as_bad (_("multiple vediv constants"));
+      vediv_found = TRUE;
+    }
+
+    if (vsew_found || vlmul_found || vta_found || vma_found)
+    {
+      ep->X_op = O_constant;
+      ep->X_add_number = (vediv_value << 5)
+	      | (vsew_value << 2)
+	      | (vlen_value);
+      expr_parse_end = str;
+    }
+    else
     {
       my_getExpression (ep, str);
       str = expr_parse_end;
     }
+  }
 }
 
 /* Detect and handle implicitly zero load-store offsets.  For example,
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24217062edc..496f4703f3d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2121,6 +2121,404 @@
 #define MASK_VDOTUVV  0xfc00707f
 #define MATCH_VFDOTVV  0xe4001057
 #define MASK_VFDOTVV  0xfc00707f
+/* XTHEADV  */
+#define MATCH_VLBV  0x10000007
+#define MASK_VLBV   0xfdf0707f
+#define MATCH_VLHV  0x10005007
+#define MASK_VLHV   0xfdf0707f
+#define MATCH_VLWV  0x10006007
+#define MASK_VLWV   0xfdf0707f
+
+#define MATCH_VLSBV    0x18000007
+#define MASK_VLSBV     0xfc00707f
+#define MATCH_VLSHV    0x18005007
+#define MASK_VLSHV     0xfc00707f
+#define MATCH_VLSWV    0x18006007
+#define MASK_VLSWV     0xfc00707f
+
+#define MATCH_VLXBV    0x1c000007
+#define MASK_VLXBV     0xfc00707f
+#define MATCH_VLXHV    0x1c005007
+#define MASK_VLXHV     0xfc00707f
+#define MATCH_VLXWV    0x1c006007
+#define MASK_VLXWV     0xfc00707f
+#define MATCH_VSUXBV   0x1c000027
+#define MASK_VSUXBV    0xfc00707f
+#define MATCH_VSUXHV   0x1c005027
+#define MASK_VSUXHV    0xfc00707f
+#define MATCH_VSUXWV   0x1c006027
+#define MASK_VSUXWV    0xfc00707f
+#define MATCH_VSUXEV   0x1c007027
+#define MASK_VSUXEV    0xfc00707f
+
+#define MATCH_VLBFFV  0x11000007
+#define MASK_VLBFFV   0xfdf0707f
+#define MATCH_VLHFFV  0x11005007
+#define MASK_VLHFFV   0xfdf0707f
+#define MATCH_VLWFFV  0x11006007
+#define MASK_VLWFFV   0xfdf0707f
+
+#define MATCH_VLSEG2BV  0x30000007
+#define MASK_VLSEG2BV   0xfdf0707f
+#define MATCH_VLSEG2HV  0x30005007
+#define MASK_VLSEG2HV   0xfdf0707f
+#define MATCH_VLSEG2WV  0x30006007
+#define MASK_VLSEG2WV   0xfdf0707f
+
+#define MATCH_VLSEG3BV  0x50000007
+#define MASK_VLSEG3BV   0xfdf0707f
+#define MATCH_VLSEG3HV  0x50005007
+#define MASK_VLSEG3HV   0xfdf0707f
+#define MATCH_VLSEG3WV  0x50006007
+#define MASK_VLSEG3WV   0xfdf0707f
+
+#define MATCH_VLSEG4BV  0x70000007
+#define MASK_VLSEG4BV   0xfdf0707f
+#define MATCH_VLSEG4HV  0x70005007
+#define MASK_VLSEG4HV   0xfdf0707f
+#define MATCH_VLSEG4WV  0x70006007
+#define MASK_VLSEG4WV   0xfdf0707f
+
+#define MATCH_VLSEG5BV  0x90000007
+#define MASK_VLSEG5BV   0xfdf0707f
+#define MATCH_VLSEG5HV  0x90005007
+#define MASK_VLSEG5HV   0xfdf0707f
+#define MATCH_VLSEG5WV  0x90006007
+#define MASK_VLSEG5WV   0xfdf0707f
+
+#define MATCH_VLSEG6BV  0xb0000007
+#define MASK_VLSEG6BV   0xfdf0707f
+#define MATCH_VLSEG6HV  0xb0005007
+#define MASK_VLSEG6HV   0xfdf0707f
+#define MATCH_VLSEG6WV  0xb0006007
+#define MASK_VLSEG6WV   0xfdf0707f
+
+#define MATCH_VLSEG7BV  0xd0000007
+#define MASK_VLSEG7BV   0xfdf0707f
+#define MATCH_VLSEG7HV  0xd0005007
+#define MASK_VLSEG7HV   0xfdf0707f
+#define MATCH_VLSEG7WV  0xd0006007
+#define MASK_VLSEG7WV   0xfdf0707f
+
+#define MATCH_VLSEG8BV  0xf0000007
+#define MASK_VLSEG8BV   0xfdf0707f
+#define MATCH_VLSEG8HV  0xf0005007
+#define MASK_VLSEG8HV   0xfdf0707f
+#define MATCH_VLSEG8WV  0xf0006007
+#define MASK_VLSEG8WV   0xfdf0707f
+
+#define MATCH_VLSSEG2BV  0x38000007
+#define MASK_VLSSEG2BV   0xfc00707f
+#define MATCH_VLSSEG2HV  0x38005007
+#define MASK_VLSSEG2HV   0xfc00707f
+#define MATCH_VLSSEG2WV  0x38006007
+#define MASK_VLSSEG2WV   0xfc00707f
+
+#define MATCH_VLSSEG3BV  0x58000007
+#define MASK_VLSSEG3BV   0xfc00707f
+#define MATCH_VLSSEG3HV  0x58005007
+#define MASK_VLSSEG3HV   0xfc00707f
+#define MATCH_VLSSEG3WV  0x58006007
+#define MASK_VLSSEG3WV   0xfc00707f
+
+#define MATCH_VLSSEG4BV  0x78000007
+#define MASK_VLSSEG4BV   0xfc00707f
+#define MATCH_VLSSEG4HV  0x78005007
+#define MASK_VLSSEG4HV   0xfc00707f
+#define MATCH_VLSSEG4WV  0x78006007
+#define MASK_VLSSEG4WV   0xfc00707f
+
+#define MATCH_VLSSEG5BV  0x98000007
+#define MASK_VLSSEG5BV   0xfc00707f
+#define MATCH_VLSSEG5HV  0x98005007
+#define MASK_VLSSEG5HV   0xfc00707f
+#define MATCH_VLSSEG5WV  0x98006007
+#define MASK_VLSSEG5WV   0xfc00707f
+
+#define MATCH_VLSSEG6BV  0xb8000007
+#define MASK_VLSSEG6BV   0xfc00707f
+#define MATCH_VLSSEG6HV  0xb8005007
+#define MASK_VLSSEG6HV   0xfc00707f
+#define MATCH_VLSSEG6WV  0xb8006007
+#define MASK_VLSSEG6WV   0xfc00707f
+
+#define MATCH_VLSSEG7BV  0xd8000007
+#define MASK_VLSSEG7BV   0xfc00707f
+#define MATCH_VLSSEG7HV  0xd8005007
+#define MASK_VLSSEG7HV   0xfc00707f
+#define MATCH_VLSSEG7WV  0xd8006007
+#define MASK_VLSSEG7WV   0xfc00707f
+
+#define MATCH_VLSSEG8BV  0xf8000007
+#define MASK_VLSSEG8BV   0xfc00707f
+#define MATCH_VLSSEG8HV  0xf8005007
+#define MASK_VLSSEG8HV   0xfc00707f
+#define MATCH_VLSSEG8WV  0xf8006007
+#define MASK_VLSSEG8WV   0xfc00707f
+
+#define MATCH_VLXSEG2BV  0x3c000007
+#define MASK_VLXSEG2BV   0xfc00707f
+#define MATCH_VLXSEG2HV  0x3c005007
+#define MASK_VLXSEG2HV   0xfc00707f
+#define MATCH_VLXSEG2WV  0x3c006007
+#define MASK_VLXSEG2WV   0xfc00707f
+
+#define MATCH_VLXSEG3BV  0x5c000007
+#define MASK_VLXSEG3BV   0xfc00707f
+#define MATCH_VLXSEG3HV  0x5c005007
+#define MASK_VLXSEG3HV   0xfc00707f
+#define MATCH_VLXSEG3WV  0x5c006007
+#define MASK_VLXSEG3WV   0xfc00707f
+
+#define MATCH_VLXSEG4BV  0x7c000007
+#define MASK_VLXSEG4BV   0xfc00707f
+#define MATCH_VLXSEG4HV  0x7c005007
+#define MASK_VLXSEG4HV   0xfc00707f
+#define MATCH_VLXSEG4WV  0x7c006007
+#define MASK_VLXSEG4WV   0xfc00707f
+
+#define MATCH_VLXSEG5BV  0x9c000007
+#define MASK_VLXSEG5BV   0xfc00707f
+#define MATCH_VLXSEG5HV  0x9c005007
+#define MASK_VLXSEG5HV   0xfc00707f
+#define MATCH_VLXSEG5WV  0x9c006007
+#define MASK_VLXSEG5WV   0xfc00707f
+
+#define MATCH_VLXSEG6BV  0xbc000007
+#define MASK_VLXSEG6BV   0xfc00707f
+#define MATCH_VLXSEG6HV  0xbc005007
+#define MASK_VLXSEG6HV   0xfc00707f
+#define MATCH_VLXSEG6WV  0xbc006007
+#define MASK_VLXSEG6WV   0xfc00707f
+
+#define MATCH_VLXSEG7BV  0xdc000007
+#define MASK_VLXSEG7BV   0xfc00707f
+#define MATCH_VLXSEG7HV  0xdc005007
+#define MASK_VLXSEG7HV   0xfc00707f
+#define MATCH_VLXSEG7WV  0xdc006007
+#define MASK_VLXSEG7WV   0xfc00707f
+
+#define MATCH_VLXSEG8BV  0xfc000007
+#define MASK_VLXSEG8BV   0xfc00707f
+#define MATCH_VLXSEG8HV  0xfc005007
+#define MASK_VLXSEG8HV   0xfc00707f
+#define MATCH_VLXSEG8WV  0xfc006007
+#define MASK_VLXSEG8WV   0xfc00707f
+
+#define MATCH_VLSEG2BFFV  0x31000007
+#define MASK_VLSEG2BFFV   0xfdf0707f
+#define MATCH_VLSEG2HFFV  0x31005007
+#define MASK_VLSEG2HFFV   0xfdf0707f
+#define MATCH_VLSEG2WFFV  0x31006007
+#define MASK_VLSEG2WFFV   0xfdf0707f
+
+#define MATCH_VLSEG3BFFV  0x51000007
+#define MASK_VLSEG3BFFV   0xfdf0707f
+#define MATCH_VLSEG3HFFV  0x51005007
+#define MASK_VLSEG3HFFV   0xfdf0707f
+#define MATCH_VLSEG3WFFV  0x51006007
+#define MASK_VLSEG3WFFV   0xfdf0707f
+
+#define MATCH_VLSEG4BFFV  0x71000007
+#define MASK_VLSEG4BFFV   0xfdf0707f
+#define MATCH_VLSEG4HFFV  0x71005007
+#define MASK_VLSEG4HFFV   0xfdf0707f
+#define MATCH_VLSEG4WFFV  0x71006007
+#define MASK_VLSEG4WFFV   0xfdf0707f
+
+#define MATCH_VLSEG5BFFV  0x91000007
+#define MASK_VLSEG5BFFV   0xfdf0707f
+#define MATCH_VLSEG5HFFV  0x91005007
+#define MASK_VLSEG5HFFV   0xfdf0707f
+#define MATCH_VLSEG5WFFV  0x91006007
+#define MASK_VLSEG5WFFV   0xfdf0707f
+
+#define MATCH_VLSEG6BFFV  0xb1000007
+#define MASK_VLSEG6BFFV   0xfdf0707f
+#define MATCH_VLSEG6HFFV  0xb1005007
+#define MASK_VLSEG6HFFV   0xfdf0707f
+#define MATCH_VLSEG6WFFV  0xb1006007
+#define MASK_VLSEG6WFFV   0xfdf0707f
+
+#define MATCH_VLSEG7BFFV  0xd1000007
+#define MASK_VLSEG7BFFV   0xfdf0707f
+#define MATCH_VLSEG7HFFV  0xd1005007
+#define MASK_VLSEG7HFFV   0xfdf0707f
+#define MATCH_VLSEG7WFFV  0xd1006007
+#define MASK_VLSEG7WFFV   0xfdf0707f
+
+#define MATCH_VLSEG8BFFV  0xf1000007
+#define MASK_VLSEG8BFFV   0xfdf0707f
+#define MATCH_VLSEG8HFFV  0xf1005007
+#define MASK_VLSEG8HFFV   0xfdf0707f
+#define MATCH_VLSEG8WFFV  0xf1006007
+#define MASK_VLSEG8WFFV   0xfdf0707f
+
+#define MATCH_VNSRLVV  0xb0000057
+#define MASK_VNSRLVV   0xfc00707f
+#define MATCH_VNSRLVX  0xb0004057
+#define MASK_VNSRLVX   0xfc00707f
+#define MATCH_VNSRLVI  0xb0003057
+#define MASK_VNSRLVI   0xfc00707f
+#define MATCH_VNSRAVV  0xb4000057
+#define MASK_VNSRAVV   0xfc00707f
+#define MATCH_VNSRAVX  0xb4004057
+#define MASK_VNSRAVX   0xfc00707f
+#define MATCH_VNSRAVI  0xb4003057
+#define MASK_VNSRAVI   0xfc00707f
+
+#define MATCH_VWMACCSUVV_ZV 0xf8002057
+#define MASK_VWMACCSUVV_ZV  0xfc00707f
+#define MATCH_VWMACCSUVX_ZV 0xf8006057
+#define MASK_VWMACCSUVX_ZV  0xfc00707f
+#define MATCH_VWMACCUSVX_ZV 0xfc006057
+#define MASK_VWMACCUSVX_ZV  0xfc00707f
+
+#define MATCH_VAADDVV_ZV  0x90000057
+#define MASK_VAADDVV_ZV   0xfc00707f
+#define MATCH_VAADDVX_ZV  0x90004057
+#define MASK_VAADDVX_ZV   0xfc00707f
+#define MATCH_VAADDVI     0x90003057
+#define MASK_VAADDVI      0xfc00707f
+#define MATCH_VASUBVV_ZV  0x98000057
+#define MASK_VASUBVV_ZV   0xfc00707f
+#define MATCH_VASUBVX_ZV  0x98004057
+#define MASK_VASUBVX_ZV   0xfc00707f
+
+#define MATCH_VWSMACCUVV  0xf0000057
+#define MASK_VWSMACCUVV   0xfc00707f
+#define MATCH_VWSMACCUVX  0xf0004057
+#define MASK_VWSMACCUVX   0xfc00707f
+#define MATCH_VWSMACCVV   0xf4000057
+#define MASK_VWSMACCVV    0xfc00707f
+#define MATCH_VWSMACCVX   0xf4004057
+#define MASK_VWSMACCVX    0xfc00707f
+#define MATCH_VWSMACCSUVV 0xf8000057
+#define MASK_VWSMACCSUVV  0xfc00707f
+#define MATCH_VWSMACCSUVX 0xf8004057
+#define MASK_VWSMACCSUVX  0xfc00707f
+#define MATCH_VWSMACCUSVX 0xfc004057
+#define MASK_VWSMACCUSVX  0xfc00707f
+
+#define MATCH_VFSQRTV_ZV  0x8c001057
+#define MASK_VFSQRTV_ZV   0xfc0ff07f
+#define MATCH_VFCLASSV_ZV 0x8c081057
+#define MASK_VFCLASSV_ZV  0xfc0ff07f
+
+#define MATCH_VFCVTXUFV_ZV  0x88001057
+#define MASK_VFCVTXUFV_ZV   0xfc0ff07f
+#define MATCH_VFCVTXFV_ZV   0x88009057
+#define MASK_VFCVTXFV_ZV    0xfc0ff07f
+#define MATCH_VFCVTFXUV_ZV  0x88011057
+#define MASK_VFCVTFXUV_ZV   0xfc0ff07f
+#define MATCH_VFCVTFXV_ZV   0x88019057
+#define MASK_VFCVTFXV_ZV    0xfc0ff07f
+
+#define MATCH_VFWCVTXUFV_ZV  0x88041057
+#define MASK_VFWCVTXUFV_ZV   0xfc0ff07f
+#define MATCH_VFWCVTXFV_ZV   0x88049057
+#define MASK_VFWCVTXFV_ZV    0xfc0ff07f
+#define MATCH_VFWCVTFXUV_ZV  0x88051057
+#define MASK_VFWCVTFXUV_ZV   0xfc0ff07f
+#define MATCH_VFWCVTFXV_ZV   0x88059057
+#define MASK_VFWCVTFXV_ZV    0xfc0ff07f
+#define MATCH_VFWCVTFFV_ZV   0x88061057
+#define MASK_VFWCVTFFV_ZV    0xfc0ff07f
+
+#define MATCH_VNCLIPUVV 0xb8000057
+#define MASK_VNCLIPUVV  0xfc00707f
+#define MATCH_VNCLIPUVX 0xb8004057
+#define MASK_VNCLIPUVX  0xfc00707f
+#define MATCH_VNCLIPUVI 0xb8003057
+#define MASK_VNCLIPUVI  0xfc00707f
+#define MATCH_VNCLIPVV  0xbc000057
+#define MASK_VNCLIPVV   0xfc00707f
+#define MATCH_VNCLIPVX  0xbc004057
+#define MASK_VNCLIPVX   0xfc00707f
+#define MATCH_VNCLIPVI  0xbc003057
+#define MASK_VNCLIPVI   0xfc00707f
+
+#define MATCH_VMFORDVV 0x68001057
+#define MASK_VMFORDVV  0xfc00707f
+
+#define MATCH_VFNCVTXUFV  0x88081057
+#define MASK_VFNCVTXUFV   0xfc0ff07f
+#define MATCH_VFNCVTXFV   0x88089057
+#define MASK_VFNCVTXFV    0xfc0ff07f
+#define MATCH_VFNCVTFXUV  0x88091057
+#define MASK_VFNCVTFXUV   0xfc0ff07f
+#define MATCH_VFNCVTFXV   0x88099057
+#define MASK_VFNCVTFXV    0xfc0ff07f
+#define MATCH_VFNCVTFFV   0x880a1057
+#define MASK_VFNCVTFFV    0xfc0ff07f
+
+#define MATCH_VMFORDVF 0x68005057
+#define MASK_VMFORDVF  0xfc00707f
+#define MATCH_VMPOPCM  0x50002057
+#define MASK_VMPOPCM   0xfc0ff07f
+#define MATCH_VMFIRSTM 0x54002057
+#define MASK_VMFIRSTM  0xfc0ff07f
+
+#define MATCH_VMSBFM_ZV   0x5800a057
+#define MASK_VMSBFM_ZV    0xfc0ff07f
+#define MATCH_VMSIFM_ZV   0x5801a057
+#define MASK_VMSIFM_ZV    0xfc0ff07f
+#define MATCH_VMSOFM_ZV   0x58012057
+#define MASK_VMSOFM_ZV    0xfc0ff07f
+#define MATCH_VIOTAM_ZV   0x58082057
+#define MASK_VIOTAM_ZV    0xfc0ff07f
+#define MATCH_VIDV_ZV     0x5808a057
+#define MASK_VIDV_ZV      0xfdfff07f
+
+#define MATCH_VEXTXV      0x32002057
+#define MASK_VEXTXV       0xfe00707f
+#define MATCH_VMVXS_ZV    0x32002057
+#define MASK_VMVXS_ZV     0xfe0ff07f
+#define MATCH_VMVSX_ZV    0x36006057
+#define MASK_VMVSX_ZV     0xfff0707f
+
+#define MATCH_VFMVFS_ZV   0x32001057
+#define MASK_VFMVFS_ZV    0xfe0ff07f
+#define MATCH_VFMVSF_ZV   0x36005057
+#define MASK_VFMVSF_ZV    0xfff0707f
+
+/* ZVAMO extension.  */
+#define MATCH_VAMOADDWV   0x0000602f
+#define MASK_VAMOADDWV    0xf800707f
+#define MATCH_VAMOADDDV   0x0000702f
+#define MASK_VAMOADDDV    0xf800707f
+#define MATCH_VAMOSWAPWV  0x0800602f
+#define MASK_VAMOSWAPWV   0xf800707f
+#define MATCH_VAMOSWAPDV  0x0800702f
+#define MASK_VAMOSWAPDV   0xf800707f
+#define MATCH_VAMOXORWV   0x2000602f
+#define MASK_VAMOXORWV    0xf800707f
+#define MATCH_VAMOXORDV   0x2000702f
+#define MASK_VAMOXORDV    0xf800707f
+#define MATCH_VAMOANDWV   0x6000602f
+#define MASK_VAMOANDWV    0xf800707f
+#define MATCH_VAMOANDDV   0x6000702f
+#define MASK_VAMOANDDV    0xf800707f
+#define MATCH_VAMOORWV    0x4000602f
+#define MASK_VAMOORWV     0xf800707f
+#define MATCH_VAMOORDV    0x4000702f
+#define MASK_VAMOORDV     0xf800707f
+#define MATCH_VAMOMINWV   0x8000602f
+#define MASK_VAMOMINWV    0xf800707f
+#define MATCH_VAMOMINDV   0x8000702f
+#define MASK_VAMOMINDV    0xf800707f
+#define MATCH_VAMOMAXWV   0xa000602f
+#define MASK_VAMOMAXWV    0xf800707f
+#define MATCH_VAMOMAXDV   0xa000702f
+#define MASK_VAMOMAXDV    0xf800707f
+#define MATCH_VAMOMINUWV  0xc000602f
+#define MASK_VAMOMINUWV   0xf800707f
+#define MATCH_VAMOMINUDV  0xc000702f
+#define MASK_VAMOMINUDV   0xf800707f
+#define MATCH_VAMOMAXUWV  0xe000602f
+#define MASK_VAMOMAXUWV   0xf800707f
+#define MATCH_VAMOMAXUDV  0xe000702f
+#define MASK_VAMOMAXUDV   0xf800707f
 /* Zvbb instructions.  */
 #define MATCH_VANDN_VV 0x4000057
 #define MASK_VANDN_VV 0xfc00707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 710a9b73189..55898009f85 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -436,7 +436,9 @@ enum riscv_insn_class
   INSN_CLASS_ZBC_OR_ZBKC,
   INSN_CLASS_ZKND_OR_ZKNE,
   INSN_CLASS_V,
+  INSN_CLASS_V_OR_XTHEADV,
   INSN_CLASS_ZVEF,
+  INSN_CLASS_ZVEF_OR_XTHEADV,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVKG,
@@ -467,6 +469,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADMEMIDX,
   INSN_CLASS_XTHEADMEMPAIR,
   INSN_CLASS_XTHEADSYNC,
+  INSN_CLASS_XTHEADV,
   INSN_CLASS_XVENTANACONDOPS,
 };
 
@@ -586,6 +589,9 @@ extern const char * const riscv_vsew[8];
 extern const char * const riscv_vlmul[8];
 extern const char * const riscv_vta[2];
 extern const char * const riscv_vma[2];
+/* xtheadv.  */
+extern const char * const riscv_vlen[4];
+extern const char * const riscv_vediv[4];
 extern const char * const riscv_fli_symval[32];
 extern const float riscv_fli_numval[32];
 
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 72d727cd77e..30ccb083c4b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -110,6 +110,18 @@ const char * const riscv_vma[2] =
   "mu", "ma"
 };
 
+/* xtheadv, The vsetvli vlmul constants.  */
+const char * const riscv_vlen[4] =
+{
+    "m1", "m2", "m4", "m8"
+};
+
+/* xtheadv, The vsetvli vediv constants.  */
+const char * const riscv_vediv[4] =
+{
+    "d1", "d2", "d4", "d8"
+};
+
 /* The FLI.[HSDQ] symbolic constants (NULL for numeric constant).  */
 const char * const riscv_fli_symval[32] =
 {
@@ -1150,8 +1162,8 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sm3p1",    0, INSN_CLASS_ZKSH,    "d,s",    MATCH_SM3P1, MASK_SM3P1, match_opcode, 0 },
 
 /* RVV instructions.  */
-{"vsetvl",     0, INSN_CLASS_V,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
-{"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
+{"vsetvl",     0, INSN_CLASS_V_OR_XTHEADV,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
+{"vsetvli",    0, INSN_CLASS_V_OR_XTHEADV,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
 {"vsetivli",   0, INSN_CLASS_V,  "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
 
 {"vlm.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLMV, MASK_VLMV, match_opcode, INSN_DREF },
@@ -1507,33 +1519,33 @@ const struct riscv_opcode riscv_opcodes[] =
 
 {"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_opcode, INSN_ALIAS },
 
-{"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
-{"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
-{"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
-{"vsub.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
-{"vsub.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
-{"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
-{"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
-
-{"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_opcode, INSN_ALIAS },
-{"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_opcode, INSN_ALIAS },
-
-{"vwaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_opcode, 0 },
-{"vwaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_opcode, 0 },
-{"vwsubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_opcode, 0 },
-{"vwsubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_opcode, 0 },
-{"vwadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_opcode, 0 },
-{"vwadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_opcode, 0 },
-{"vwsub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_opcode, 0 },
-{"vwsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_opcode, 0 },
-{"vwaddu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_opcode, 0 },
-{"vwaddu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_opcode, 0 },
-{"vwsubu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_opcode, 0 },
-{"vwsubu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_opcode, 0 },
-{"vwadd.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_opcode, 0 },
-{"vwadd.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_opcode, 0 },
-{"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_opcode, 0 },
-{"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_opcode, 0 },
+{"vadd.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 },
+{"vadd.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 },
+{"vadd.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 },
+{"vsub.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_opcode, 0 },
+{"vsub.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_opcode, 0 },
+{"vrsub.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_opcode, 0 },
+{"vrsub.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_opcode, 0 },
+
+{"vwcvt.x.x.v",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_opcode, INSN_ALIAS },
+{"vwcvtu.x.x.v", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_opcode, INSN_ALIAS },
+
+{"vwaddu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_opcode, 0 },
+{"vwaddu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_opcode, 0 },
+{"vwsubu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_opcode, 0 },
+{"vwsubu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_opcode, 0 },
+{"vwadd.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_opcode, 0 },
+{"vwadd.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_opcode, 0 },
+{"vwsub.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_opcode, 0 },
+{"vwsub.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_opcode, 0 },
+{"vwaddu.wv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_opcode, 0 },
+{"vwaddu.wx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_opcode, 0 },
+{"vwsubu.wv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_opcode, 0 },
+{"vwsubu.wx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_opcode, 0 },
+{"vwadd.wv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_opcode, 0 },
+{"vwadd.wx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_opcode, 0 },
+{"vwsub.wv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_opcode, 0 },
+{"vwsub.wx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_opcode, 0 },
 
 {"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_opcode, 0 },
 {"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_opcode, 0 },
@@ -1542,43 +1554,43 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vzext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_opcode, 0 },
 {"vsext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_opcode, 0 },
 
-{"vadc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
-{"vadc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
-{"vadc.vim",   0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
-{"vmadc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
-{"vmadc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
-{"vmadc.vim",  0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
+{"vadc.vvm",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_opcode, 0 },
+{"vadc.vxm",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_opcode, 0 },
+{"vadc.vim",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_opcode, 0 },
+{"vmadc.vvm",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
+{"vmadc.vxm",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
+{"vmadc.vim",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
 {"vmadc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
 {"vmadc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
 {"vmadc.vi",   0, INSN_CLASS_V,  "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
-{"vsbc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
-{"vsbc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
-{"vmsbc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
-{"vmsbc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
+{"vsbc.vvm",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_opcode, 0 },
+{"vsbc.vxm",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_opcode, 0 },
+{"vmsbc.vvm",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
+{"vmsbc.vxm",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
 {"vmsbc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
 {"vmsbc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
 
-{"vnot.v",     0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
-
-{"vand.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
-{"vand.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
-{"vand.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
-{"vor.vv",     0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
-{"vor.vx",     0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
-{"vor.vi",     0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
-{"vxor.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
-{"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
-{"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
-
-{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
-{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
-{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
-{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
-{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
-{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
-{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
-{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
-{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
+{"vnot.v",     0, INSN_CLASS_V_OR_XTHEADV,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_opcode, INSN_ALIAS },
+
+{"vand.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_opcode, 0 },
+{"vand.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_opcode, 0 },
+{"vand.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_opcode, 0 },
+{"vor.vv",     0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_opcode, 0 },
+{"vor.vx",     0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_opcode, 0 },
+{"vor.vi",     0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_opcode, 0 },
+{"vxor.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_opcode, 0 },
+{"vxor.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_opcode, 0 },
+{"vxor.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_opcode, 0 },
+
+{"vsll.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_opcode, 0 },
+{"vsll.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_opcode, 0 },
+{"vsll.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_opcode, 0 },
+{"vsrl.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_opcode, 0 },
+{"vsrl.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_opcode, 0 },
+{"vsrl.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_opcode, 0 },
+{"vsra.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 },
+{"vsra.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 },
+{"vsra.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 },
 
 {"vncvt.x.x.w",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_opcode, INSN_ALIAS },
 
@@ -1589,130 +1601,138 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_opcode, 0 },
 {"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_opcode, 0 },
 
-{"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
-{"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
-{"vmseq.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
-{"vmsne.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
-{"vmsne.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
-{"vmsne.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
-{"vmsltu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
-{"vmsltu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
-{"vmslt.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
-{"vmslt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
-{"vmsleu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
-{"vmsleu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
-{"vmsleu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
-{"vmsle.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
-{"vmsle.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
-{"vmsle.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
-{"vmsgtu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
-{"vmsgtu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
-{"vmsgt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
-{"vmsgt.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
-{"vmsgt.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
-{"vmsgtu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
-{"vmsge.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
-{"vmsgeu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
-{"vmslt.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
-{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_vs1_eq_vs2, INSN_ALIAS },
-{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
-{"vmsge.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
-{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_vs1_eq_vs2, INSN_ALIAS },
-{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
-
-{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
-{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
-{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO },
-{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO },
-
-{"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
-{"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
-{"vmin.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
-{"vmin.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
-{"vmaxu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
-{"vmaxu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
-{"vmax.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
-{"vmax.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
-
-{"vmul.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
-{"vmul.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
-{"vmulh.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
-{"vmulh.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
-{"vmulhu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
-{"vmulhu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
-{"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
-{"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
-
-{"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_opcode, 0 },
-{"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_opcode, 0 },
-{"vwmulu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_opcode, 0 },
-{"vwmulu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_opcode, 0 },
-{"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_opcode, 0 },
-{"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_opcode, 0 },
-
-{"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
-{"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
-{"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
-{"vnmsac.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
-{"vmadd.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
-{"vmadd.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
-{"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
-{"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
-
-{"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_opcode, 0},
-{"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_opcode, 0},
-{"vwmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_opcode, 0},
-{"vwmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_opcode, 0},
+{"vmseq.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
+{"vmseq.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
+{"vmseq.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
+{"vmsne.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
+{"vmsne.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
+{"vmsne.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
+{"vmsltu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
+{"vmsltu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
+{"vmslt.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
+{"vmslt.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
+{"vmsleu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
+{"vmsleu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
+{"vmsleu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
+{"vmsle.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
+{"vmsle.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
+{"vmsle.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
+{"vmsgtu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
+{"vmsgtu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
+{"vmsgt.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
+{"vmsgt.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
+{"vmsgt.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
+{"vmsgtu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
+{"vmsge.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
+{"vmsgeu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
+{"vmslt.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
+{"vmsltu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_vs1_eq_vs2, INSN_ALIAS },
+{"vmsltu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
+{"vmsge.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
+{"vmsgeu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_vs1_eq_vs2, INSN_ALIAS },
+{"vmsgeu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
+
+{"vmsge.vx",   0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"vmsge.vx",   0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"vmsgeu.vx",  0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"vmsgeu.vx",  0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+
+{"vminu.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_opcode, 0},
+{"vminu.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_opcode, 0},
+{"vmin.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_opcode, 0},
+{"vmin.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_opcode, 0},
+{"vmaxu.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_opcode, 0},
+{"vmaxu.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_opcode, 0},
+{"vmax.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_opcode, 0},
+{"vmax.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_opcode, 0},
+
+{"vmul.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_opcode, 0 },
+{"vmul.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_opcode, 0 },
+{"vmulh.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_opcode, 0 },
+{"vmulh.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_opcode, 0 },
+{"vmulhu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_opcode, 0 },
+{"vmulhu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_opcode, 0 },
+{"vmulhsu.vv", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_opcode, 0 },
+{"vmulhsu.vx", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_opcode, 0 },
+
+{"vwmul.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_opcode, 0 },
+{"vwmul.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_opcode, 0 },
+{"vwmulu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_opcode, 0 },
+{"vwmulu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_opcode, 0 },
+{"vwmulsu.vv", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_opcode, 0 },
+{"vwmulsu.vx", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_opcode, 0 },
+
+{"vmacc.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_opcode, 0},
+{"vmacc.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_opcode, 0},
+{"vnmsac.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_opcode, 0},
+{"vnmsac.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_opcode, 0},
+{"vmadd.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_opcode, 0},
+{"vmadd.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_opcode, 0},
+{"vnmsub.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_opcode, 0},
+{"vnmsub.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_opcode, 0},
+
+{"vwmaccu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_opcode, 0},
+{"vwmaccu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_opcode, 0},
+{"vwmacc.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_opcode, 0},
+{"vwmacc.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_opcode, 0},
 {"vwmaccsu.vv", 0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_opcode, 0},
+{"vwmaccsu.vv", 0, INSN_CLASS_XTHEADV,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV_ZV, MASK_VWMACCSUVV_ZV, match_opcode, 0},
 {"vwmaccsu.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_opcode, 0},
+{"vwmaccsu.vx", 0, INSN_CLASS_XTHEADV,  "Vd,s,VtVm", MATCH_VWMACCSUVX_ZV, MASK_VWMACCSUVX_ZV, match_opcode, 0},
 {"vwmaccus.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_opcode, 0},
-
-{"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
-{"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
-{"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
-{"vdiv.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
-{"vremu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
-{"vremu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
-{"vrem.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
-{"vrem.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
-
-{"vmerge.vvm", 0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
-{"vmerge.vxm", 0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
-{"vmerge.vim", 0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
-
-{"vmv.v.v",    0, INSN_CLASS_V,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
-{"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
-{"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
-
-{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
-{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
-{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
-{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
-{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
-{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
-{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
-{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
-{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
-{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
+{"vwmaccus.vx", 0, INSN_CLASS_XTHEADV, "Vd,s,VtVm", MATCH_VWMACCUSVX_ZV, MASK_VWMACCUSVX_ZV, match_opcode, 0},
+
+{"vdivu.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_opcode, 0 },
+{"vdivu.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_opcode, 0 },
+{"vdiv.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_opcode, 0 },
+{"vdiv.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_opcode, 0 },
+{"vremu.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_opcode, 0 },
+{"vremu.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_opcode, 0 },
+{"vrem.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_opcode, 0 },
+{"vrem.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_opcode, 0 },
+
+{"vmerge.vvm", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
+{"vmerge.vxm", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
+{"vmerge.vim", 0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
+
+{"vmv.v.v",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
+{"vmv.v.x",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
+{"vmv.v.i",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
+
+{"vsaddu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
+{"vsaddu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
+{"vsaddu.vi",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
+{"vsadd.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
+{"vsadd.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
+{"vsadd.vi",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
+{"vssubu.vv",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
+{"vssubu.vx",  0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
+{"vssub.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
+{"vssub.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
 
 {"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_opcode, 0 },
 {"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_opcode, 0 },
 {"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_opcode, 0 },
+{"vaadd.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VAADDVV_ZV, MASK_VAADDVV_ZV, match_opcode, 0 },
 {"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_opcode, 0 },
+{"vaadd.vx",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,sVm", MATCH_VAADDVX_ZV, MASK_VAADDVX_ZV, match_opcode, 0 },
+{"vaadd.vi",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,ViVm", MATCH_VAADDVI, MASK_VAADDVI, match_opcode, 0 },
 {"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_opcode, 0 },
 {"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_opcode, 0 },
 {"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_opcode, 0 },
+{"vasub.vv", 0, INSN_CLASS_XTHEADV, "Vd,Vt,VsVm", MATCH_VASUBVV_ZV, MASK_VASUBVV_ZV, match_opcode, 0 },
 {"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_opcode, 0 },
+{"vasub.vx", 0, INSN_CLASS_XTHEADV, "Vd,Vt,sVm", MATCH_VASUBVX_ZV, MASK_VASUBVX_ZV, match_opcode, 0 },
 
-{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
-{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
+{"vsmul.vv",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
+{"vsmul.vx",   0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
 
-{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
-{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
-{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
-{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
-{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
-{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
+{"vssrl.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
+{"vssrl.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
+{"vssrl.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
+{"vssra.vv",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
+{"vssra.vx",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
+{"vssra.vi",    0, INSN_CLASS_V_OR_XTHEADV,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
 
 {"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 },
 {"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 },
@@ -1721,190 +1741,210 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
 {"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
 
-{"vfadd.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
-{"vfadd.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
-{"vfsub.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
-{"vfsub.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
-{"vfrsub.vf",  0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
-
-{"vfwadd.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_opcode, 0},
-{"vfwadd.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_opcode, 0},
-{"vfwsub.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_opcode, 0},
-{"vfwsub.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_opcode, 0},
-{"vfwadd.wv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_opcode, 0},
-{"vfwadd.wf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_opcode, 0},
-{"vfwsub.wv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_opcode, 0},
-{"vfwsub.wf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_opcode, 0},
-
-{"vfmul.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
-{"vfmul.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
-{"vfdiv.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
-{"vfdiv.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
-{"vfrdiv.vf",  0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
-
-{"vfwmul.vv",  0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_opcode, 0},
-{"vfwmul.vf",  0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0},
-
-{"vfmadd.vv",  0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
-{"vfmadd.vf",  0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
-{"vfnmadd.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
-{"vfnmadd.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
-{"vfmsub.vv",  0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
-{"vfmsub.vf",  0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
-{"vfnmsub.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
-{"vfnmsub.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
-{"vfmacc.vv",  0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
-{"vfmacc.vf",  0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
-{"vfnmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
-{"vfnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
-{"vfmsac.vv",  0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
-{"vfmsac.vf",  0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
-{"vfnmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
-{"vfnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
-
-{"vfwmacc.vv",  0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0},
-{"vfwmacc.vf",  0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0},
-{"vfwnmacc.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0},
-{"vfwnmacc.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0},
-{"vfwmsac.vv",  0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0},
-{"vfwmsac.vf",  0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0},
-{"vfwnmsac.vv", 0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0},
-{"vfwnmsac.vf", 0, INSN_CLASS_ZVEF, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0},
+{"vfadd.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
+{"vfadd.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
+{"vfsub.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
+{"vfsub.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
+{"vfrsub.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
+
+{"vfwadd.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_opcode, 0},
+{"vfwadd.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_opcode, 0},
+{"vfwsub.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_opcode, 0},
+{"vfwsub.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_opcode, 0},
+{"vfwadd.wv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_opcode, 0},
+{"vfwadd.wf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_opcode, 0},
+{"vfwsub.wv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_opcode, 0},
+{"vfwsub.wf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_opcode, 0},
+
+{"vfmul.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
+{"vfmul.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
+{"vfdiv.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
+{"vfdiv.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
+{"vfrdiv.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
+
+{"vfwmul.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_opcode, 0},
+{"vfwmul.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0},
+
+{"vfmadd.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
+{"vfmadd.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
+{"vfnmadd.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
+{"vfnmadd.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
+{"vfmsub.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
+{"vfmsub.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
+{"vfnmsub.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
+{"vfnmsub.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
+{"vfmacc.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
+{"vfmacc.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
+{"vfnmacc.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
+{"vfnmacc.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
+{"vfmsac.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
+{"vfmsac.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
+{"vfnmsac.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
+{"vfnmsac.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
+
+{"vfwmacc.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0},
+{"vfwmacc.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0},
+{"vfwnmacc.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0},
+{"vfwnmacc.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0},
+{"vfwmsac.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0},
+{"vfwmsac.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0},
+{"vfwnmsac.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0},
+{"vfwnmsac.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0},
 
 {"vfsqrt.v",   0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_opcode, 0},
+{"vfsqrt.v", 0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFSQRTV_ZV, MASK_VFSQRTV_ZV, match_opcode, 0},
 {"vfrsqrt7.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_opcode, 0},
 {"vfrsqrte7.v",0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_opcode, 0},
 {"vfrec7.v",   0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_opcode, 0},
 {"vfrece7.v",  0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_opcode, 0},
 {"vfclass.v",  0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_opcode, 0},
+{"vfclass.v", 0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFCLASSV_ZV, MASK_VFCLASSV_ZV, match_opcode, 0},
 
-{"vfmin.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
-{"vfmin.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
-{"vfmax.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
-{"vfmax.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
+{"vfmin.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
+{"vfmin.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
+{"vfmax.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
+{"vfmax.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
 
 {"vfneg.v",    0, INSN_CLASS_ZVEF, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2, INSN_ALIAS },
 {"vfabs.v",    0, INSN_CLASS_ZVEF, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2, INSN_ALIAS },
 
-{"vfsgnj.vv",  0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
-{"vfsgnj.vf",  0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
-{"vfsgnjn.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
-{"vfsgnjn.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
-{"vfsgnjx.vv", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
-{"vfsgnjx.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
-
-{"vmfeq.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
-{"vmfeq.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
-{"vmfne.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
-{"vmfne.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
-{"vmflt.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
-{"vmflt.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
-{"vmfle.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
-{"vmfle.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
-{"vmfgt.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
-{"vmfge.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
+{"vfsgnj.vv",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
+{"vfsgnj.vf",  0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
+{"vfsgnjn.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
+{"vfsgnjn.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
+{"vfsgnjx.vv", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
+{"vfsgnjx.vf", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
+
+{"vmfeq.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
+{"vmfeq.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
+{"vmfne.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
+{"vmfne.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
+{"vmflt.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
+{"vmflt.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
+{"vmfle.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
+{"vmfle.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
+{"vmfgt.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
+{"vmfge.vf",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
 
 /* These aliases are for assembly but not disassembly.  */
-{"vmfgt.vv",    0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
-{"vmfge.vv",   0, INSN_CLASS_ZVEF, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
+{"vmfgt.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
+{"vmfge.vv",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
 
-{"vfmerge.vfm",0, INSN_CLASS_ZVEF, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
-{"vfmv.v.f",   0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
+{"vfmerge.vfm",0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
+{"vfmv.v.f",   0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
 
 {"vfcvt.xu.f.v",     0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_opcode, 0},
+{"vfcvt.xu.f.v",     0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFCVTXUFV_ZV, MASK_VFCVTXUFV_ZV, match_opcode, 0},
 {"vfcvt.x.f.v",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_opcode, 0},
+{"vfcvt.x.f.v",      0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFCVTXFV_ZV, MASK_VFCVTXFV_ZV, match_opcode, 0},
 {"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_opcode, 0},
 {"vfcvt.rtz.x.f.v",  0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_opcode, 0},
 {"vfcvt.f.xu.v",     0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_opcode, 0},
+{"vfcvt.f.xu.v",     0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFCVTFXUV_ZV, MASK_VFCVTFXUV_ZV, match_opcode, 0},
 {"vfcvt.f.x.v",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_opcode, 0},
+{"vfcvt.f.x.v",      0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFCVTFXV_ZV, MASK_VFCVTFXV_ZV, match_opcode, 0},
 
 {"vfwcvt.xu.f.v",     0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_opcode, 0},
+{"vfwcvt.xu.f.v",     0, INSN_CLASS_XTHEADV,   "Vd,VtVm", MATCH_VFWCVTXUFV_ZV, MASK_VFWCVTXUFV_ZV, match_opcode, 0},
 {"vfwcvt.x.f.v",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_opcode, 0},
+{"vfwcvt.x.f.v",      0, INSN_CLASS_XTHEADV,   "Vd,VtVm", MATCH_VFWCVTXFV_ZV, MASK_VFWCVTXFV_ZV, match_opcode, 0},
 {"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_opcode, 0},
 {"vfwcvt.rtz.x.f.v",  0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_opcode, 0},
 {"vfwcvt.f.xu.v",     0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_opcode, 0},
+{"vfwcvt.f.xu.v",     0, INSN_CLASS_XTHEADV,   "Vd,VtVm", MATCH_VFWCVTFXUV_ZV, MASK_VFWCVTFXUV_ZV, match_opcode, 0},
 {"vfwcvt.f.x.v",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_opcode, 0},
+{"vfwcvt.f.x.v",      0, INSN_CLASS_XTHEADV,   "Vd,VtVm", MATCH_VFWCVTFXV_ZV, MASK_VFWCVTFXV_ZV, match_opcode, 0},
 {"vfwcvt.f.f.v",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_opcode, 0},
+{"vfwcvt.f.f.v",      0, INSN_CLASS_XTHEADV,   "Vd,VtVm", MATCH_VFWCVTFFV_ZV, MASK_VFWCVTFFV_ZV, match_opcode, 0},
 
 {"vfncvt.xu.f.w",     0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_opcode, 0},
 {"vfncvt.x.f.w",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_opcode, 0},
-{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_opcode, 0},
-{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_opcode, 0},
-{"vfncvt.f.xu.w",     0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_opcode, 0},
-{"vfncvt.f.x.w",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_opcode, 0},
 {"vfncvt.f.f.w",      0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_opcode, 0},
 {"vfncvt.rod.f.f.w",  0, INSN_CLASS_ZVEF, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_opcode, 0},
 
-{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
-{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
-{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
-{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
-{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
-{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
-{"vredor.vs",  0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
-{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
+{"vredsum.vs", 0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
+{"vredmaxu.vs",0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
+{"vredmax.vs", 0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
+{"vredminu.vs",0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
+{"vredmin.vs", 0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
+{"vredand.vs", 0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
+{"vredor.vs",  0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
+{"vredxor.vs", 0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
 
-{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
-{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
+{"vwredsumu.vs",0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
+{"vwredsum.vs", 0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
 
-{"vfredosum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
+{"vfredosum.vs",0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
 {"vfredusum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0},
 {"vfredsum.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, INSN_ALIAS},
-{"vfredmax.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
-{"vfredmin.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
+{"vfredsum.vs", 0, INSN_CLASS_XTHEADV,   "Vd,Vt,VsVm", MATCH_VFREDUSUMVS, MASK_VFREDUSUMVS, match_opcode, 0},
+{"vfredmax.vs", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
+{"vfredmin.vs", 0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
 
-{"vfwredosum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
+{"vfwredosum.vs",0, INSN_CLASS_ZVEF_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
 {"vfwredusum.vs",0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
 {"vfwredsum.vs", 0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, INSN_ALIAS},
+{"vfwredsum.vs", 0, INSN_CLASS_XTHEADV,   "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
 
 {"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
-{"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
-{"vmclr.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
-{"vmset.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
-{"vmnot.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+{"vmcpy.m",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+{"vmclr.m",    0, INSN_CLASS_V_OR_XTHEADV, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+{"vmset.m",    0, INSN_CLASS_V_OR_XTHEADV, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+{"vmnot.m",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
 
-{"vmand.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
-{"vmnand.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
+{"vmand.mm",   0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
+{"vmnand.mm",  0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
 {"vmandn.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
 {"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, INSN_ALIAS},
-{"vmxor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
-{"vmor.mm",    0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
-{"vmnor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
+{"vmandnot.mm",0, INSN_CLASS_XTHEADV, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
+{"vmxor.mm",   0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
+{"vmor.mm",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
+{"vmnor.mm",   0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
 {"vmorn.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
 {"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, INSN_ALIAS},
-{"vmxnor.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
+{"vmornot.mm", 0, INSN_CLASS_XTHEADV, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
+{"vmxnor.mm",  0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
 
 {"vcpop.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, 0},
 {"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VCPOPM, MASK_VCPOPM, match_opcode, INSN_ALIAS},
 {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
 {"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_opcode, 0},
+{"vmsbf.m",    0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VMSBFM_ZV, MASK_VMSBFM_ZV, match_opcode, 0},
 {"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_opcode, 0},
+{"vmsif.m",    0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VMSIFM_ZV, MASK_VMSIFM_ZV, match_opcode, 0},
 {"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_opcode, 0},
+{"vmsof.m",    0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VMSOFM_ZV, MASK_VMSOFM_ZV, match_opcode, 0},
 {"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_opcode, 0},
+{"viota.m",    0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VIOTAM_ZV, MASK_VIOTAM_ZV, match_opcode, 0},
 {"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_opcode, 0},
+{"vid.v",      0, INSN_CLASS_XTHEADV, "VdVm", MATCH_VIDV_ZV, MASK_VIDV_ZV, match_opcode, 0},
 
 {"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
+{"vmv.x.s",    0, INSN_CLASS_XTHEADV, "d,Vt", MATCH_VMVXS_ZV, MASK_VMVXS_ZV, match_opcode, INSN_ALIAS},
 {"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
+{"vmv.s.x",    0, INSN_CLASS_XTHEADV, "Vd,s", MATCH_VMVSX_ZV, MASK_VMVSX_ZV, match_opcode, 0},
 
-{"vfmv.f.s",   0, INSN_CLASS_ZVEF, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
-{"vfmv.s.f",   0, INSN_CLASS_ZVEF, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
+{"vfmv.f.s",   0, INSN_CLASS_V, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
+{"vfmv.f.s",   0, INSN_CLASS_XTHEADV, "D,Vt", MATCH_VFMVFS_ZV, MASK_VFMVFS_ZV, match_opcode, 0},
+{"vfmv.s.f",   0, INSN_CLASS_V, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
+{"vfmv.s.f",   0, INSN_CLASS_XTHEADV, "Vd,S", MATCH_VFMVSF_ZV, MASK_VFMVSF_ZV, match_opcode, 0},
 
-{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0},
-{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0},
-{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
-{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
+{"vslideup.vx",0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0},
+{"vslideup.vi",0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0},
+{"vslidedown.vx",0,INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
+{"vslidedown.vi",0,INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
 
-{"vslide1up.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0},
-{"vslide1down.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
+{"vslide1up.vx",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0},
+{"vslide1down.vx",  0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
 {"vfslide1up.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_opcode, 0},
 {"vfslide1down.vf", 0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_opcode, 0},
 
-{"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0},
-{"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0},
-{"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0},
+{"vrgather.vv",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0},
+{"vrgather.vx",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0},
+{"vrgather.vi",    0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0},
 {"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_opcode, 0},
 
-{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0},
+{"vcompress.vm",0, INSN_CLASS_V_OR_XTHEADV, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0},
 
 {"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_opcode, 0},
 {"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_opcode, 0},
@@ -1980,6 +2020,424 @@ const struct riscv_opcode riscv_opcodes[] =
 {"c.zext.w",  64, INSN_CLASS_ZCB_AND_ZBA, "Cs",  MATCH_C_ZEXT_W, MASK_C_ZEXT_W, match_opcode, 0 },
 {"c.zext.b",   0, INSN_CLASS_ZCB, "Cs",  MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 },
 {"c.sext.w",  64, INSN_CLASS_ZCB, "d",  MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
+/* RVV 0.7 instructions.*/
+{"vlb.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLBV, MASK_VLBV, match_opcode, INSN_DREF },
+{"vlh.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLHV, MASK_VLHV, match_opcode, INSN_DREF },
+{"vlw.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLWV, MASK_VLWV, match_opcode, INSN_DREF },
+{"vlbu.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF },
+{"vlhu.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF },
+{"vlwu.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF },
+{"vle.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF },
+{"vsb.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF },
+{"vsh.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF },
+{"vsw.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF },
+{"vse.v",      0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF },
+
+{"vlsb.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSBV, MASK_VLSBV, match_opcode, INSN_DREF },
+{"vlsh.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSHV, MASK_VLSHV, match_opcode, INSN_DREF },
+{"vlsw.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSWV, MASK_VLSWV, match_opcode, INSN_DREF },
+{"vlsbu.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF },
+{"vlshu.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF },
+{"vlswu.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF },
+{"vlse.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF },
+{"vssb.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF },
+{"vssh.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF },
+{"vssw.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF },
+{"vsse.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF },
+
+{"vlxb.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXBV, MASK_VLXBV, match_opcode, INSN_DREF },
+{"vlxh.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXHV, MASK_VLXHV, match_opcode, INSN_DREF },
+{"vlxw.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXWV, MASK_VLXWV, match_opcode, INSN_DREF },
+{"vlxbu.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF },
+{"vlxhu.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF },
+{"vlxwu.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI16V, match_opcode, INSN_DREF },
+{"vlxe.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI16V, match_opcode, INSN_DREF },
+{"vsxb.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF },
+{"vsxh.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF },
+{"vsxw.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF },
+{"vsxe.v",     0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF },
+{"vsuxb.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSUXBV, MASK_VSUXBV, match_opcode, INSN_DREF },
+{"vsuxh.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSUXHV, MASK_VSUXHV, match_opcode, INSN_DREF },
+{"vsuxw.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSUXWV, MASK_VSUXWV, match_opcode, INSN_DREF },
+{"vsuxe.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSUXEV, MASK_VSUXEV, match_opcode, INSN_DREF },
+
+{"vlbff.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLBFFV, MASK_VLBFFV, match_opcode, INSN_DREF },
+{"vlhff.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLHFFV, MASK_VLHFFV, match_opcode, INSN_DREF },
+{"vlwff.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLWFFV, MASK_VLWFFV, match_opcode, INSN_DREF },
+{"vlbuff.v",   0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF },
+{"vlhuff.v",   0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
+{"vlwuff.v",   0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
+{"vleff.v",    0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
+
+{"vlseg2b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2BV, MASK_VLSEG2BV, match_opcode, INSN_DREF },
+{"vlseg2h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2HV, MASK_VLSEG2HV, match_opcode, INSN_DREF },
+{"vlseg2w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2WV, MASK_VLSEG2WV, match_opcode, INSN_DREF },
+{"vlseg2bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF },
+{"vlseg2hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_opcode, INSN_DREF },
+{"vlseg2wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_opcode, INSN_DREF },
+{"vlseg2e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF },
+{"vsseg2b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
+{"vsseg2h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
+{"vsseg2w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
+{"vsseg2e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
+
+{"vlseg3b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3BV, MASK_VLSEG3BV, match_opcode, INSN_DREF },
+{"vlseg3h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3HV, MASK_VLSEG3HV, match_opcode, INSN_DREF },
+{"vlseg3w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3WV, MASK_VLSEG3WV, match_opcode, INSN_DREF },
+{"vlseg3bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_opcode, INSN_DREF },
+{"vlseg3hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_opcode, INSN_DREF },
+{"vlseg3wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_opcode, INSN_DREF },
+{"vlseg3e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_opcode, INSN_DREF },
+{"vsseg3b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
+{"vsseg3h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
+{"vsseg3w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
+{"vsseg3e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
+
+{"vlseg4b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4BV, MASK_VLSEG4BV, match_opcode, INSN_DREF },
+{"vlseg4h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4HV, MASK_VLSEG4HV, match_opcode, INSN_DREF },
+{"vlseg4w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4WV, MASK_VLSEG4WV, match_opcode, INSN_DREF },
+{"vlseg4bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_opcode, INSN_DREF },
+{"vlseg4hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_opcode, INSN_DREF },
+{"vlseg4wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_opcode, INSN_DREF },
+{"vlseg4e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF },
+{"vsseg4b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
+{"vsseg4h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
+{"vsseg4w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
+{"vsseg4e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
+
+{"vlseg5b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5BV, MASK_VLSEG5BV, match_opcode, INSN_DREF },
+{"vlseg5h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5HV, MASK_VLSEG5HV, match_opcode, INSN_DREF },
+{"vlseg5w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5WV, MASK_VLSEG5WV, match_opcode, INSN_DREF },
+{"vlseg5bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_opcode, INSN_DREF },
+{"vlseg5hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_opcode, INSN_DREF },
+{"vlseg5wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_opcode, INSN_DREF },
+{"vlseg5e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF },
+{"vsseg5b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
+{"vsseg5h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
+{"vsseg5w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
+{"vsseg5e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
+
+{"vlseg6b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6BV, MASK_VLSEG6BV, match_opcode, INSN_DREF },
+{"vlseg6h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6HV, MASK_VLSEG6HV, match_opcode, INSN_DREF },
+{"vlseg6w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6WV, MASK_VLSEG6WV, match_opcode, INSN_DREF },
+{"vlseg6bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_opcode, INSN_DREF },
+{"vlseg6hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_opcode, INSN_DREF },
+{"vlseg6wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_opcode, INSN_DREF },
+{"vlseg6e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF },
+{"vsseg6b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
+{"vsseg6h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
+{"vsseg6w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
+{"vsseg6e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
+
+{"vlseg7b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7BV, MASK_VLSEG7BV, match_opcode, INSN_DREF },
+{"vlseg7h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7HV, MASK_VLSEG7HV, match_opcode, INSN_DREF },
+{"vlseg7w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7WV, MASK_VLSEG7WV, match_opcode, INSN_DREF },
+{"vlseg7bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_opcode, INSN_DREF },
+{"vlseg7hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_opcode, INSN_DREF },
+{"vlseg7wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_opcode, INSN_DREF },
+{"vlseg7e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF },
+{"vsseg7b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
+{"vsseg7h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
+{"vsseg7w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
+{"vsseg7e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
+
+{"vlseg8b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8BV, MASK_VLSEG8BV, match_opcode, INSN_DREF },
+{"vlseg8h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8HV, MASK_VLSEG8HV, match_opcode, INSN_DREF },
+{"vlseg8w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8WV, MASK_VLSEG8WV, match_opcode, INSN_DREF },
+{"vlseg8bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_opcode, INSN_DREF },
+{"vlseg8hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_opcode, INSN_DREF },
+{"vlseg8wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF },
+{"vlseg8e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF },
+{"vsseg8b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
+{"vsseg8h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
+{"vsseg8w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
+{"vsseg8e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
+
+{"vlsseg2b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2BV, MASK_VLSSEG2BV, match_opcode, INSN_DREF },
+{"vlsseg2h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2HV, MASK_VLSSEG2HV, match_opcode, INSN_DREF },
+{"vlsseg2w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2WV, MASK_VLSSEG2WV, match_opcode, INSN_DREF },
+{"vlsseg2bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF },
+{"vlsseg2hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_opcode, INSN_DREF },
+{"vlsseg2wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_opcode, INSN_DREF },
+{"vlsseg2e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF },
+{"vssseg2b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
+{"vssseg2h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
+{"vssseg2w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
+{"vssseg2e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
+
+{"vlsseg3b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3BV, MASK_VLSSEG3BV, match_opcode, INSN_DREF },
+{"vlsseg3h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3HV, MASK_VLSSEG3HV, match_opcode, INSN_DREF },
+{"vlsseg3w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3WV, MASK_VLSSEG3WV, match_opcode, INSN_DREF },
+{"vlsseg3bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_opcode, INSN_DREF },
+{"vlsseg3hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_opcode, INSN_DREF },
+{"vlsseg3wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_opcode, INSN_DREF },
+{"vlsseg3e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF },
+{"vssseg3b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
+{"vssseg3h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
+{"vssseg3w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
+{"vssseg3e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
+
+{"vlsseg4b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4BV, MASK_VLSSEG4BV, match_opcode, INSN_DREF },
+{"vlsseg4h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4HV, MASK_VLSSEG4HV, match_opcode, INSN_DREF },
+{"vlsseg4w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4WV, MASK_VLSSEG4WV, match_opcode, INSN_DREF },
+{"vlsseg4bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_opcode, INSN_DREF },
+{"vlsseg4hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_opcode, INSN_DREF },
+{"vlsseg4wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_opcode, INSN_DREF },
+{"vlsseg4e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF },
+{"vssseg4b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
+{"vssseg4h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
+{"vssseg4w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
+{"vssseg4e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
+
+{"vlsseg5b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5BV, MASK_VLSSEG5BV, match_opcode, INSN_DREF },
+{"vlsseg5h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5HV, MASK_VLSSEG5HV, match_opcode, INSN_DREF },
+{"vlsseg5w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5WV, MASK_VLSSEG5WV, match_opcode, INSN_DREF },
+{"vlsseg5bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_opcode, INSN_DREF },
+{"vlsseg5hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_opcode, INSN_DREF },
+{"vlsseg5wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_opcode, INSN_DREF },
+{"vlsseg5e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF },
+{"vssseg5b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
+{"vssseg5h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
+{"vssseg5w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
+{"vssseg5e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
+
+{"vlsseg6b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6BV, MASK_VLSSEG6BV, match_opcode, INSN_DREF },
+{"vlsseg6h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6HV, MASK_VLSSEG6HV, match_opcode, INSN_DREF },
+{"vlsseg6w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6WV, MASK_VLSSEG6WV, match_opcode, INSN_DREF },
+{"vlsseg6bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_opcode, INSN_DREF },
+{"vlsseg6hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_opcode, INSN_DREF },
+{"vlsseg6wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_opcode, INSN_DREF },
+{"vlsseg6e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF },
+{"vssseg6b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
+{"vssseg6h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
+{"vssseg6w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
+{"vssseg6e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
+
+{"vlsseg7b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7BV, MASK_VLSSEG7BV, match_opcode, INSN_DREF },
+{"vlsseg7h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7HV, MASK_VLSSEG7HV, match_opcode, INSN_DREF },
+{"vlsseg7w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7WV, MASK_VLSSEG7WV, match_opcode, INSN_DREF },
+{"vlsseg7bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_opcode, INSN_DREF },
+{"vlsseg7hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_opcode, INSN_DREF },
+{"vlsseg7wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_opcode, INSN_DREF },
+{"vlsseg7e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF },
+{"vssseg7b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
+{"vssseg7h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
+{"vssseg7w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
+{"vssseg7e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
+
+{"vlsseg8b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8BV, MASK_VLSSEG8BV, match_opcode, INSN_DREF },
+{"vlsseg8h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8HV, MASK_VLSSEG8HV, match_opcode, INSN_DREF },
+{"vlsseg8w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8WV, MASK_VLSSEG8WV, match_opcode, INSN_DREF },
+{"vlsseg8bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_opcode, INSN_DREF },
+{"vlsseg8hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_opcode, INSN_DREF },
+{"vlsseg8wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF },
+{"vlsseg8e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF },
+{"vssseg8b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
+{"vssseg8h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
+{"vssseg8w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
+{"vssseg8e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
+
+{"vlxseg2b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG2BV, MASK_VLXSEG2BV, match_opcode, INSN_DREF },
+{"vlxseg2h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG2HV, MASK_VLXSEG2HV, match_opcode, INSN_DREF },
+{"vlxseg2w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG2WV, MASK_VLXSEG2WV, match_opcode, INSN_DREF },
+{"vlxseg2bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF },
+{"vlxseg2hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_opcode, INSN_DREF },
+{"vlxseg2wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_opcode, INSN_DREF },
+{"vlxseg2e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF },
+{"vsxseg2b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF },
+{"vsxseg2h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_opcode, INSN_DREF },
+{"vsxseg2w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_opcode, INSN_DREF },
+{"vsxseg2e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF },
+
+{"vlxseg3b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG3BV, MASK_VLXSEG3BV, match_opcode, INSN_DREF },
+{"vlxseg3h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG3HV, MASK_VLXSEG3HV, match_opcode, INSN_DREF },
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+{"vlxseg3hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_opcode, INSN_DREF },
+{"vlxseg3wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_opcode, INSN_DREF },
+{"vlxseg3e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF },
+{"vsxseg3b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_opcode, INSN_DREF },
+{"vsxseg3h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_opcode, INSN_DREF },
+{"vsxseg3w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_opcode, INSN_DREF },
+{"vsxseg3e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF },
+
+{"vlxseg4b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG4BV, MASK_VLXSEG4BV, match_opcode, INSN_DREF },
+{"vlxseg4h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG4HV, MASK_VLXSEG4HV, match_opcode, INSN_DREF },
+{"vlxseg4w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG4WV, MASK_VLXSEG4WV, match_opcode, INSN_DREF },
+{"vlxseg4bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_opcode, INSN_DREF },
+{"vlxseg4hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_opcode, INSN_DREF },
+{"vlxseg4wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_opcode, INSN_DREF },
+{"vlxseg4e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF },
+{"vsxseg4b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_opcode, INSN_DREF },
+{"vsxseg4h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_opcode, INSN_DREF },
+{"vsxseg4w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_opcode, INSN_DREF },
+{"vsxseg4e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF },
+
+{"vlxseg5b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG5BV, MASK_VLXSEG5BV, match_opcode, INSN_DREF },
+{"vlxseg5h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG5HV, MASK_VLXSEG5HV, match_opcode, INSN_DREF },
+{"vlxseg5w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG5WV, MASK_VLXSEG5WV, match_opcode, INSN_DREF },
+{"vlxseg5bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_opcode, INSN_DREF },
+{"vlxseg5hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_opcode, INSN_DREF },
+{"vlxseg5wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_opcode, INSN_DREF },
+{"vlxseg5e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF },
+{"vsxseg5b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_opcode, INSN_DREF },
+{"vsxseg5h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_opcode, INSN_DREF },
+{"vsxseg5w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_opcode, INSN_DREF },
+{"vsxseg5e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF },
+
+{"vlxseg6b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG6BV, MASK_VLXSEG6BV, match_opcode, INSN_DREF },
+{"vlxseg6h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG6HV, MASK_VLXSEG6HV, match_opcode, INSN_DREF },
+{"vlxseg6w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG6WV, MASK_VLXSEG6WV, match_opcode, INSN_DREF },
+{"vlxseg6bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_opcode, INSN_DREF },
+{"vlxseg6hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_opcode, INSN_DREF },
+{"vlxseg6wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_opcode, INSN_DREF },
+{"vlxseg6e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF },
+{"vsxseg6b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_opcode, INSN_DREF },
+{"vsxseg6h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_opcode, INSN_DREF },
+{"vsxseg6w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_opcode, INSN_DREF },
+{"vsxseg6e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF },
+
+{"vlxseg7b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG7BV, MASK_VLXSEG7BV, match_opcode, INSN_DREF },
+{"vlxseg7h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG7HV, MASK_VLXSEG7HV, match_opcode, INSN_DREF },
+{"vlxseg7w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG7WV, MASK_VLXSEG7WV, match_opcode, INSN_DREF },
+{"vlxseg7bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_opcode, INSN_DREF },
+{"vlxseg7hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_opcode, INSN_DREF },
+{"vlxseg7wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_opcode, INSN_DREF },
+{"vlxseg7e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF },
+{"vsxseg7b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_opcode, INSN_DREF },
+{"vsxseg7h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_opcode, INSN_DREF },
+{"vsxseg7w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_opcode, INSN_DREF },
+{"vsxseg7e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF },
+
+{"vlxseg8b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG8BV, MASK_VLXSEG8BV, match_opcode, INSN_DREF },
+{"vlxseg8h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG8HV, MASK_VLXSEG8HV, match_opcode, INSN_DREF },
+{"vlxseg8w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLXSEG8WV, MASK_VLXSEG8WV, match_opcode, INSN_DREF },
+{"vlxseg8bu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_opcode, INSN_DREF },
+{"vlxseg8hu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_opcode, INSN_DREF },
+{"vlxseg8wu.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF },
+{"vlxseg8e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF },
+{"vsxseg8b.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_opcode, INSN_DREF },
+{"vsxseg8h.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_opcode, INSN_DREF },
+{"vsxseg8w.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF },
+{"vsxseg8e.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF },
+
+{"vlseg2bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2BFFV, MASK_VLSEG2BFFV, match_opcode, INSN_DREF },
+{"vlseg2hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2HFFV, MASK_VLSEG2HFFV, match_opcode, INSN_DREF },
+{"vlseg2wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2WFFV, MASK_VLSEG2WFFV, match_opcode, INSN_DREF },
+{"vlseg2buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF },
+{"vlseg2huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_opcode, INSN_DREF },
+{"vlseg2wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_opcode, INSN_DREF },
+{"vlseg2eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF },
+
+{"vlseg3bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3BFFV, MASK_VLSEG3BFFV, match_opcode, INSN_DREF },
+{"vlseg3hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3HFFV, MASK_VLSEG3HFFV, match_opcode, INSN_DREF },
+{"vlseg3wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3WFFV, MASK_VLSEG3WFFV, match_opcode, INSN_DREF },
+{"vlseg3buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF },
+{"vlseg3huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_opcode, INSN_DREF },
+{"vlseg3wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_opcode, INSN_DREF },
+{"vlseg3eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF },
+
+{"vlseg4bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4BFFV, MASK_VLSEG4BFFV, match_opcode, INSN_DREF },
+{"vlseg4hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4HFFV, MASK_VLSEG4HFFV, match_opcode, INSN_DREF },
+{"vlseg4wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4WFFV, MASK_VLSEG4WFFV, match_opcode, INSN_DREF },
+{"vlseg4buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_opcode, INSN_DREF },
+{"vlseg4huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_opcode, INSN_DREF },
+{"vlseg4wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_opcode, INSN_DREF },
+{"vlseg4eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF },
+
+{"vlseg5bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5BFFV, MASK_VLSEG5BFFV, match_opcode, INSN_DREF },
+{"vlseg5hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5HFFV, MASK_VLSEG5HFFV, match_opcode, INSN_DREF },
+{"vlseg5wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5WFFV, MASK_VLSEG5WFFV, match_opcode, INSN_DREF },
+{"vlseg5buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_opcode, INSN_DREF },
+{"vlseg5huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_opcode, INSN_DREF },
+{"vlseg5wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_opcode, INSN_DREF },
+{"vlseg5eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF },
+
+{"vlseg6bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6BFFV, MASK_VLSEG6BFFV, match_opcode, INSN_DREF },
+{"vlseg6hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6HFFV, MASK_VLSEG6HFFV, match_opcode, INSN_DREF },
+{"vlseg6wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6WFFV, MASK_VLSEG6WFFV, match_opcode, INSN_DREF },
+{"vlseg6buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_opcode, INSN_DREF },
+{"vlseg6huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_opcode, INSN_DREF },
+{"vlseg6wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_opcode, INSN_DREF },
+{"vlseg6eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF },
+
+{"vlseg7bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7BFFV, MASK_VLSEG7BFFV, match_opcode, INSN_DREF },
+{"vlseg7hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7HFFV, MASK_VLSEG7HFFV, match_opcode, INSN_DREF },
+{"vlseg7wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7WFFV, MASK_VLSEG7WFFV, match_opcode, INSN_DREF },
+{"vlseg7buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_opcode, INSN_DREF },
+{"vlseg7huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_opcode, INSN_DREF },
+{"vlseg7wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF },
+{"vlseg7eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF },
+
+{"vlseg8bff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8BFFV, MASK_VLSEG8BFFV, match_opcode, INSN_DREF },
+{"vlseg8hff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8HFFV, MASK_VLSEG8HFFV, match_opcode, INSN_DREF },
+{"vlseg8wff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8WFFV, MASK_VLSEG8WFFV, match_opcode, INSN_DREF },
+{"vlseg8buff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_opcode, INSN_DREF },
+{"vlseg8huff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF },
+{"vlseg8wuff.v", 0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF },
+{"vlseg8eff.v",  0, INSN_CLASS_XTHEADV,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF },
+
+{"vnsrl.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VNSRLVV, MASK_VNSRLVV, match_opcode, 0 },
+{"vnsrl.vx",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,sVm", MATCH_VNSRLVX, MASK_VNSRLVX, match_opcode, 0 },
+{"vnsrl.vi",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VjVm", MATCH_VNSRLVI, MASK_VNSRLVI, match_opcode, 0 },
+{"vnsra.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VNSRAVV, MASK_VNSRAVV, match_opcode, 0 },
+{"vnsra.vx",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,sVm", MATCH_VNSRAVX, MASK_VNSRAVX, match_opcode, 0 },
+{"vnsra.vi",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VjVm", MATCH_VNSRAVI, MASK_VNSRAVI, match_opcode, 0 },
+
+{"vwsmaccu.vv", 0, INSN_CLASS_XTHEADV,  "Vd,Vs,VtVm", MATCH_VWSMACCUVV, MASK_VWSMACCUVV, match_opcode, 0 },
+{"vwsmaccu.vx", 0, INSN_CLASS_XTHEADV,  "Vd,s,VtVm", MATCH_VWSMACCUVX, MASK_VWSMACCUVX, match_opcode, 0 },
+{"vwsmacc.vv",  0, INSN_CLASS_XTHEADV,  "Vd,Vs,VtVm", MATCH_VWSMACCVV, MASK_VWSMACCVV, match_opcode, 0 },
+{"vwsmacc.vx",  0, INSN_CLASS_XTHEADV,  "Vd,s,VtVm", MATCH_VWSMACCVX, MASK_VWSMACCVX, match_opcode, 0 },
+{"vwsmaccsu.vv",0, INSN_CLASS_XTHEADV,  "Vd,Vs,VtVm", MATCH_VWSMACCSUVV, MASK_VWSMACCSUVV, match_opcode, 0 },
+{"vwsmaccsu.vx",0, INSN_CLASS_XTHEADV,  "Vd,s,VtVm", MATCH_VWSMACCSUVX, MASK_VWSMACCSUVX, match_opcode, 0 },
+{"vwsmaccus.vx",0, INSN_CLASS_XTHEADV,  "Vd,s,VtVm", MATCH_VWSMACCUSVX, MASK_VWSMACCUSVX, match_opcode, 0 },
+
+{"vnclipu.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VNCLIPUVV, MASK_VNCLIPUVV, match_opcode, 0 },
+{"vnclipu.vx",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,sVm", MATCH_VNCLIPUVX, MASK_VNCLIPUVX, match_opcode, 0 },
+{"vnclipu.vi",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VjVm", MATCH_VNCLIPUVI, MASK_VNCLIPUVI, match_opcode, 0 },
+{"vnclip.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VNCLIPVV, MASK_VNCLIPVV, match_opcode, 0 },
+{"vnclip.vx",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,sVm", MATCH_VNCLIPVX, MASK_VNCLIPVX, match_opcode, 0 },
+{"vnclip.vi",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VjVm", MATCH_VNCLIPVI, MASK_VNCLIPVI, match_opcode, 0 },
+
+{"vmford.vv",  0, INSN_CLASS_XTHEADV, "Vd,Vt,VsVm", MATCH_VMFORDVV, MASK_VMFORDVV, match_opcode, 0},
+{"vmford.vf",  0, INSN_CLASS_XTHEADV, "Vd,Vt,SVm", MATCH_VMFORDVF, MASK_VMFORDVF, match_opcode, 0},
+
+{"vfncvt.xu.f.v",0,INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFNCVTXUFV, MASK_VFNCVTXUFV, match_opcode, 0},
+{"vfncvt.x.f.v",0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFNCVTXFV, MASK_VFNCVTXFV, match_opcode, 0},
+{"vfncvt.f.xu.v",0,INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFNCVTFXUV, MASK_VFNCVTFXUV, match_opcode, 0},
+{"vfncvt.f.x.v",0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFNCVTFXV, MASK_VFNCVTFXV, match_opcode, 0},
+{"vfncvt.f.f.v",0, INSN_CLASS_XTHEADV, "Vd,VtVm", MATCH_VFNCVTFFV, MASK_VFNCVTFFV, match_opcode, 0},
+
+{"vmpopc.m",   0, INSN_CLASS_XTHEADV, "d,VtVm", MATCH_VMPOPCM, MASK_VMPOPCM, match_opcode, 0 },
+{"vmfirst.m",  0, INSN_CLASS_XTHEADV, "d,VtVm", MATCH_VMFIRSTM, MASK_VMFIRSTM, match_opcode, 0},
+
+{"vext.x.v",   0, INSN_CLASS_XTHEADV, "d,Vt,s", MATCH_VEXTXV, MASK_VEXTXV, match_opcode, 0},
+
+{"vdot.vv",    0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VDOTVV, MASK_VDOTVV, match_opcode, 0},
+{"vdotu.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VDOTUVV, MASK_VDOTUVV, match_opcode, 0},
+{"vfdot.vv",   0, INSN_CLASS_XTHEADV,  "Vd,Vt,VsVm", MATCH_VFDOTVV, MASK_VFDOTVV, match_opcode, 0},
+
+/* Zvamo instructions.  */
+{"vamoaddw.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOADDWV, MASK_VAMOADDWV, match_opcode, INSN_DREF},
+{"vamoaddd.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOADDDV, MASK_VAMOADDDV, match_opcode, INSN_DREF},
+{"vamoswapw.v",  0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOSWAPWV, MASK_VAMOSWAPWV, match_opcode, INSN_DREF},
+{"vamoswapd.v",  0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOSWAPDV, MASK_VAMOSWAPDV, match_opcode, INSN_DREF},
+
+{"vamoxorw.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOXORWV, MASK_VAMOXORWV, match_opcode, INSN_DREF},
+{"vamoxord.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOXORDV, MASK_VAMOXORDV, match_opcode, INSN_DREF},
+{"vamoandw.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOANDWV, MASK_VAMOANDWV, match_opcode, INSN_DREF},
+{"vamoandd.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOANDDV, MASK_VAMOANDDV, match_opcode, INSN_DREF},
+{"vamoorw.v",    0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOORWV, MASK_VAMOORWV, match_opcode, INSN_DREF},
+{"vamoord.v",    0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOORDV, MASK_VAMOORDV, match_opcode, INSN_DREF},
+
+{"vamominw.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMINWV, MASK_VAMOMINWV, match_opcode, INSN_DREF},
+{"vamomind.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMINDV, MASK_VAMOMINDV, match_opcode, INSN_DREF},
+{"vamomaxw.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMAXWV, MASK_VAMOMAXWV, match_opcode, INSN_DREF},
+{"vamomaxd.v",   0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMAXDV, MASK_VAMOMAXDV, match_opcode, INSN_DREF},
+{"vamominuw.v",  0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMINUWV, MASK_VAMOMINUWV, match_opcode, INSN_DREF},
+{"vamominud.v",  0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMINUDV, MASK_VAMOMINUDV, match_opcode, INSN_DREF},
+{"vamomaxuw.v",  0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMAXUWV, MASK_VAMOMAXUWV, match_opcode, INSN_DREF},
+{"vamomaxud.v",  0, INSN_CLASS_XTHEADV,  "Ve,Vt,(s),VfVm", MATCH_VAMOMAXUDV, MASK_VAMOMAXUDV, match_opcode, INSN_DREF},
 
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
