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Mon, 6 Nov 2023 13:13:08 +0000 From: Victor Do Nascimento To: CC: , , Victor Do Nascimento Subject: [PATCH 3/3] aarch64: Add LSE128 instructions Date: Mon, 6 Nov 2023 13:12:48 +0000 Message-ID: <20231106131301.2576862-4-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106131301.2576862-1-victor.donascimento@arm.com> References: <20231106131301.2576862-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B1:EE_|GV2PR08MB8368:EE_|DU6PEPF00009523:EE_|DB9PR08MB9708:EE_ X-MS-Office365-Filtering-Correlation-Id: d31f52f5-c546-4cca-8d57-08dbdeca26cc X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: ezJk7/DHbXP8Y1zcXpmJ1FR38es0GClFqYlsxziM3AJ5/4b9jK8taXfbXK0P3pA3dos0TERNJ1Yld7U/VfpIHqLutW4rduDF3OJpU2TF827xQdbvU6OdZJQhuOz5O6QdUTn4bPSHHx0+GJDxcvQZ2jXx1NK4grUC9YShYbnf3CrKt7tvukPJWKagioXmoIH+O6+GDxc/2lU7kTcjQFwEuTERn/k/UMkHiczU+iIRw77wzW2r5wcNrs7G4lEAGzqy9UVrKMI+TCB53EdGouAR8qB360WBU17Ve3DYkveVK+HHIymBCnCgnGydBYFE3YtiUVgbDF1Yp2midzFKGeMA7Vrwv7dt0ZxiKDRyvBm3YmoNUUTLF/BUF0T6n7a0LSlnaPcZlTynSLHUsaL1x7dvZYk/exRdWXsoz0r7+N/fcTXj+qjbQsVVRi331lKMM3GYBdhLhU6EGjNKr03leYHTs/v9Hxj5v9GeA4EsTQBbgaDseYBmANojGiPIeT8vsX7sXuTxUZDBuSwWqZsuqhUy8Vj8IA8DwVPDKSi2WTOl8le6+rISSixifrxl8V17mT0rJgyrhLlRbP3M7D1zOFPcTB5l56+zRaZw+yYl6eM0EpzT33Tsh0H1c0K+aVX3VtdcSo85GvVnLg/otfkFda1O/UJlLpVHqx8OlDLaCDmBIYNa+jqqdp7b+JNABrj3LbwSgkqDJ4FSb28uzWq9fczkQ2o5WH4LaeOK2II01n3jF7LNfT/jdiX5cFFlqQLUJdnWFlPZoLXanHh21de4OLT8VA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009523.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9708 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Implement, together with the necessary tests, the following new LSE128 atomic instructions: * Atomic bit clear on quadword in memory (ldclrp{a|l|al}); * Atomic bit set on quadword in memory (ldsetp{a|l|al}); * Swap quadword in memory (swpp{a|l|al}); gas/ChangeLog: * testsuite/gas/aarch64/lse128-atomic.d: New. * testsuite/gas/aarch64/lse128-atomic.s: Likewise. opcodes/ChangeLog: * aarch64-tbl.h (ldclrp): new _LSE128_INSN entry. (ldclrpa): Likewise. (ldclrpal): Likewise. (ldclrpl): Likewise. (ldsetp): Likewise. (ldsetpa): Likewise. (ldsetpal): Likewise. (ldsetpl): Likewise. (swpp): Likewise. (swppa): Likewise. (swppal): Likewise. (swppl): Likewise. --- gas/testsuite/gas/aarch64/lse128-atomic.d | 32 ++++++++++++++++++++++ gas/testsuite/gas/aarch64/lse128-atomic.s | 33 +++++++++++++++++++++++ opcodes/aarch64-tbl.h | 13 +++++++++ 3 files changed, 78 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.d create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.s diff --git a/gas/testsuite/gas/aarch64/lse128-atomic.d b/gas/testsuite/gas/aarch64/lse128-atomic.d new file mode 100644 index 00000000000..bea83fe3642 --- /dev/null +++ b/gas/testsuite/gas/aarch64/lse128-atomic.d @@ -0,0 +1,32 @@ +#objdump: -dr +#as:-march=armv9-a+lse128 + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: 19211040 ldclrp x0, x1, \[x2\] + 4: 192313e2 ldclrp x2, x3, \[sp\] + 8: 19a11040 ldclrpa x0, x1, \[x2\] + c: 19a313e2 ldclrpa x2, x3, \[sp\] + 10: 19e11040 ldclrpal x0, x1, \[x2\] + 14: 19e313e2 ldclrpal x2, x3, \[sp\] + 18: 19611040 ldclrpl x0, x1, \[x2\] + 1c: 196313e2 ldclrpl x2, x3, \[sp\] + 20: 19213040 ldsetp x0, x1, \[x2\] + 24: 192333e2 ldsetp x2, x3, \[sp\] + 28: 19a13040 ldsetpa x0, x1, \[x2\] + 2c: 19a333e2 ldsetpa x2, x3, \[sp\] + 30: 19e13040 ldsetpal x0, x1, \[x2\] + 34: 19e333e2 ldsetpal x2, x3, \[sp\] + 38: 19613040 ldsetpl x0, x1, \[x2\] + 3c: 196333e2 ldsetpl x2, x3, \[sp\] + 40: 19218040 swpp x0, x1, \[x2\] + 44: 192383e2 swpp x2, x3, \[sp\] + 48: 19a18040 swppa x0, x1, \[x2\] + 4c: 19a383e2 swppa x2, x3, \[sp\] + 50: 19e18040 swppal x0, x1, \[x2\] + 54: 19e383e2 swppal x2, x3, \[sp\] + 58: 19618040 swppl x0, x1, \[x2\] + 5c: 196383e2 swppl x2, x3, \[sp\] \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/lse128-atomic.s b/gas/testsuite/gas/aarch64/lse128-atomic.s new file mode 100644 index 00000000000..802f1b76fc7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/lse128-atomic.s @@ -0,0 +1,33 @@ +/* lse128-atomic.s Test file For AArch64 LSE128 atomic instructions + encoding. + + Copyright (C) 2014-2023 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + + .macro format_0 op + .irp suffix, , a, al, l + \op\suffix x0, x1, [x2] + \op\suffix x2, x3, [sp] + .endr + .endm + +func: + format_0 ldclrp + format_0 ldsetp + format_0 swpp diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 58787fbc4a9..74fd6695d81 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4101,6 +4101,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + /* LSE128 extension (atomic). */ + _LSE128_INSN ("ldclrp", 0x19201000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldclrpa", 0x19a01000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldclrpal", 0x19e01000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldclrpl", 0x19601000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetp", 0x19203000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetpa", 0x19a03000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetpal", 0x19e03000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetpl", 0x19603000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swpp", 0x19208000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), /* Move wide (immediate). */ CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV),