diff mbox series

[v1,1/1] opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush insns

Message ID 20230925092244.3449756-1-neal.frager@amd.com
State Accepted, archived
Headers
Series [v1,1/1] opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush insns |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Neal Frager Sept. 25, 2023, 9:22 a.m. UTC 
  Added two new instructions, wdc.ext.clear and wdc.ext.flush,
to enable MicroBlaze to flush an external cache, which is
used with the new coherency support for multiprocessing.

This patch has been tested for years of AMD Xilinx Yocto
releases as part of the following patch set:

https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils

Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
 opcodes/microblaze-opc.h  | 5 ++++-
 opcodes/microblaze-opcm.h | 4 ++--
 2 files changed, 6 insertions(+), 3 deletions(-)

Comments

Nick Clifton Sept. 27, 2023, 1:49 p.m. UTC | #1 
Hi Neal,

> Added two new instructions, wdc.ext.clear and wdc.ext.flush,
> to enable MicroBlaze to flush an external cache, which is
> used with the new coherency support for multiprocessing.

Patch approved and applied.

One small question:

> +  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }

This new line omits a comma at the end.  Was this deliberate ?

I have assumed that it was just a typo and added one, but if there is
a good reason to omit the comma, please let me know and I will correct
the pushed patch.

Cheers
   Nick
Frager, Neal via Binutils Sept. 27, 2023, 1:52 p.m. UTC | #2 
Hi Nick,

> Added two new instructions, wdc.ext.clear and wdc.ext.flush, to enable 
> MicroBlaze to flush an external cache, which is used with the new 
> coherency support for multiprocessing.

> Patch approved and applied.

> One small question:

> +  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, 
> + NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, 
> + OPCODE_MASK_H35B, wdcextclear, special_inst }

> This new line omits a comma at the end.  Was this deliberate ?

> I have assumed that it was just a typo and added one, but if there is a good reason to omit the comma, please let me know and I will correct the pushed patch.

Yes, you are correct.  Thank you for catching this typo and fixing it for me!

Best regards,
Neal Frager
AMD
diff mbox series

Patch

diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 94048e67551..c53eacc3db2 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -91,6 +91,7 @@ 
 #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
 #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
 #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
 
 /* New Mask for msrset, msrclr insns.  */
@@ -101,7 +102,7 @@ 
 #define DELAY_SLOT 1
 #define NO_DELAY_SLOT 0
 
-#define MAX_OPCODES 289
+#define MAX_OPCODES 291
 
 const struct op_code_struct
 {
@@ -174,7 +175,9 @@  const struct op_code_struct
   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }
   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 4cf6f077219..92c245dc0fd 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -33,8 +33,8 @@  enum microblaze_instr
   /* 'or/and/xor' are C++ keywords.  */
   microblaze_or, microblaze_and, microblaze_xor,
   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,