From patchwork Thu Aug 17 18:08:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tatsuyuki Ishi X-Patchwork-Id: 74284 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 346D8385ED78 for ; Thu, 17 Aug 2023 18:09:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 346D8385ED78 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1692295794; bh=NdQ0hoXRGw8WKBEObjxsi9TcN/pwcwTfN8Nco08hiM4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=gW2YjzlAZgZlZMAQFYcvCBRZQ+Ejo8+750Kwi1+pibjdZ6FZBCDK2ZxT0ucs5i4Dg XA+uDwYGrEzJjBKQheQjg4A7SmIfNBpAQGTZxUxCHxtWfiPFyUBcHAPjGU/KqYblKu D8icnOKQocYcZb7HZR09PvkVcC8N5B+zOPhFiMfQ= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id 6DD1E3854826 for ; Thu, 17 Aug 2023 18:09:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6DD1E3854826 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1bb91c20602so161895ad.0 for ; Thu, 17 Aug 2023 11:09:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692295762; x=1692900562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NdQ0hoXRGw8WKBEObjxsi9TcN/pwcwTfN8Nco08hiM4=; b=gF2nf3ggv2JTupfcdKUUS4Gj7hmTlL+dcfSKie2GDJC7+Y60jf8rwJdqL1RW/EmREQ +Slx9Mv0uoOP7rlnUZrFxCSU09Ol4Y33nYZOyZGAFVYnTXr3N7UFwh4ADkzMpotiVIzx r36tTfBXCiWQRGyzE2/2k5Ezl3r/D2odIblvV0HERA4V8ASFGdr3uEGofFo6tZWb83G0 OtEfU0xs/Ly797tk0Pw1fRDXnx2uwRlkHDDVBf3uW2o1rGOppN/9/bOV7PiBvK+VcgXm 7APzeQXj3rhasW0dt4oOF7nwzPBEr0mlnDp/8IZ/gOc+LsvLRefpK7lr48PqI+bz0Ncp mmuA== X-Gm-Message-State: AOJu0YzZE/iTdk870vI3bqEAckgMSDhP3cem3EUW5J4ChhIKkDWmAM5M Vr9GOJW9S7wPFQDKs02XdQQHKEAoVuwApzMo X-Google-Smtp-Source: AGHT+IF95najBguPUFTFwLL+zQ0LzMH+KNA4QrPFeSAIVIGJ9JQGUeQ+4I0BverR/VY2T8UnQ9Ktjg== X-Received: by 2002:a17:903:32c3:b0:1b8:9fc4:2733 with SMTP id i3-20020a17090332c300b001b89fc42733mr148869plr.3.1692295761849; Thu, 17 Aug 2023 11:09:21 -0700 (PDT) Received: from localhost (zz20184013906F627101.userreverse.dion.ne.jp. [111.98.113.1]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d30400b001bdd700dc11sm50870plc.292.2023.08.17.11.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Aug 2023 11:09:20 -0700 (PDT) To: binutils@sourceware.org Cc: rui314@gmail.com, ruiu@bluewhale.systems, Tatsuyuki Ishi Subject: [PATCH 2/4] RISC-V: Add assembly support for TLSDESC. Date: Fri, 18 Aug 2023 03:08:35 +0900 Message-ID: <20230817180852.121628-4-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230817180852.121628-2-ishitatsuyuki@gmail.com> References: <20230817180852.121628-2-ishitatsuyuki@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tatsuyuki Ishi via Binutils From: Tatsuyuki Ishi Reply-To: Tatsuyuki Ishi Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" --- gas/config/tc-riscv.c | 18 +++++++++++++----- opcodes/riscv-opc.c | 1 + 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 959cbbc32a5..0a1fac9de9d 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2195,6 +2195,7 @@ static const struct percent_op_match percent_op_utype[] = {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, + {"tlsdesc_hi", BFD_RELOC_RISCV_TLSDESC_HI20}, {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, {"hi", BFD_RELOC_RISCV_HI20}, @@ -2206,6 +2207,8 @@ static const struct percent_op_match percent_op_itype[] = {"lo", BFD_RELOC_RISCV_LO12_I}, {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, + {"tlsdesc_load_lo", BFD_RELOC_RISCV_TLSDESC_LOAD_LO12}, + {"tlsdesc_add_lo", BFD_RELOC_RISCV_TLSDESC_ADD_LO12}, {0, 0} }; @@ -2217,8 +2220,9 @@ static const struct percent_op_match percent_op_stype[] = {0, 0} }; -static const struct percent_op_match percent_op_rtype[] = +static const struct percent_op_match percent_op_relax_only[] = { + {"tlsdesc_call", BFD_RELOC_RISCV_TLSDESC_CALL}, {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, {0, 0} }; @@ -3326,10 +3330,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, *imm_reloc = BFD_RELOC_RISCV_LO12_I; goto load_store; case '1': - /* This is used for TLS, where the fourth operand is - %tprel_add, to get a relocation applied to an add - instruction, for relaxation to use. */ - p = percent_op_rtype; + /* This is used for TLS relocations that acts as relaxation + markers and do not change the instruction encoding, + i.e. %tprel_add and %tlsdesc_call. */ + p = percent_op_relax_only; goto alu_op; case '0': /* AMO displacement, which must be zero. */ load_store: @@ -4082,6 +4086,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_RISCV_TPREL_LO12_I: case BFD_RELOC_RISCV_TPREL_LO12_S: case BFD_RELOC_RISCV_TPREL_ADD: + case BFD_RELOC_RISCV_TLSDESC_HI20: relaxable = true; /* Fall through. */ @@ -4255,6 +4260,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_RISCV_CALL: case BFD_RELOC_RISCV_CALL_PLT: + case BFD_RELOC_RISCV_TLSDESC_LOAD_LO12: + case BFD_RELOC_RISCV_TLSDESC_ADD_LO12: + case BFD_RELOC_RISCV_TLSDESC_CALL: relaxable = true; break; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 067e9fdb611..467666b9805 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -370,6 +370,7 @@ const struct riscv_opcode riscv_opcodes[] = {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, +{"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },