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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4954a2b074csm51619595e9.6.2026.07.17.06.50.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jul 2026 06:50:23 -0700 (PDT) Message-ID: <1d918dc0-4b90-4093-b261-b91bdf372d39@suse.com> Date: Fri, 17 Jul 2026 15:50:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/2] x86: fold F16C templates with their AVX512VL counterparts From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: X-Spam-Status: No, score=-3015.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org It's not quite clear why this wasn't done so far. These, conceptually, aren't any different from the FMA ones. Doing so actually made me notice a flaw in FMA template handling, which is being fixed alongside making the necessary changes to accommodate F16C: Both features aren't prereqs of AVX512F. When they're disabled, enabling AVX512VL would still not allow the 128- and 256-bit forms to assemble. --- This actually points out another issue with FMA and F16C: Code created prior to the introduction of AVX512 might have used ".arch .no{fma,f16c}" to have uses of the respective insns properly rejected. That protection suddenly ceased to work properly when AVX512 support was added to the assembler: Those insns would now assemble to their AVX512VL EVEX forms. The least bad option to deal with this looks to be to reject the AVX512VL forms also when FMA/F16C are explicitly disabled while AVX512VL isn't explicitly enabled. Are there any better suggestions? --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2314,14 +2314,18 @@ cpu_flags_match (const insn_template *t) { /* Dual AVX/AVX512 templates need to retain AVX512* only if we already know that EVEX encoding will be needed. */ - if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma) + if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 + || any.bitfield.cpufma || any.bitfield.cpuf16c) && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl)) { - if (need_evex_encoding (t)) + if (need_evex_encoding (t) + || (any.bitfield.cpufma && !cpu_arch_flags.bitfield.cpufma) + || (any.bitfield.cpuf16c && !cpu_arch_flags.bitfield.cpuf16c)) { any.bitfield.cpuavx = 0; any.bitfield.cpuavx2 = 0; any.bitfield.cpufma = 0; + any.bitfield.cpuf16c = 0; } /* need_evex_encoding(t) isn't reliable before operands were parsed. */ @@ -4232,10 +4236,12 @@ install_template (const insn_template *t if (t->opcode_modifier.vex && t->opcode_modifier.evex) { if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2) - || maybe_cpu (t, CpuFMA)) + || maybe_cpu (t, CpuFMA) || maybe_cpu (t, CpuF16C)) && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL))) { - if (need_evex_encoding (t)) + if (need_evex_encoding (t) + || (maybe_cpu (t, CpuFMA) && !cpu_arch_flags.bitfield.cpufma) + || (maybe_cpu (t, CpuF16C) && !cpu_arch_flags.bitfield.cpuf16c)) { i.tm.opcode_modifier.vex = 0; i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f; @@ -8799,7 +8805,10 @@ check_VecOperands (const insn_template * if (!cpu_flags_all_zero (&cpu) && !cpu.bitfield.cpuavx512vl && !cpu_arch_flags.bitfield.cpuavx512vl - && (!t->opcode_modifier.vex || need_evex_encoding (t))) + && (!t->opcode_modifier.vex || need_evex_encoding (t) + /* Note: No need to check F16C here. Those insns have distinct + templates for distinct VEX.L / EVEX.L'L. */ + || (maybe_cpu (t, CpuFMA) && !cpu_arch_flags.bitfield.cpufma))) { for (op = 0; op < t->operands; ++op) { --- a/gas/testsuite/gas/i386/avx512vl-plain.l +++ b/gas/testsuite/gas/i386/avx512vl-plain.l @@ -1,8 +1,8 @@ .*: Assembler messages: .*:5: Error: .* -.*:6: Error: .* -.*:7: Error: .* -.*:20: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:22: Error: .* GAS LISTING .* @@ -11,23 +11,27 @@ GAS LISTING .* [ ]*3[ ]+\.arch \.avx512vl [ ]*4[ ]+_start: [ ]*5[ ]+\{evex\} vaesenc[ ]+%ymm1, %ymm2, %ymm3 -[ ]*6[ ]+vgf2p8mulb[ ]+%ymm1, %ymm2, %ymm3\{%k4\} -[ ]*7[ ]+\{evex\} vpclmulqdq[ ]+\$0, %ymm1, %ymm2, %ymm3 -[ ]*8[ ]* -[ ]*9[ ]+\.arch \.vaes -[ ]*10[ ]+\?\?\?\? 62F26D28[ ]+\{evex\} vaesenc[ ]+%ymm1, %ymm2, %ymm3 -[ ]*10[ ]+DCD9 -[ ]*11[ ]* -[ ]*12[ ]+\.arch \.gfni -[ ]*13[ ]+\?\?\?\? 62F26D2C[ ]+vgf2p8mulb[ ]+%ymm1, %ymm2, %ymm3\{%k4\} -[ ]*13[ ]+CFD9 -[ ]*14[ ]* -[ ]*15[ ]+\.arch \.vpclmulqdq -[ ]*16[ ]+\?\?\?\? 62F36D28[ ]+\{evex\} vpclmulqdq[ ]+\$0, %ymm1, %ymm2, %ymm3 -[ ]*16[ ]+44D900 -[ ]*17[ ]* -[ ]*18[ ]+\.arch generic32 -[ ]*19[ ]+\.arch \.avx512f -[ ]*20[ ]+\{evex\}[ ]+vpermd[ ]+%ymm1, %ymm2, %ymm3 -[ ]*21[ ]+\?\?\?\? C4E26D36[ ]+vpermd[ ]+%ymm1, %ymm2, %ymm3 +[ ]*6[ ]+\?\?\?\? 62F27D08[ ]+vcvtph2ps[ ]+%xmm1, %xmm2 +[ ]*6[ ]+13D1 +[ ]*7[ ]+\?\?\?\? 62F26D08[ ]+vfmadd132ps[ ]+%xmm1, %xmm2, %xmm3 +[ ]*7[ ]+98D9 +[ ]*8[ ]+vgf2p8mulb[ ]+%ymm1, %ymm2, %ymm3\{%k4\} +[ ]*9[ ]+\{evex\} vpclmulqdq[ ]+\$0, %ymm1, %ymm2, %ymm3 +[ ]*10[ ]* +[ ]*11[ ]+\.arch \.vaes +[ ]*12[ ]+\?\?\?\? 62F26D28[ ]+\{evex\} vaesenc[ ]+%ymm1, %ymm2, %ymm3 +[ ]*12[ ]+DCD9 +[ ]*13[ ]* +[ ]*14[ ]+\.arch \.gfni +[ ]*15[ ]+\?\?\?\? 62F26D2C[ ]+vgf2p8mulb[ ]+%ymm1, %ymm2, %ymm3\{%k4\} +[ ]*15[ ]+CFD9 +[ ]*16[ ]* +[ ]*17[ ]+\.arch \.vpclmulqdq +[ ]*18[ ]+\?\?\?\? 62F36D28[ ]+\{evex\} vpclmulqdq[ ]+\$0, %ymm1, %ymm2, %ymm3 +[ ]*18[ ]+44D900 +[ ]*19[ ]* +[ ]*20[ ]+\.arch generic32 +[ ]*21[ ]+\.arch \.avx512f +[ ]*22[ ]+\{evex\}[ ]+vpermd[ ]+%ymm1, %ymm2, %ymm3 +[ ]*23[ ]+\?\?\?\? C4E26D36[ ]+vpermd[ ]+%ymm1, %ymm2, %ymm3 #pass --- a/gas/testsuite/gas/i386/avx512vl-plain.s +++ b/gas/testsuite/gas/i386/avx512vl-plain.s @@ -3,6 +3,8 @@ .arch .avx512vl _start: {evex} vaesenc %ymm1, %ymm2, %ymm3 + vcvtph2ps %xmm1, %xmm2 + vfmadd132ps %xmm1, %xmm2, %xmm3 vgf2p8mulb %ymm1, %ymm2, %ymm3{%k4} {evex} vpclmulqdq $0, %ymm1, %ymm2, %ymm3 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1922,17 +1922,20 @@ vgf2p8affineinvqb, 0x66cf, AVX&GFNI, Mod vgf2p8affineqb, 0x66ce, AVX&GFNI, Modrm|Vex|Space0F3A|Src1VVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vgf2p8mulb, 0x66cf, GFNI&(AVX|AVX512F), Modrm|Vex|EVexDYN|Masking|Space0F38|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -// FSGSBASE, RDRND and F16C +// FSGSBASE and RDRND rdfsbase, 0xf30fae/0, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } rdgsbase, 0xf30fae/1, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } rdrand, 0xfc7/6, RdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } wrfsbase, 0xf30fae/2, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } wrgsbase, 0xf30fae/3, FSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } -vcvtph2ps, 0x6613, F16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } -vcvtph2ps, 0x6613, F16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } -vcvtps2ph, 0x661d, F16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vcvtps2ph, 0x661d, F16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } + +// F16C instructions + +vcvtph2ps, 0x6613, F16C|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } +vcvtph2ps, 0x6613, F16C|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } +vcvtps2ph, 0x661d, F16C|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } +vcvtps2ph, 0x661d, F16C|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } // FMA instructions @@ -2655,15 +2658,9 @@ vcvtdq2pd, 0xF3E6, AVX512VL, Modrm|EVex2 vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } vcvtudq2pd, 0xF37A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2ps, 0x6613, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex128|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } vcvtps2pd, 0x5A, AVX512VL, Modrm|EVex256|Masking|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex128|Masking|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vcvtps2ph, 0x661D, AVX512VL, Modrm|EVex256|Masking|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } - vmovddup, 0xF212, AVX512VL, Modrm|EVex=2|Masking|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } vpdb, 0xf31, AVX512VL, Modrm|EVex128|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }