diff mbox series

[RFA] Fix for mcore simulator

Message ID 1d854df9-b28c-41eb-af7c-e3a423885558@gmail.com
State New
Headers
Series [RFA] Fix for mcore simulator |

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Commit Message

Jeff Law Oct. 4, 2023, 10:09 p.m. UTC 
  I was looking for cases where a GCC patch under evaluation would cause 
test results to change.  Quite surprisingly the mcore-elf port showed 
test differences.   After a fair amount of digging my conclusion was the 
sequences before/after the patch should have been semantically the same.


Of course if the code is supposed to behave the same, then that points 
to problems elsewhere (assembler, linker, simulator).  Sure enough the 
mcore simulator was mis-handling the sign extension instructions.  The 
simulator implementation of sextb is via paired shift-by-24 operations. 
Similarly the simulator implements sexth via paired shift-by-16 operations.

The temporary holding the value was declared as a "long" thus this 
approach worked fine for hosts with a 32 bit wide long and failed 
miserably for hosts with a 64 bit wide long.

This patch makes the shift count automatically adjust based on the size 
of the temporary.  It includes a simple test for sextb and sexth.  I 
have _not_ done a full audit of the mcore simulator for more 32->64 bit 
issues.

This also fixes 443 execution tests in the GCC testsuite ;-)



OK for the trunk?

Thanks,
Jeff

Comments

Nick Clifton Oct. 5, 2023, 10:14 a.m. UTC | #1 
Hi Jeff,

> This patch makes the shift count automatically adjust based on the size of the temporary.  It includes a simple test for sextb and sexth.  I have _not_ done a full audit of 
> the mcore simulator for more 32->64 bit issues.
> 
> This also fixes 443 execution tests in the GCC testsuite ;-)

Yay!

> OK for the trunk?

No - because the sim sources are part of GDB not the binutils, so
you need to post the patch to their mailing list.

But if it helps I would definitely recommend that they approve the patch. :-)

Cheers
   Nick
diff mbox series

Patch

diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 53cfdad050b..48d9ff8645a 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -641,8 +641,8 @@  step_once (SIM_DESC sd, SIM_CPU *cpu)
 	      {
 		long tmp;
 		tmp = gr[RD];
-		tmp <<= 24;
-		tmp >>= 24;
+		tmp <<= (sizeof (tmp) * 8) - 8;
+		tmp >>= (sizeof (tmp) * 8) - 8;
 		gr[RD] = tmp;
 	      }
 	      break;
@@ -653,8 +653,8 @@  step_once (SIM_DESC sd, SIM_CPU *cpu)
 	      {
 		long tmp;
 		tmp = gr[RD];
-		tmp <<= 16;
-		tmp >>= 16;
+		tmp <<= (sizeof (tmp) * 8) - 16;
+		tmp >>= (sizeof (tmp) * 8) - 16;
 		gr[RD] = tmp;
 	      }
 	      break;
diff --git a/sim/testsuite/mcore/sextb.s b/sim/testsuite/mcore/sextb.s
new file mode 100644
index 00000000000..5500f7abe67
--- /dev/null
+++ b/sim/testsuite/mcore/sextb.s
@@ -0,0 +1,25 @@ 
+# check that sext.b/sext.h work correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+	start
+	# Construct -120 using bgeni+addi+sext
+	bgeni	r2, 7
+	addi	r2,8
+	sextb	r2
+
+	# Construct -120 using movi+not
+	movi	r7,119
+	not	r7
+
+	# Compare them, they should be equal
+	cmpne	r2,r7
+	jbt	.L1
+	pass
+.L1:
+	fail
+
+
+
+
diff --git a/sim/testsuite/mcore/sexth.s b/sim/testsuite/mcore/sexth.s
new file mode 100644
index 00000000000..97279c49ed4
--- /dev/null
+++ b/sim/testsuite/mcore/sexth.s
@@ -0,0 +1,27 @@ 
+# check that sext.b/sext.h work correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+	start
+	# Construct -32760 using bgeni+addi+sext
+	bgeni	r2, 15
+	addi	r2,8
+	sexth	r2
+
+	# Construct -32760 using bmask+subi+not
+        bmaski  r7,15
+        subi    r7,8    // 32759 0x7ff7
+	not	r7
+
+
+	# Compare them, they should be equal
+	cmpne	r2,r7
+	jbt	.L1
+	pass
+.L1:
+	fail
+
+
+
+