diff mbox series

[v4,1/7] x86: support for internal 'TILE' feature

Message ID 1d2f32c004a7bd4e35c075699dcf88879400b730.1790705096.git.RohanRadhesh.Shenoy@amd.com
State New
Headers
Series x86: add ACE V1 ISA support |

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Commit Message

Shenoy, Rohan Radhesh Sept. 29, 2026, 6:30 p.m. UTC 
  ACE shares the tile registers and the following instructions with
AMX_TILE:
LDTILECFG, STTILECFG, TILERELEASE, TILEZERO
while the remaining AMX_TILE instructions are not part of ACE.
Add an internal pseudo-ISA bit 'TILE' - to represent this shared subset.
---
 gas/config/tc-i386.c                       | 15 +++++++++++----
 gas/testsuite/gas/i386/x86-64-noamx-tile.l |  2 ++
 gas/testsuite/gas/i386/x86-64-noamx-tile.s |  3 +++
 gas/testsuite/gas/i386/x86-64.exp          |  1 +
 opcodes/i386-gen.c                         |  5 ++++-
 opcodes/i386-opc.h                         |  3 +++
 opcodes/i386-opc.tbl                       |  8 ++++----
 7 files changed, 28 insertions(+), 9 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-noamx-tile.l
 create mode 100644 gas/testsuite/gas/i386/x86-64-noamx-tile.s

Comments

Jan Beulich Oct. 2, 2026, 7:03 a.m. UTC | #1 
On 29.09.2026 20:30, Rohan Shenoy wrote:
> ACE shares the tile registers and the following instructions with
> AMX_TILE:
> LDTILECFG, STTILECFG, TILERELEASE, TILEZERO
> while the remaining AMX_TILE instructions are not part of ACE.
> Add an internal pseudo-ISA bit 'TILE' - to represent this shared subset.

Okay.

Jan
diff mbox series

Patch

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ce9cc8236fa..4c8acb0df5b 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2360,7 +2360,7 @@  cpu_flags_match (const insn_template *t)
 	      || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile
 	      || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr
 	      || any.bitfield.cpumsr_imm || any.bitfield.cpuamx_transpose
-	      || any.bitfield.cpuamx_movrs))
+	      || any.bitfield.cpuamx_movrs || any.bitfield.cputile))
 	{
 	  /* These checks (verifying that APX_F() was properly used in the
 	     opcode table entry) make sure there's no need for an "else" to
@@ -3352,6 +3352,13 @@  static void isa_disable (unsigned int idx)
 
   cpu_arch_isa_flags
     = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable);
+
+  /* TILE is internal. .noamx_tile does not automatically clear it.  */
+  if (!cpu_arch_flags.bitfield.cpuamx_tile)
+    {
+      cpu_arch_flags.bitfield.cputile = 0;
+      cpu_arch_isa_flags.bitfield.cputile = 0;
+    }
 }
 
 static void
@@ -4303,7 +4310,7 @@  install_template (const insn_template *t)
 	   || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
 	   || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)
 	   || maybe_cpu (t, CpuMSR_IMM) || maybe_cpu (t, CpuAMX_TRANSPOSE)
-	   || maybe_cpu (t, CpuAMX_MOVRS))
+	   || maybe_cpu (t, CpuAMX_MOVRS) || maybe_cpu (t, CpuTILE))
 	  && maybe_cpu (t, CpuAPX_F))
 	{
 	  if (need_evex_encoding (t))
@@ -12588,7 +12595,7 @@  output_insn (const struct last_insn *last_insn)
       unsigned int feature_2_used = 0;
 
       if ((i.xstate & xstate_tmm) == xstate_tmm
-	  || is_cpu (&i.tm, CpuAMX_TILE))
+	  || is_cpu (&i.tm, CpuTILE))
 	feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
 
       if (is_cpu (&i.tm, Cpu8087)
@@ -17073,7 +17080,7 @@  static bool check_register (const reg_entry *r)
     return false;
 
   if (r->reg_type.bitfield.tmmword
-      && (!cpu_arch_flags.bitfield.cpuamx_tile
+      && (!cpu_arch_flags.bitfield.cputile
           || flag_code != CODE_64BIT))
     return false;
 
diff --git a/gas/testsuite/gas/i386/x86-64-noamx-tile.l b/gas/testsuite/gas/i386/x86-64-noamx-tile.l
new file mode 100644
index 00000000000..93a3f4b04e5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-noamx-tile.l
@@ -0,0 +1,2 @@ 
+.*: Assembler messages:
+.*:3: Error: `ldtilecfg' is not supported on `.*\.noamx_tile'
diff --git a/gas/testsuite/gas/i386/x86-64-noamx-tile.s b/gas/testsuite/gas/i386/x86-64-noamx-tile.s
new file mode 100644
index 00000000000..398c07a2eee
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-noamx-tile.s
@@ -0,0 +1,3 @@ 
+	.text
+	.arch .noamx_tile
+	ldtilecfg (%rax)
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index eb10d9b8b9f..9e7ac49abd2 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -688,6 +688,7 @@  run_dump_test "x86-64-lfence-ret-d"
 run_dump_test "x86-64-lfence-ret-e"
 run_dump_test "x86-64-lfence-byte"
 run_list_test "x86-64-amx-inval"
+run_list_test "x86-64-noamx-tile"
 run_dump_test "x86-64-amx"
 run_dump_test "x86-64-amx-intel"
 run_dump_test "x86-64-amx-bad"
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index cf37d8786e9..15ba45edd70 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -269,8 +269,10 @@  static const dependency isa_dependencies[] =
     "RTM|HLE" },
   { "TSXLDTRK",
     "RTM" },
-  { "AMX_TILE",
+  { "TILE",
     "XSAVE|64" },
+  { "AMX_TILE",
+    "TILE" },
   { "AMX_INT8",
     "AMX_TILE" },
   { "AMX_BF16",
@@ -488,6 +490,7 @@  static bitfield cpu_flags[] =
   BITFIELD (AMX_MOVRS),
   BITFIELD (AMX_AVX512),
   BITFIELD (AMX_TILE),
+  BITFIELD (TILE),
   BITFIELD (MOVDIRI),
   BITFIELD (MOVDIR64B),
   BITFIELD (ENQCMD),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index cd8f228f5a9..10fc3d3ddb5 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -278,6 +278,8 @@  enum i386_cpu
   CpuAMX_AVX512,
   /* AMX-TILE instructions required */
   CpuAMX_TILE,
+  /* Tile management instructions required (internal). */
+  CpuTILE,
   /* GFNI instructions required */
   CpuGFNI,
   /* VAES instructions required */
@@ -552,6 +554,7 @@  typedef union i386_cpu_flags
       unsigned int cpuamx_movrs:1;
       unsigned int cpuamx_avx512:1;
       unsigned int cpuamx_tile:1;
+      unsigned int cputile:1;
       unsigned int cpugfni:1;
       unsigned int cpuvaes:1;
       unsigned int cpuvpclmulqdq:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5ed809f74af..0801ebba0db 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3241,8 +3241,8 @@  xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {}
 
 // AMX instructions.
 
-ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
-sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+ldtilecfg, 0x49/0, APX_F(TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+sttilecfg, 0x6649/0, APX_F(TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
 
 tcmmimfp16ps, 0x666c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 tcmmrlfp16ps, 0x6c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
@@ -3260,9 +3260,9 @@  tileloaddrs, 0xf24a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoS
 tileloaddrst1, 0x664a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }
 
-tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {}
+tilerelease, 0x49c0, TILE, Vex128|Space0F38|VexW0|NoSuf, {}
 
-tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
+tilezero, 0xf249, TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
 
 <z:pfx, z0:, z1:66>