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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id u18-20020a05600c19d200b0041896d2a05fsm5716638wmq.5.2024.04.19.02.28.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Apr 2024 02:28:49 -0700 (PDT) Message-ID: <117c9c1f-795e-41f9-b582-b8477b42bebd@suse.com> Date: Fri, 19 Apr 2024 11:28:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: Binutils Cc: "H.J. Lu" From: Jan Beulich Subject: [PATCH] x86/Intel: SHLD/SHRD have dual meaning Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL X-Spam-Status: No, score=-3025.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Since we uniformly permit D suffixes in Intel mode whenever in AT&T mode an L suffix may be used, we need to be consistent with this. Take the easy route, despite that still leading to an anomaly which is also visible from the new testcase: shld eax, ecx, 1 shld eax, ecx, cl can mean two things with APX: SHL with a D suffix in NDD EVEX encoding, or the traditional SHLD in legacy encoding. --- The alternative, more intrusive and more risky (in terms of perceived or even real regressions) route would be to mark the few insns which permit suffixes even in Intel syntax, and reject suffix uses when that indicator isn't set. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -5389,7 +5389,7 @@ static void init_globals (void) } /* Helper for md_assemble() to decide whether to prepare for a possible 2nd - parsing pass. Instead of introducing a rarely use new insn attribute this + parsing pass. Instead of introducing a rarely used new insn attribute this utilizes a common pattern between affected templates. It is deemed acceptable that this will lead to unnecessary pass 2 preparations in a limited set of cases. */ @@ -5401,7 +5401,10 @@ static INLINE bool may_need_pass2 (const : (t->opcode_space == SPACE_0F && (t->base_opcode | 1) == 0xbf) || (t->opcode_space == SPACE_BASE - && t->base_opcode == 0x63); + && t->base_opcode == 0x63) + || (intel_syntax /* shld / shrd may mean suffixed shl / shr. */ + && t->opcode_space == SPACE_EVEXMAP4 + && (t->base_opcode | 8) == 0x2c); } #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) --- /dev/null +++ b/gas/testsuite/gas/i386/intel-suffix.d @@ -0,0 +1,34 @@ +#objdump: -dw +#name: Intel syntax w/ suffixes + +.*: +file format .* + +Disassembly of section \.text: +0+0 <.*>: +[ ]*[a-f0-9]+: 0f a4 c8 01[ ]+shld \$0x1,%ecx,%eax +[ ]*[a-f0-9]+: 0f a5 c8[ ]+shld %cl,%ecx,%eax +[ ]*[a-f0-9]+: d1 e1[ ]+shl \$1,%ecx +[ ]*[a-f0-9]+: d3 e1[ ]+shl %cl,%ecx +[ ]*[a-f0-9]+: 62 f4 7c 18 d1 e1[ ]+shl \$1,%ecx,%eax +[ ]*[a-f0-9]+: 62 f4 7c 18 d3 e1[ ]+shl %cl,%ecx,%eax +[ ]*[a-f0-9]+: d1 e1[ ]+shl \$1,%ecx +[ ]*[a-f0-9]+: d3 e1[ ]+shl %cl,%ecx +[ ]*[a-f0-9]+: 62 f4 7c 18 d1 c1[ ]+rol \$1,%ecx,%eax +[ ]*[a-f0-9]+: 62 f4 7c 18 d3 c1[ ]+rol %cl,%ecx,%eax +[ ]*[a-f0-9]+: d1 c1[ ]+rol \$1,%ecx +[ ]*[a-f0-9]+: d3 c1[ ]+rol %cl,%ecx + +0+[0-9a-f]+ <.*>: +[ ]*[a-f0-9]+: 0f ac c8 01[ ]+shrd \$0x1,%ecx,%eax +[ ]*[a-f0-9]+: 0f ad c8[ ]+shrd %cl,%ecx,%eax +[ ]*[a-f0-9]+: d1 e9[ ]+shr \$1,%ecx +[ ]*[a-f0-9]+: d3 e9[ ]+shr %cl,%ecx +[ ]*[a-f0-9]+: 62 f4 7c 18 d1 f9[ ]+sar \$1,%ecx,%eax +[ ]*[a-f0-9]+: 62 f4 7c 18 d3 f9[ ]+sar %cl,%ecx,%eax +[ ]*[a-f0-9]+: d1 f9[ ]+sar \$1,%ecx +[ ]*[a-f0-9]+: d3 f9[ ]+sar %cl,%ecx +[ ]*[a-f0-9]+: 62 f4 7c 18 d1 c9[ ]+ror \$1,%ecx,%eax +[ ]*[a-f0-9]+: 62 f4 7c 18 d3 c9[ ]+ror %cl,%ecx,%eax +[ ]*[a-f0-9]+: d1 c9[ ]+ror \$1,%ecx +[ ]*[a-f0-9]+: d3 c9[ ]+ror %cl,%ecx +#pass --- /dev/null +++ b/gas/testsuite/gas/i386/intel-suffix.s @@ -0,0 +1,39 @@ + .intel_syntax noprefix + .text +left: + shld eax, ecx, 1 + shld eax, ecx, cl + + shld ecx, 1 + shld ecx, cl + + sald eax, ecx, 1 + sald eax, ecx, cl + + sald ecx, 1 + sald ecx, cl + + rold eax, ecx, 1 + rold eax, ecx, cl + + rold ecx, 1 + rold ecx, cl + +right: + shrd eax, ecx, 1 + shrd eax, ecx, cl + + shrd ecx, 1 + shrd ecx, cl + + sard eax, ecx, 1 + sard eax, ecx, cl + + sard ecx, 1 + sard ecx, cl + + rord eax, ecx, 1 + rord eax, ecx, cl + + rord ecx, 1 + rord ecx, cl --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -160,6 +160,7 @@ run_dump_test "x86-64-disp-intel" run_list_test "disp-imm-64" run_dump_test "intel-movs64" run_dump_test "intel-cmps64" +run_dump_test "intel-suffix" run_dump_test "x86-64-disp32" run_dump_test "rexw" run_list_test "x86-64-specific-reg"