diff mbox series

[v4,2/7] x86: decode EVEX 0F38 4B by length

Message ID 0ed0b87d09a08fe6f3093838df68d04491c42ce4.1790705096.git.RohanRadhesh.Shenoy@amd.com
State New
Headers
Series x86: add ACE V1 ISA support |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed

Commit Message

Rohan Shenoy Sept. 29, 2026, 6:30 p.m. UTC 
  Existing decode path ignores entries when L'L is non-zero. This is a
prerequisite for ACE which needs decoding for non-zero L'L in this path.
---
 opcodes/i386-dis-evex-len.h    | 5 +++++
 opcodes/i386-dis-evex-x86-64.h | 5 +++++
 opcodes/i386-dis-evex.h        | 2 +-
 opcodes/i386-dis.c             | 2 ++
 4 files changed, 13 insertions(+), 1 deletion(-)

Comments

Jan Beulich Oct. 2, 2026, 7:14 a.m. UTC | #1 
On 29.09.2026 20:30, Rohan Shenoy wrote:
> Existing decode path ignores entries when L'L is non-zero. This is a
> prerequisite for ACE which needs decoding for non-zero L'L in this path.

Both sentences aren't quite right. How about:

"The existing decode path handles L'L through use of
 USE_X86_64_EVEX_MEM_W_TABLE. For ACE insns at the same major opcode the
 decode step through evex_len_table[] needs to become explicit."

If you're okay with that, I can swap the description while committing.

Jan
Rohan Shenoy Oct. 5, 2026, 6:33 a.m. UTC | #2 
AMD General

> If you're okay with that, I can swap the description while committing.

> Jan

Yes I am okay (even for the subsequent patches you've offered to change while committing). Thanks.

Rohan
diff mbox series

Patch

diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index 370710915de..23e9487ec68 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -51,6 +51,11 @@  static const struct dis386 evex_len_table[][3] = {
     { PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_0_L_2) },
   },
 
+  /* EVEX_LEN_0F384B_X86_64 */
+  {
+    { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+  },
+
   /* EVEX_LEN_0F385A */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex-x86-64.h b/opcodes/i386-dis-evex-x86-64.h
index 93acb0ba18d..8f8f5dfcd96 100644
--- a/opcodes/i386-dis-evex-x86-64.h
+++ b/opcodes/i386-dis-evex-x86-64.h
@@ -3,6 +3,11 @@ 
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F384A_X86_64) },
   },
+  /* X86_64_EVEX_0F384B */
+  {
+    { Bad_Opcode },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F384B_X86_64) },
+  },
   /* X86_64_EVEX_0F386D */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index fe515a01932..52bf0d798ac 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -377,7 +377,7 @@  static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
     { X86_64_TABLE (X86_64_EVEX_0F384A) },
-    { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+    { X86_64_TABLE (X86_64_EVEX_0F384B) },
     { "vrcp14p%XW",	{ XM, EXx }, PREFIX_DATA },
     { "vrcp14s%XW",	{ XMScalar, VexScalar, EXdq }, PREFIX_DATA },
     { "vrsqrt14p%XW",	{ XM, EXx }, 0 },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f7ad933fdb9..95dbf96156f 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1404,6 +1404,7 @@  enum
   X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
 
   X86_64_EVEX_0F384A,
+  X86_64_EVEX_0F384B,
   X86_64_EVEX_0F386D,
   X86_64_EVEX_0F3A07,
   X86_64_EVEX_0F3A77,
@@ -1604,6 +1605,7 @@  enum
   EVEX_LEN_0F381B,
   EVEX_LEN_0F3836,
   EVEX_LEN_0F384A_X86_64_W_0,
+  EVEX_LEN_0F384B_X86_64,
   EVEX_LEN_0F385A,
   EVEX_LEN_0F385B,
   EVEX_LEN_0F386D_X86_64_W_0,