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Mon, 6 Nov 2023 13:13:08 +0000 From: Victor Do Nascimento To: CC: , , Victor Do Nascimento Subject: [PATCH 0/3] aarch64: Add support for the Armv9.4-a LSE128 extension Date: Mon, 6 Nov 2023 13:12:45 +0000 Message-ID: <20231106131301.2576862-1-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B1:EE_|PA6PR08MB10813:EE_|AM2PEPF0001C70E:EE_|AS8PR08MB8246:EE_ X-MS-Office365-Filtering-Correlation-Id: 686182c2-5d3e-4eb9-4177-08dbdeca2548 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: CspzKasyEWdV096YV0NKdU13AB/Qo5uWmvqoqjxfW5laK991slp0h/svrdgp+7RYjdAFksAXnK6L3PGhQkxSm1AUG7BrMFicKYx0jb+s0JINW5GR0oA8QjVfBMG8LYQs+XTVVyA1WYcmHzSavmjLtfAfOVYoPXoJEikNjRseaG8harE7OK/Z/AD2F8+4MrjKOLnwOZoS1/DTmfCu62bRWq3ZCs8rjW+CUs3QO2k2PoVhBphsU4aysK5dEPz019idEfO60hktg1/qazJvgu+yCv60+akK2WAYHB01d461XQkj+GUsx+76AzYwhfNcTpSkUnZhV9T9lnMQZTCdRTy0L1v+VwziFqksI7VjLO2QYhDIGxCvzFhtON9cTRX/vZuSS/eGAF7sxPY1lsgmMAFac5sNGcasEGidGnFA/6GBObW66T+w/2h8Vr0ChoQ3nNH5Hc/uXi2uaGr1tWsY9Frz6v2Pph1MLR4SRjIJ6DxO+jHh/sJ1XLVhoIVd34+T6JXTYDwGpirHQSvxQLFZ0IKjfhzSIa+KKaBCMySDVS7PdMjkHPBsBf059WzL6jOXn2wTKfheeEHAjRwihutdCeq1F47UAFvjIcRxvVXA4K9OHsA17Z+9YxXi9PSAkGPJ44ULlwXtlZlTziM8Zx2hUV7eXO4cZY5qFV6WAxpKlKZhcZVCrtMu5P+on0Dt+HF7rsiMj58Q49730chC9HaGiVCOJ/JxC9oHFCQoQsTxI2f9AdZqIKAJnVlg01448s2lSEeGUS4mAv7spLKSkz1AAVZnYg== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C70E.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8246 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Add support for the 128-bit Atomic Instructions extension, also known and referred to as LSE128 and which is made optional from Armv9.4-a onward. The feature is enabled by passing the +lse128 option to -march (eg: -march=armv9.4-a+lse128) or using the ".arch_extension lse128" directive in the assembly file. Given that the implementation of the LSE128 feature requires that the LSE feature is also present, the +lse128 option also implicitly enables the +lse feature. LSE128 adds support for the following new 128-bit atomic instructions: * Atomic bit clear on quadword in memory (ldclrp{a|l|al}); * Atomic bit set on quadword in memory (ldsetp{a|l|al}); * Swap quadword in memory (swpp{a|l|al}); Regression testing for aarch64-none-linux-gnu target with no regressions. Victor Do Nascimento (3): aarch64: Add LSE128 instruction operand support aarch64: Add arch support for LSE128 extension aarch64: Add LSE128 instructions gas/config/tc-aarch64.c | 6 +++++ gas/doc/c-aarch64.texi | 2 ++ gas/testsuite/gas/aarch64/lse128-atomic.d | 32 ++++++++++++++++++++++ gas/testsuite/gas/aarch64/lse128-atomic.s | 33 +++++++++++++++++++++++ include/opcode/aarch64.h | 5 ++++ opcodes/aarch64-opc.c | 4 +++ opcodes/aarch64-opc.h | 2 ++ opcodes/aarch64-tbl.h | 20 ++++++++++++++ 8 files changed, 104 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.d create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.s