diff mbox

[v2,6/6,powerpc] Rename fegetenv_status to fegetenv_control

Message ID 1568918810-20393-7-git-send-email-pc@us.ibm.com
State Superseded
Headers

Commit Message

Paul A. Clarke Sept. 19, 2019, 6:46 p.m. UTC 
  From: "Paul A. Clarke" <pc@us.ibm.com>

fegetenv_status is used variously to retrieve the FPSCR exception enable
bits, rounding mode bits, or both.  These are referred to as the control
bits in the POWER ISA.  FPSCR status bits are also returned by the
'mffs' and 'mffsl' instructions, but they are uniformly ignored by all
uses of fegetenv_status.  Change the name to be reflective of its
current and expected use.

2019-09-19  Paul A. Clarke  <pc@us.ibm.com>

	* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): Rename to
	fegetenv_control.
	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
	rename of fegetenv_status to fegetenv_control.
	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
	* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise.
	* sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Likewise.
	* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise.
	* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
---
v2: This is a new patch in the series.

 sysdeps/powerpc/fpu/fedisblxcpt.c | 2 +-
 sysdeps/powerpc/fpu/feenablxcpt.c | 2 +-
 sysdeps/powerpc/fpu/fegetexcept.c | 2 +-
 sysdeps/powerpc/fpu/fegetmode.c   | 2 +-
 sysdeps/powerpc/fpu/fenv_libc.h   | 6 +++---
 sysdeps/powerpc/fpu/fesetenv.c    | 2 +-
 sysdeps/powerpc/fpu/fesetmode.c   | 2 +-
 7 files changed, 9 insertions(+), 9 deletions(-)

Comments

Paul E Murphy Sept. 23, 2019, 4:21 p.m. UTC | #1 
On 9/19/19 1:46 PM, Paul A. Clarke wrote:
> From: "Paul A. Clarke" <pc@us.ibm.com>
> 
> fegetenv_status is used variously to retrieve the FPSCR exception enable
> bits, rounding mode bits, or both.  These are referred to as the control
> bits in the POWER ISA.  FPSCR status bits are also returned by the
> 'mffs' and 'mffsl' instructions, but they are uniformly ignored by all
> uses of fegetenv_status.  Change the name to be reflective of its
> current and expected use.
> 
> 2019-09-19  Paul A. Clarke  <pc@us.ibm.com>
> 
> 	* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): Rename to
> 	fegetenv_control.
> 	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
> 	rename of fegetenv_status to fegetenv_control.
> 	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
> 	* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise.
> 	* sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Likewise.
> 	* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise.
> 	* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
> ---
> v2: This is a new patch in the series.

OK.

Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>

> diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c
> index 0e0a01c..65c5ebe 100644
> --- a/sysdeps/powerpc/fpu/fegetmode.c
> +++ b/sysdeps/powerpc/fpu/fegetmode.c
> @@ -21,6 +21,6 @@
>   int
>   fegetmode (femode_t *modep)
>   {
> -  *modep = fegetenv_status ();
> +  *modep = fegetenv_control ();
>     return 0;
>   }

Slightly off-topic, is fegetmode documented?
Paul A. Clarke Sept. 23, 2019, 5:48 p.m. UTC | #2 
On 9/23/19 11:21 AM, Paul E Murphy wrote:
> On 9/19/19 1:46 PM, Paul A. Clarke wrote:
>> fegetenv_status is used variously to retrieve the FPSCR exception enable
>> bits, rounding mode bits, or both.  These are referred to as the control
>> bits in the POWER ISA.  FPSCR status bits are also returned by the
>> 'mffs' and 'mffsl' instructions, but they are uniformly ignored by all
>> uses of fegetenv_status.  Change the name to be reflective of its
>> current and expected use.
>>
>> 2019-09-19  Paul A. Clarke  <pc@us.ibm.com>
>>
>>     * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): Rename to
>>     fegetenv_control.
>>     * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
>>     rename of fegetenv_status to fegetenv_control.
>>     * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
>>     * sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise.
>>     * sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Likewise.
>>     * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise.
>>     * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
>> ---
>> v2: This is a new patch in the series.
> 
> OK.

Thanks!

> Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
> 
>> diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c
>> index 0e0a01c..65c5ebe 100644
>> --- a/sysdeps/powerpc/fpu/fegetmode.c
>> +++ b/sysdeps/powerpc/fpu/fegetmode.c
>> @@ -21,6 +21,6 @@
>>   int
>>   fegetmode (femode_t *modep)
>>   {
>> -  *modep = fegetenv_status ();
>> +  *modep = fegetenv_control ();
>>     return 0;
>>   }
> 
> Slightly off-topic, is fegetmode documented?

Again, not an expert here, but "git blame math/fegetmode.c" shows this:
--
commit ec94343f592df68ba1ba49bb2c558f7d2629387c
Author: Joseph Myers <joseph@codesourcery.com>
Date:   Wed Sep 7 16:40:09 2016 +0000

    Add femode_t functions.
    
    TS 18661-1 defines a type femode_t to represent the set of dynamic
    floating-point control modes (such as the rounding mode and trap
    enablement modes), and functions fegetmode and fesetmode to manipulate
    those modes (without affecting other state such as the raised
    exception flags) and a corresponding macro FE_DFL_MODE.
[...]
--

PC
diff mbox

Patch

diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
index 0d9bf00..870cfc8 100644
--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
@@ -26,7 +26,7 @@  fedisableexcept (int excepts)
   int result, new;
 
   /* Get current exception mask to return.  */
-  fe.fenv = curr.fenv = fegetenv_status ();
+  fe.fenv = curr.fenv = fegetenv_control ();
   result = fenv_reg_to_exceptions (fe.l);
 
   if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
index cf670b8..43f6482 100644
--- a/sysdeps/powerpc/fpu/feenablxcpt.c
+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
@@ -26,7 +26,7 @@  feenableexcept (int excepts)
   int result, new;
 
   /* Get current exception mask to return.  */
-  fe.fenv = curr.fenv = fegetenv_status ();
+  fe.fenv = curr.fenv = fegetenv_control ();
   result = fenv_reg_to_exceptions (fe.l);
 
   if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c
index bd27a80..179e3c4 100644
--- a/sysdeps/powerpc/fpu/fegetexcept.c
+++ b/sysdeps/powerpc/fpu/fegetexcept.c
@@ -24,7 +24,7 @@  __fegetexcept (void)
 {
   fenv_union_t fe;
 
-  fe.fenv = fegetenv_status ();
+  fe.fenv = fegetenv_control ();
 
   return fenv_reg_to_exceptions (fe.l);
 }
diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c
index 0e0a01c..65c5ebe 100644
--- a/sysdeps/powerpc/fpu/fegetmode.c
+++ b/sysdeps/powerpc/fpu/fegetmode.c
@@ -21,6 +21,6 @@ 
 int
 fegetmode (femode_t *modep)
 {
-  *modep = fegetenv_status ();
+  *modep = fegetenv_control ();
   return 0;
 }
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index 3b91340..231d264 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -68,7 +68,7 @@  extern const fenv_t *__fe_mask_env (void) attribute_hidden;
    'mffs' on architectures older than "power9" because the additional
    bits set for 'mffsl' are "don't care" for 'mffs'.  'mffs' is a superset
    of 'mffsl'.  */
-#define fegetenv_status()					\
+#define fegetenv_control()					\
   ({register double __fr;						\
     __asm__ __volatile__ (						\
       ".machine push; .machine \"power9\"; mffsl %0; .machine pop"	\
@@ -92,7 +92,7 @@  extern const fenv_t *__fe_mask_env (void) attribute_hidden;
     __fr.fenv;								\
   })
 
-/* Like fegetenv_status, but also sets the rounding mode.  */
+/* Like fegetenv_control, but also sets the rounding mode.  */
 #ifdef _ARCH_PWR9
 #define fegetenv_and_set_rn(rn) __fe_mffscrn (rn)
 #else
@@ -123,7 +123,7 @@  extern const fenv_t *__fe_mask_env (void) attribute_hidden;
 
 /* Set the last 2 nibbles of the FPSCR, which contain the
    exception enables and the rounding mode.
-   'fegetenv_status' retrieves these bits by reading the FPSCR.  */
+   'fegetenv_control' retrieves these bits by reading the FPSCR.  */
 #define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env));
 
 /* This very handy macro:
diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
index 949d916..fc7b819 100644
--- a/sysdeps/powerpc/fpu/fesetenv.c
+++ b/sysdeps/powerpc/fpu/fesetenv.c
@@ -26,7 +26,7 @@  __fesetenv (const fenv_t *envp)
 
   /* get the currently set exceptions.  */
   new.fenv = *envp;
-  old.fenv = fegetenv_status ();
+  old.fenv = fegetenv_control ();
 
   __TEST_AND_EXIT_NON_STOP (old.l, new.l);
   __TEST_AND_ENTER_NON_STOP (old.l, new.l);
diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c
index 90d86a9..1e9a874 100644
--- a/sysdeps/powerpc/fpu/fesetmode.c
+++ b/sysdeps/powerpc/fpu/fesetmode.c
@@ -27,7 +27,7 @@  fesetmode (const femode_t *modep)
   /* Logic regarding enabled exceptions as in fesetenv.  */
 
   new.fenv = *modep;
-  old.fenv = fegetenv_status ();
+  old.fenv = fegetenv_control ();
   new.l = (new.l & ~FPSCR_STATUS_MASK) | (old.l & FPSCR_STATUS_MASK);
 
   if (old.l == new.l)