diff mbox

[v3,5/6] Implement support for recording vector data transfer instructions

Message ID 1407935535-27978-6-git-send-email-omair.javaid@linaro.org
State Committed
Headers

Commit Message

Omair Javaid Aug. 13, 2014, 1:12 p.m. UTC 
  gdb:

2014-08-13  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (arm_record_vdata_transfer_insn): Added record handler for
	vector data transfer instructions.
	(arm_record_coproc_data_proc): Updated.

---
 gdb/arm-tdep.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 97 insertions(+), 1 deletion(-)

Comments

Will Newton Aug. 13, 2014, 2:10 p.m. UTC | #1 
On 13 August 2014 14:12, Omair Javaid <omair.javaid@linaro.org> wrote:
> gdb:
>
> 2014-08-13  Omair Javaid  <omair.javaid@linaro.org>
>
>         * arm-tdep.c (arm_record_vdata_transfer_insn): Added record handler for
>         vector data transfer instructions.
>         (arm_record_coproc_data_proc): Updated.
>
> ---
>  gdb/arm-tdep.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 97 insertions(+), 1 deletion(-)

Looks ok to me.

> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
> index 315b5b0..7f651bc 100644
> --- a/gdb/arm-tdep.c
> +++ b/gdb/arm-tdep.c
> @@ -11990,6 +11990,102 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
>    return -1;
>  }
>
> +/* Record handler for vector data transfer instructions.  */
> +
> +static int
> +arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
> +{
> +  uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
> +  uint32_t record_buf[4];
> +
> +  const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
> +  reg_t = bits (arm_insn_r->arm_insn, 12, 15);
> +  reg_v = bits (arm_insn_r->arm_insn, 21, 23);
> +  bits_a = bits (arm_insn_r->arm_insn, 21, 23);
> +  bit_l = bit (arm_insn_r->arm_insn, 20);
> +  bit_c = bit (arm_insn_r->arm_insn, 8);
> +
> +  /* Handle VMOV instruction.  */
> +  if (bit_l && bit_c)
> +    {
> +      record_buf[0] = reg_t;
> +      arm_insn_r->reg_rec_count = 1;
> +    }
> +  else if (bit_l && !bit_c)
> +    {
> +      /* Handle VMOV instruction.  */
> +      if (bits_a == 0x00)
> +        {
> +          if (bit (arm_insn_r->arm_insn, 20))
> +            record_buf[0] = reg_t;
> +          else
> +            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
> +                            (reg_v << 1));
> +
> +          arm_insn_r->reg_rec_count = 1;
> +        }
> +      /* Handle VMRS instruction.  */
> +      else if (bits_a == 0x07)
> +        {
> +          if (reg_t == 15)
> +            reg_t = ARM_PS_REGNUM;
> +
> +          record_buf[0] = reg_t;
> +          arm_insn_r->reg_rec_count = 1;
> +        }
> +    }
> +  else if (!bit_l && !bit_c)
> +    {
> +      /* Handle VMOV instruction.  */
> +      if (bits_a == 0x00)
> +        {
> +          if (bit (arm_insn_r->arm_insn, 20))
> +            record_buf[0] = reg_t;
> +          else
> +            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
> +                            (reg_v << 1));
> +
> +          arm_insn_r->reg_rec_count = 1;
> +        }
> +      /* Handle VMSR instruction.  */
> +      else if (bits_a == 0x07)
> +        {
> +          record_buf[0] = ARM_FPSCR_REGNUM;
> +          arm_insn_r->reg_rec_count = 1;
> +        }
> +    }
> +  else if (!bit_l && bit_c)
> +    {
> +      /* Handle VMOV instruction.  */
> +      if (!(bits_a & 0x04))
> +        {
> +          record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
> +                          + ARM_D0_REGNUM;
> +          arm_insn_r->reg_rec_count = 1;
> +        }
> +      /* Handle VDUP instruction.  */
> +      else
> +        {
> +          if (bit (arm_insn_r->arm_insn, 21))
> +            {
> +              reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
> +              record_buf[0] = reg_v + ARM_D0_REGNUM;
> +              record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
> +              arm_insn_r->reg_rec_count = 2;
> +            }
> +          else
> +            {
> +              reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
> +              record_buf[0] = reg_v + ARM_D0_REGNUM;
> +              arm_insn_r->reg_rec_count = 1;
> +            }
> +        }
> +    }
> +
> +  REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
> +  return 0;
> +}
> +
>  /* Record handler for extension register load/store instructions.  */
>
>  static int
> @@ -12467,7 +12563,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
>
>        /* Advanced SIMD, VFP instructions.  */
>        if (!op1_sbit && op)
> -        return arm_record_unsupported_insn (arm_insn_r);
> +        return arm_record_vdata_transfer_insn (arm_insn_r);
>      }
>    else
>      {
> --
> 1.9.1
>
Omair Javaid Aug. 27, 2014, 9:09 a.m. UTC | #2 
On 13 August 2014 19:10, Will Newton <will.newton@linaro.org> wrote:
> On 13 August 2014 14:12, Omair Javaid <omair.javaid@linaro.org> wrote:
>> gdb:
>>
>> 2014-08-13  Omair Javaid  <omair.javaid@linaro.org>
>>
>>         * arm-tdep.c (arm_record_vdata_transfer_insn): Added record handler for
>>         vector data transfer instructions.
>>         (arm_record_coproc_data_proc): Updated.
>>
>> ---
>>  gdb/arm-tdep.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 97 insertions(+), 1 deletion(-)
>
> Looks ok to me.
>
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index 315b5b0..7f651bc 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -11990,6 +11990,102 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
>>    return -1;
>>  }
>>
>> +/* Record handler for vector data transfer instructions.  */
>> +
>> +static int
>> +arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
>> +{
>> +  uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
>> +  uint32_t record_buf[4];
>> +
>> +  const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
>> +  reg_t = bits (arm_insn_r->arm_insn, 12, 15);
>> +  reg_v = bits (arm_insn_r->arm_insn, 21, 23);
>> +  bits_a = bits (arm_insn_r->arm_insn, 21, 23);
>> +  bit_l = bit (arm_insn_r->arm_insn, 20);
>> +  bit_c = bit (arm_insn_r->arm_insn, 8);
>> +
>> +  /* Handle VMOV instruction.  */
>> +  if (bit_l && bit_c)
>> +    {
>> +      record_buf[0] = reg_t;
>> +      arm_insn_r->reg_rec_count = 1;
>> +    }
>> +  else if (bit_l && !bit_c)
>> +    {
>> +      /* Handle VMOV instruction.  */
>> +      if (bits_a == 0x00)
>> +        {
>> +          if (bit (arm_insn_r->arm_insn, 20))
>> +            record_buf[0] = reg_t;
>> +          else
>> +            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
>> +                            (reg_v << 1));
>> +
>> +          arm_insn_r->reg_rec_count = 1;
>> +        }
>> +      /* Handle VMRS instruction.  */
>> +      else if (bits_a == 0x07)
>> +        {
>> +          if (reg_t == 15)
>> +            reg_t = ARM_PS_REGNUM;
>> +
>> +          record_buf[0] = reg_t;
>> +          arm_insn_r->reg_rec_count = 1;
>> +        }
>> +    }
>> +  else if (!bit_l && !bit_c)
>> +    {
>> +      /* Handle VMOV instruction.  */
>> +      if (bits_a == 0x00)
>> +        {
>> +          if (bit (arm_insn_r->arm_insn, 20))
>> +            record_buf[0] = reg_t;
>> +          else
>> +            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
>> +                            (reg_v << 1));
>> +
>> +          arm_insn_r->reg_rec_count = 1;
>> +        }
>> +      /* Handle VMSR instruction.  */
>> +      else if (bits_a == 0x07)
>> +        {
>> +          record_buf[0] = ARM_FPSCR_REGNUM;
>> +          arm_insn_r->reg_rec_count = 1;
>> +        }
>> +    }
>> +  else if (!bit_l && bit_c)
>> +    {
>> +      /* Handle VMOV instruction.  */
>> +      if (!(bits_a & 0x04))
>> +        {
>> +          record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
>> +                          + ARM_D0_REGNUM;
>> +          arm_insn_r->reg_rec_count = 1;
>> +        }
>> +      /* Handle VDUP instruction.  */
>> +      else
>> +        {
>> +          if (bit (arm_insn_r->arm_insn, 21))
>> +            {
>> +              reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
>> +              record_buf[0] = reg_v + ARM_D0_REGNUM;
>> +              record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
>> +              arm_insn_r->reg_rec_count = 2;
>> +            }
>> +          else
>> +            {
>> +              reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
>> +              record_buf[0] = reg_v + ARM_D0_REGNUM;
>> +              arm_insn_r->reg_rec_count = 1;
>> +            }
>> +        }
>> +    }
>> +
>> +  REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
>> +  return 0;
>> +}
>> +
>>  /* Record handler for extension register load/store instructions.  */
>>
>>  static int
>> @@ -12467,7 +12563,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
>>
>>        /* Advanced SIMD, VFP instructions.  */
>>        if (!op1_sbit && op)
>> -        return arm_record_unsupported_insn (arm_insn_r);
>> +        return arm_record_vdata_transfer_insn (arm_insn_r);
>>      }
>>    else
>>      {
>> --
>> 1.9.1
>>
>
>
>
> --
> Will Newton
> Toolchain Working Group, Linaro

Ping! Kindly provide your feedback and help me approve this patch series.
Pedro Alves Aug. 27, 2014, 10:19 a.m. UTC | #3 
On 08/13/2014 03:10 PM, Will Newton wrote:
> On 13 August 2014 14:12, Omair Javaid <omair.javaid@linaro.org> wrote:
>> gdb:
>>
>> 2014-08-13  Omair Javaid  <omair.javaid@linaro.org>
>>
>>         * arm-tdep.c (arm_record_vdata_transfer_insn): Added record handler for
>>         vector data transfer instructions.
>>         (arm_record_coproc_data_proc): Updated.
>>
>> ---
>>  gdb/arm-tdep.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 97 insertions(+), 1 deletion(-)
> 
> Looks ok to me.

This is OK then.

Thanks,
Pedro Alves
diff mbox

Patch

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 315b5b0..7f651bc 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11990,6 +11990,102 @@  arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
   return -1;
 }
 
+/* Record handler for vector data transfer instructions.  */
+
+static int
+arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
+{
+  uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
+  uint32_t record_buf[4];
+
+  const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch);
+  reg_t = bits (arm_insn_r->arm_insn, 12, 15);
+  reg_v = bits (arm_insn_r->arm_insn, 21, 23);
+  bits_a = bits (arm_insn_r->arm_insn, 21, 23);
+  bit_l = bit (arm_insn_r->arm_insn, 20);
+  bit_c = bit (arm_insn_r->arm_insn, 8);
+
+  /* Handle VMOV instruction.  */
+  if (bit_l && bit_c)
+    {
+      record_buf[0] = reg_t;
+      arm_insn_r->reg_rec_count = 1;
+    }
+  else if (bit_l && !bit_c)
+    {
+      /* Handle VMOV instruction.  */
+      if (bits_a == 0x00)
+        {
+          if (bit (arm_insn_r->arm_insn, 20))
+            record_buf[0] = reg_t;
+          else
+            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
+                            (reg_v << 1));
+
+          arm_insn_r->reg_rec_count = 1;
+        }
+      /* Handle VMRS instruction.  */
+      else if (bits_a == 0x07)
+        {
+          if (reg_t == 15)
+            reg_t = ARM_PS_REGNUM;
+
+          record_buf[0] = reg_t;
+          arm_insn_r->reg_rec_count = 1;
+        }
+    }
+  else if (!bit_l && !bit_c)
+    {
+      /* Handle VMOV instruction.  */
+      if (bits_a == 0x00)
+        {
+          if (bit (arm_insn_r->arm_insn, 20))
+            record_buf[0] = reg_t;
+          else
+            record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) |
+                            (reg_v << 1));
+
+          arm_insn_r->reg_rec_count = 1;
+        }
+      /* Handle VMSR instruction.  */
+      else if (bits_a == 0x07)
+        {
+          record_buf[0] = ARM_FPSCR_REGNUM;
+          arm_insn_r->reg_rec_count = 1;
+        }
+    }
+  else if (!bit_l && bit_c)
+    {
+      /* Handle VMOV instruction.  */
+      if (!(bits_a & 0x04))
+        {
+          record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4))
+                          + ARM_D0_REGNUM;
+          arm_insn_r->reg_rec_count = 1;
+        }
+      /* Handle VDUP instruction.  */
+      else
+        {
+          if (bit (arm_insn_r->arm_insn, 21))
+            {
+              reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
+              record_buf[0] = reg_v + ARM_D0_REGNUM;
+              record_buf[1] = reg_v + ARM_D0_REGNUM + 1;
+              arm_insn_r->reg_rec_count = 2;
+            }
+          else
+            {
+              reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4);
+              record_buf[0] = reg_v + ARM_D0_REGNUM;
+              arm_insn_r->reg_rec_count = 1;
+            }
+        }
+    }
+
+  REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf);
+  return 0;
+}
+
 /* Record handler for extension register load/store instructions.  */
 
 static int
@@ -12467,7 +12563,7 @@  arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
 
       /* Advanced SIMD, VFP instructions.  */
       if (!op1_sbit && op)
-        return arm_record_unsupported_insn (arm_insn_r);
+        return arm_record_vdata_transfer_insn (arm_insn_r);
     }
   else
     {