diff mbox series

[2/2] riscv-cores.def: Add Allwinner D1 core

Message ID 20220613132042.2972081-2-christoph.muellner@vrull.eu
State New
Headers
Series [1/2] riscv-cores.def: Fix description of RISCV_CORE() macro |

Commit Message

Christoph Müllner June 13, 2022, 1:20 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

This adds Allwinner's D1 to the list of known cores.
The Allwinner includes a single-core XuanTie C906 and is available
for quite some time. Note, that the tuning struct for the C906
is already part of GCC.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-cores.def | 2 ++
 1 file changed, 2 insertions(+)

Comments

Christoph Müllner June 15, 2022, 8:30 a.m. UTC | #1 
On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This adds Allwinner's D1 to the list of known cores.
> The Allwinner includes a single-core XuanTie C906 and is available
> for quite some time. Note, that the tuning struct for the C906
> is already part of GCC.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
>  gcc/config/riscv/riscv-cores.def | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> index 60bcadbb034..dd97ece376f 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
>  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
>  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
>
> +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")


I just realized that this lacks a test case (other -mcpu=... entries have one).
And the core string is wrong (s/thead-c906/allwinner-d1).
I will send a v2.

> +
>  #undef RISCV_CORE
> --
> 2.35.3
>
Philipp Tomsich June 15, 2022, 8:39 a.m. UTC | #2 
On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> <christoph.muellner@vrull.eu> wrote:
> >
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This adds Allwinner's D1 to the list of known cores.
> > The Allwinner includes a single-core XuanTie C906 and is available
> > for quite some time. Note, that the tuning struct for the C906
> > is already part of GCC.
> >
> > gcc/ChangeLog:
> >
> >         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > ---
> >  gcc/config/riscv/riscv-cores.def | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> > index 60bcadbb034..dd97ece376f 100644
> > --- a/gcc/config/riscv/riscv-cores.def
> > +++ b/gcc/config/riscv/riscv-cores.def
> > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
> >  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
> >  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
> >
> > +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
>
>
> I just realized that this lacks a test case (other -mcpu=... entries have one).
> And the core string is wrong (s/thead-c906/allwinner-d1).
> I will send a v2.

Is the D1 different from the C906? I thought the D1 was using the C906 core?

Philipp.
Christoph Müllner June 15, 2022, 8:55 a.m. UTC | #3 
On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
> <christoph.muellner@vrull.eu> wrote:
> >
> > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> > <christoph.muellner@vrull.eu> wrote:
> > >
> > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > >
> > > This adds Allwinner's D1 to the list of known cores.
> > > The Allwinner includes a single-core XuanTie C906 and is available
> > > for quite some time. Note, that the tuning struct for the C906
> > > is already part of GCC.
> > >
> > > gcc/ChangeLog:
> > >
> > >         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
> > >
> > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > ---
> > >  gcc/config/riscv/riscv-cores.def | 2 ++
> > >  1 file changed, 2 insertions(+)
> > >
> > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> > > index 60bcadbb034..dd97ece376f 100644
> > > --- a/gcc/config/riscv/riscv-cores.def
> > > +++ b/gcc/config/riscv/riscv-cores.def
> > > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
> > >  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
> > >  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
> > >
> > > +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
> >
> >
> > I just realized that this lacks a test case (other -mcpu=... entries have one).
> > And the core string is wrong (s/thead-c906/allwinner-d1).
> > I will send a v2.
>
> Is the D1 different from the C906? I thought the D1 was using the C906 core?

Yes, that's the case.
I'll stick with "thead-c906" as core name for the v2.
Thanks!
Philipp Tomsich June 15, 2022, 8:56 a.m. UTC | #4 
Please update the commit message to reflect this.

On Wed, 15 Jun 2022 at 10:56, Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
> On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > On Wed, 15 Jun 2022 at 10:30, Christoph Müllner
> > <christoph.muellner@vrull.eu> wrote:
> > >
> > > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
> > > <christoph.muellner@vrull.eu> wrote:
> > > >
> > > > From: Christoph Müllner <christoph.muellner@vrull.eu>
> > > >
> > > > This adds Allwinner's D1 to the list of known cores.
> > > > The Allwinner includes a single-core XuanTie C906 and is available
> > > > for quite some time. Note, that the tuning struct for the C906
> > > > is already part of GCC.
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > >         * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
> > > >
> > > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> > > > ---
> > > >  gcc/config/riscv/riscv-cores.def | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > >
> > > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> > > > index 60bcadbb034..dd97ece376f 100644
> > > > --- a/gcc/config/riscv/riscv-cores.def
> > > > +++ b/gcc/config/riscv/riscv-cores.def
> > > > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
> > > >  RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
> > > >  RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
> > > >
> > > > +RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
> > >
> > >
> > > I just realized that this lacks a test case (other -mcpu=... entries have one).
> > > And the core string is wrong (s/thead-c906/allwinner-d1).
> > > I will send a v2.
> >
> > Is the D1 different from the C906? I thought the D1 was using the C906 core?
>
> Yes, that's the case.
> I'll stick with "thead-c906" as core name for the v2.
> Thanks!
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 60bcadbb034..dd97ece376f 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -44,4 +44,6 @@  RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
+RISCV_CORE("thead-c906",      "rv64imafdc", "thead-c906")
+
 #undef RISCV_CORE