diff mbox series

[3/3,AArch32] use canonical ordering for complex mul, fma and fms

Message ID 20211217154310.GA9498@arm.com
State Committed
Headers
Series [1/3] middle-end vect: Simplify and extend the complex numbers validation routines. |

Commit Message

Tamar Christina Dec. 17, 2021, 3:43 p.m. UTC 
  Hi All,

After the first patch in the series this updates the optabs to expect the
canonical sequence.

Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.

Ok for master? and backport along with the first patch?

Thanks,
Tamar

gcc/ChangeLog:

	PR tree-optimization/102819
	PR tree-optimization/103169
	* config/arm/neon.md (cmul<conj_op><mode>3): Use canon order.
	* config/arm/vec-common.md (cmul<conj_op><mode>3,
	cml<fcmac1><conj_op><mode>4): Likewise.

--- inline copy of patch -- 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 8b0a396947cc8e7345f178b926128d7224fb218a..2b6ae67a7ec6bef505c2eaef0ec495d14c656495 100644


--

Comments

Tamar Christina Dec. 20, 2021, 4:22 p.m. UTC | #1 
Updated version of patch following AArch64 review.

Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.

Ok for master? and backport along with the first patch?

Thanks,
Tamar

gcc/ChangeLog:

	PR tree-optimization/102819
	PR tree-optimization/103169
	* config/arm/vec-common.md (cml<fcmac1><conj_op><mode>4): Use
	canonical order.

--- inline copy of patch ---

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index e71d9b3811fde62159f5c21944fef9fe3f97b4bd..eab77ac8decce76d70f5b2594f4439e6ed363e6e 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -265,18 +265,18 @@ (define_expand "arm_vcmla<rot><mode>"
 ;; remainder.  Because of this, expand early.
 (define_expand "cml<fcmac1><conj_op><mode>4"
   [(set (match_operand:VF 0 "register_operand")
-	(plus:VF (match_operand:VF 1 "register_operand")
-		 (unspec:VF [(match_operand:VF 2 "register_operand")
-			     (match_operand:VF 3 "register_operand")]
-			    VCMLA_OP)))]
+	(plus:VF (unspec:VF [(match_operand:VF 1 "register_operand")
+			     (match_operand:VF 2 "register_operand")]
+			    VCMLA_OP)
+		 (match_operand:VF 3 "register_operand")))]
   "(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT
 		      && ARM_HAVE_<MODE>_ARITH)) && !BYTES_BIG_ENDIAN"
 {
   rtx tmp = gen_reg_rtx (<MODE>mode);
-  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[1],
-					     operands[3], operands[2]));
+  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[3],
+					     operands[2], operands[1]));
   emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], tmp,
-					     operands[3], operands[2]));
+					     operands[2], operands[1]));
   DONE;
 })
Tamar Christina Jan. 11, 2022, 7:10 a.m. UTC | #2 
ping

> -----Original Message-----
> From: Tamar Christina
> Sent: Monday, December 20, 2021 4:22 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd <nd@arm.com>; Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; nickc@redhat.com; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>
> Subject: RE: [3/3 PATCH][AArch32] use canonical ordering for complex mul,
> fma and fms
> 
> Updated version of patch following AArch64 review.
> 
> Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.
> 
> Ok for master? and backport along with the first patch?
> 
> Thanks,
> Tamar
> 
> gcc/ChangeLog:
> 
> 	PR tree-optimization/102819
> 	PR tree-optimization/103169
> 	* config/arm/vec-common.md (cml<fcmac1><conj_op><mode>4):
> Use
> 	canonical order.
> 
> --- inline copy of patch ---
> 
> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> common.md index
> e71d9b3811fde62159f5c21944fef9fe3f97b4bd..eab77ac8decce76d70f5b2594f
> 4439e6ed363e6e 100644
> --- a/gcc/config/arm/vec-common.md
> +++ b/gcc/config/arm/vec-common.md
> @@ -265,18 +265,18 @@ (define_expand "arm_vcmla<rot><mode>"
>  ;; remainder.  Because of this, expand early.
>  (define_expand "cml<fcmac1><conj_op><mode>4"
>    [(set (match_operand:VF 0 "register_operand")
> -	(plus:VF (match_operand:VF 1 "register_operand")
> -		 (unspec:VF [(match_operand:VF 2 "register_operand")
> -			     (match_operand:VF 3 "register_operand")]
> -			    VCMLA_OP)))]
> +	(plus:VF (unspec:VF [(match_operand:VF 1 "register_operand")
> +			     (match_operand:VF 2 "register_operand")]
> +			    VCMLA_OP)
> +		 (match_operand:VF 3 "register_operand")))]
>    "(TARGET_COMPLEX || (TARGET_HAVE_MVE &&
> TARGET_HAVE_MVE_FLOAT
>  		      && ARM_HAVE_<MODE>_ARITH))
> && !BYTES_BIG_ENDIAN"
>  {
>    rtx tmp = gen_reg_rtx (<MODE>mode);
> -  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[1],
> -					     operands[3], operands[2]));
> +  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[3],
> +					     operands[2], operands[1]));
>    emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], tmp,
> -					     operands[3], operands[2]));
> +					     operands[2], operands[1]));
>    DONE;
>  })
Tamar Christina Feb. 1, 2022, 9:54 a.m. UTC | #3 
Ping x3

> -----Original Message-----
> From: Tamar Christina
> Sent: Tuesday, January 11, 2022 7:11 AM
> To: gcc-patches@gcc.gnu.org
> Cc: nd <nd@arm.com>; Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; 'nickc@redhat.com' <nickc@redhat.com>;
> Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Subject: RE: [3/3 PATCH][AArch32] use canonical ordering for complex mul,
> fma and fms
> 
> ping
> 
> > -----Original Message-----
> > From: Tamar Christina
> > Sent: Monday, December 20, 2021 4:22 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: nd <nd@arm.com>; Ramana Radhakrishnan
> > <Ramana.Radhakrishnan@arm.com>; Richard Earnshaw
> > <Richard.Earnshaw@arm.com>; nickc@redhat.com; Kyrylo Tkachov
> > <Kyrylo.Tkachov@arm.com>
> > Subject: RE: [3/3 PATCH][AArch32] use canonical ordering for complex
> > mul, fma and fms
> >
> > Updated version of patch following AArch64 review.
> >
> > Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.
> >
> > Ok for master? and backport along with the first patch?
> >
> > Thanks,
> > Tamar
> >
> > gcc/ChangeLog:
> >
> > 	PR tree-optimization/102819
> > 	PR tree-optimization/103169
> > 	* config/arm/vec-common.md (cml<fcmac1><conj_op><mode>4):
> > Use
> > 	canonical order.
> >
> > --- inline copy of patch ---
> >
> > diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> > common.md index
> >
> e71d9b3811fde62159f5c21944fef9fe3f97b4bd..eab77ac8decce76d70f5b2594f
> > 4439e6ed363e6e 100644
> > --- a/gcc/config/arm/vec-common.md
> > +++ b/gcc/config/arm/vec-common.md
> > @@ -265,18 +265,18 @@ (define_expand "arm_vcmla<rot><mode>"
> >  ;; remainder.  Because of this, expand early.
> >  (define_expand "cml<fcmac1><conj_op><mode>4"
> >    [(set (match_operand:VF 0 "register_operand")
> > -	(plus:VF (match_operand:VF 1 "register_operand")
> > -		 (unspec:VF [(match_operand:VF 2 "register_operand")
> > -			     (match_operand:VF 3 "register_operand")]
> > -			    VCMLA_OP)))]
> > +	(plus:VF (unspec:VF [(match_operand:VF 1 "register_operand")
> > +			     (match_operand:VF 2 "register_operand")]
> > +			    VCMLA_OP)
> > +		 (match_operand:VF 3 "register_operand")))]
> >    "(TARGET_COMPLEX || (TARGET_HAVE_MVE &&
> TARGET_HAVE_MVE_FLOAT
> >  		      && ARM_HAVE_<MODE>_ARITH))
> > && !BYTES_BIG_ENDIAN"
> >  {
> >    rtx tmp = gen_reg_rtx (<MODE>mode);
> > -  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[1],
> > -					     operands[3], operands[2]));
> > +  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[3],
> > +					     operands[2], operands[1]));
> >    emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], tmp,
> > -					     operands[3], operands[2]));
> > +					     operands[2], operands[1]));
> >    DONE;
> >  })
Kyrylo Tkachov Feb. 1, 2022, 9:56 a.m. UTC | #4 
> -----Original Message-----
> From: Tamar Christina <Tamar.Christina@arm.com>
> Sent: Monday, December 20, 2021 4:22 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd <nd@arm.com>; Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; nickc@redhat.com; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>
> Subject: RE: [3/3 PATCH][AArch32] use canonical ordering for complex mul,
> fma and fms
> 
> Updated version of patch following AArch64 review.
> 
> Bootstrapped Regtested on arm-none-linux-gnueabihf and no issues.
> 
> Ok for master? and backport along with the first patch?

Ok, sorry I missed it.
Thanks,
Kyrill

> 
> Thanks,
> Tamar
> 
> gcc/ChangeLog:
> 
> 	PR tree-optimization/102819
> 	PR tree-optimization/103169
> 	* config/arm/vec-common.md (cml<fcmac1><conj_op><mode>4):
> Use
> 	canonical order.
> 
> --- inline copy of patch ---
> 
> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> common.md
> index
> e71d9b3811fde62159f5c21944fef9fe3f97b4bd..eab77ac8decce76d70f5b2594
> f4439e6ed363e6e 100644
> --- a/gcc/config/arm/vec-common.md
> +++ b/gcc/config/arm/vec-common.md
> @@ -265,18 +265,18 @@ (define_expand "arm_vcmla<rot><mode>"
>  ;; remainder.  Because of this, expand early.
>  (define_expand "cml<fcmac1><conj_op><mode>4"
>    [(set (match_operand:VF 0 "register_operand")
> -	(plus:VF (match_operand:VF 1 "register_operand")
> -		 (unspec:VF [(match_operand:VF 2 "register_operand")
> -			     (match_operand:VF 3 "register_operand")]
> -			    VCMLA_OP)))]
> +	(plus:VF (unspec:VF [(match_operand:VF 1 "register_operand")
> +			     (match_operand:VF 2 "register_operand")]
> +			    VCMLA_OP)
> +		 (match_operand:VF 3 "register_operand")))]
>    "(TARGET_COMPLEX || (TARGET_HAVE_MVE &&
> TARGET_HAVE_MVE_FLOAT
>  		      && ARM_HAVE_<MODE>_ARITH)) &&
> !BYTES_BIG_ENDIAN"
>  {
>    rtx tmp = gen_reg_rtx (<MODE>mode);
> -  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[1],
> -					     operands[3], operands[2]));
> +  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[3],
> +					     operands[2], operands[1]));
>    emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], tmp,
> -					     operands[3], operands[2]));
> +					     operands[2], operands[1]));
>    DONE;
>  })
>
diff mbox series

Patch

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 8b0a396947cc8e7345f178b926128d7224fb218a..2b6ae67a7ec6bef505c2eaef0ec495d14c656495 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2859,9 +2859,9 @@  (define_expand "cmul<conj_op><mode>3"
   rtx res1 = gen_reg_rtx (<MODE>mode);
   rtx tmp = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));
   emit_insn (gen_neon_vcmla<rotsplit1><mode> (res1, tmp,
-					      operands[2], operands[1]));
+					      operands[1], operands[2]));
   emit_insn (gen_neon_vcmla<rotsplit2><mode> (operands[0], res1,
-					      operands[2], operands[1]));
+					      operands[1], operands[2]));
   DONE;
 })
 
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index e71d9b3811fde62159f5c21944fef9fe3f97b4bd..0940e987de53e191f4abdd248c654aed69f016f7 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -239,14 +239,14 @@  (define_expand "cmul<conj_op><mode>3"
     {
       rtx tmp = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));
       emit_insn (gen_arm_vcmla<rotsplit1><mode> (res1, tmp,
-						 operands[2], operands[1]));
+						 operands[1], operands[2]));
     }
   else
     emit_insn (gen_arm_vcmla<rotsplit1><mode> (res1, CONST0_RTX (<MODE>mode),
-					       operands[2], operands[1]));
+					       operands[1], operands[2]));
 
   emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], res1,
-					     operands[2], operands[1]));
+					     operands[1], operands[2]));
   DONE;
 })
 
@@ -265,18 +265,18 @@  (define_expand "arm_vcmla<rot><mode>"
 ;; remainder.  Because of this, expand early.
 (define_expand "cml<fcmac1><conj_op><mode>4"
   [(set (match_operand:VF 0 "register_operand")
-	(plus:VF (match_operand:VF 1 "register_operand")
-		 (unspec:VF [(match_operand:VF 2 "register_operand")
-			     (match_operand:VF 3 "register_operand")]
-			    VCMLA_OP)))]
+	(plus:VF (unspec:VF [(match_operand:VF 1 "register_operand")
+			     (match_operand:VF 2 "register_operand")]
+			    VCMLA_OP)
+		 (match_operand:VF 3 "register_operand")))]
   "(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT
 		      && ARM_HAVE_<MODE>_ARITH)) && !BYTES_BIG_ENDIAN"
 {
   rtx tmp = gen_reg_rtx (<MODE>mode);
-  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[1],
-					     operands[3], operands[2]));
+  emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[3],
+					     operands[1], operands[2]));
   emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], tmp,
-					     operands[3], operands[2]));
+					     operands[1], operands[2]));
   DONE;
 })