Message ID | 20220113145645.4077141-6-christophe.lyon@foss.st.com |
---|---|
State | Superseded |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6234B3951C7F for <patchwork@sourceware.org>; Thu, 13 Jan 2022 15:03:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6234B3951C7F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1642086224; bh=A9mYsK2GkM87ljhaTSvROenRdJVkZwHx4Da6f5qh7sM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=RZ1IJrwCiMb0EkUOpc5iC9rFC1YG8LsGCEsZuFFPdxwGzG1w+bSqPqM7wZtEsAgpu umFOmrp8T3uUnLT2g2kbbpdSmnB8pf1ZFInp0uvLx2o+CewlT6Q7iZ71qxDVPcaLeP 7PZNB4n6kqE7ugDS3xU/DS+J2btqh1GOCbBM8+eU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id 1A67A3951C36 for <gcc-patches@gcc.gnu.org>; Thu, 13 Jan 2022 14:58:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1A67A3951C36 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20D9c8NJ031830 for <gcc-patches@gcc.gnu.org>; Thu, 13 Jan 2022 15:58:55 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dj25b5ag9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for <gcc-patches@gcc.gnu.org>; Thu, 13 Jan 2022 15:58:55 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CC54C10002A for <gcc-patches@gcc.gnu.org>; Thu, 13 Jan 2022 15:58:54 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C5D1B21423E for <gcc-patches@gcc.gnu.org>; Thu, 13 Jan 2022 15:58:54 +0100 (CET) Received: from gnx2104.gnb.st.com (10.75.127.47) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Thu, 13 Jan 2022 15:58:54 +0100 To: <gcc-patches@gcc.gnu.org> Subject: [PATCH v3 05/15] arm: Add support for VPR_REG in arm_class_likely_spilled_p Date: Thu, 13 Jan 2022 15:56:15 +0100 Message-ID: <20220113145645.4077141-6-christophe.lyon@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220113145645.4077141-1-christophe.lyon@foss.st.com> References: <20220113145645.4077141-1-christophe.lyon@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-13_07,2022-01-13_01,2021-12-02_01 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Christophe Lyon <christophe.lyon@foss.st.com> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
ARM/MVE use vectors of boolean for predicates
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Commit Message
Christophe Lyon
Jan. 13, 2022, 2:56 p.m. UTC
VPR_REG is the only register in its class, so it should be handled by TARGET_CLASS_LIKELY_SPILLED_P, which is achieved by calling default_class_likely_spilled_p. No test fails without this patch, but it seems it should be implemented. 2022-01-13 Christophe Lyon <christophe.lyon@foss.st.com> gcc/ * config/arm/arm.c (arm_class_likely_spilled_p): Handle VPR_REG.
Comments
On 13/01/2022 14:56, Christophe Lyon via Gcc-patches wrote: > VPR_REG is the only register in its class, so it should be handled by > TARGET_CLASS_LIKELY_SPILLED_P, which is achieved by calling > default_class_likely_spilled_p. No test fails without this patch, but > it seems it should be implemented. > > 2022-01-13 Christophe Lyon <christophe.lyon@foss.st.com> > > gcc/ > * config/arm/arm.c (arm_class_likely_spilled_p): Handle VPR_REG. > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index c3559ca8703..64a8f2dc7de 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -29317,7 +29317,7 @@ arm_class_likely_spilled_p (reg_class_t rclass) > || rclass == CC_REG) > return true; > > - return false; > + return default_class_likely_spilled_p (rclass); > } > > /* Implements target hook small_register_classes_for_mode_p. */ LGTM, but await reviewer approval. I suspect this would help avoiding spilling of other special registers, though I'm not sure we codegen any enough to make a difference, which is why it is likely to have no effect on anything else.
On Wed, Jan 19, 2022 at 7:25 PM Andre Vieira (lists) via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > > On 13/01/2022 14:56, Christophe Lyon via Gcc-patches wrote: > > VPR_REG is the only register in its class, so it should be handled by > > TARGET_CLASS_LIKELY_SPILLED_P, which is achieved by calling > > default_class_likely_spilled_p. No test fails without this patch, but > > it seems it should be implemented. > > > > 2022-01-13 Christophe Lyon <christophe.lyon@foss.st.com> > > > > gcc/ > > * config/arm/arm.c (arm_class_likely_spilled_p): Handle VPR_REG. > > > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > > index c3559ca8703..64a8f2dc7de 100644 > > --- a/gcc/config/arm/arm.c > > +++ b/gcc/config/arm/arm.c > > @@ -29317,7 +29317,7 @@ arm_class_likely_spilled_p (reg_class_t rclass) > > || rclass == CC_REG) > > return true; > > > > - return false; > > + return default_class_likely_spilled_p (rclass); > > } > > > > /* Implements target hook small_register_classes_for_mode_p. */ > LGTM, but await reviewer approval. I suspect this would help avoiding > spilling of other special registers, though I'm not sure we codegen any > enough to make a difference, which is why it is likely to have no effect > on anything else. > > Yeah. I thought this had been approved at v2: https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581778.html (like most other patches in the series, except the few ones I had to change v2 -> v3) Thanks, Christophe
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c3559ca8703..64a8f2dc7de 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -29317,7 +29317,7 @@ arm_class_likely_spilled_p (reg_class_t rclass) || rclass == CC_REG) return true; - return false; + return default_class_likely_spilled_p (rclass); } /* Implements target hook small_register_classes_for_mode_p. */