Message ID | b4b2341b-567e-fc53-4a54-deeff5e01cb0@linux.ibm.com |
---|---|
State | New |
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Thu, 13 Jan 2022 01:56:10 +0000 (GMT) To: GCC Patches <gcc-patches@gcc.gnu.org> Subject: [PATCH] rs6000: Use known constant for GET_MODE_NUNITS and similar Message-ID: <b4b2341b-567e-fc53-4a54-deeff5e01cb0@linux.ibm.com> Date: Thu, 13 Jan 2022 09:56:09 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Type: text/plain; charset=gbk Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: yEg4B2G4GAt-ypcBJBvgkOJ6FRbOBN06 X-Proofpoint-GUID: cON6ReWqBnRjlLvR7jVOtSwmDyiEbkSG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-12_08,2022-01-11_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201130002 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: "Kewen.Lin via Gcc-patches" <gcc-patches@gcc.gnu.org> Reply-To: "Kewen.Lin" <linkw@linux.ibm.com> Cc: Bill Schmidt <wschmidt@linux.ibm.com>, David Edelsohn <dje.gcc@gmail.com>, Segher Boessenkool <segher@kernel.crashing.org> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
rs6000: Use known constant for GET_MODE_NUNITS and similar
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Commit Message
Kewen.Lin
Jan. 13, 2022, 1:56 a.m. UTC
Hi, This patch is to clean up some codes with GET_MODE_UNIT_SIZE or GET_MODE_NUNITS, which can use known constant instead. Bootstrapped and regtested on powerpc64le-linux-gnu P9 and powerpc64-linux-gnu P8. Is it ok for trunk? BR, Kewen ----- gcc/ChangeLog: * config/rs6000/altivec.md (altivec_vreveti2): Use known constant values to simplify code. * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): Likewise. --- gcc/config/rs6000/altivec.md | 11 +++-------- gcc/config/rs6000/vsx.md | 8 ++++---- 2 files changed, 7 insertions(+), 12 deletions(-) -- 2.27.0
Comments
On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin <linkw@linux.ibm.com> wrote: > > Hi, > > This patch is to clean up some codes with GET_MODE_UNIT_SIZE or > GET_MODE_NUNITS, which can use known constant instead. I'll let Segher decide, but often the additional code is useful self-documentation instead of magic constants. Or at least the change requires comments documenting the derivation of the constants currently described by the code itself. Thanks, David > > Bootstrapped and regtested on powerpc64le-linux-gnu P9 and > powerpc64-linux-gnu P8. > > Is it ok for trunk? > > BR, > Kewen > ----- > gcc/ChangeLog: > > * config/rs6000/altivec.md (altivec_vreveti2): Use known constant > values to simplify code. > * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, > *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): > Likewise. > --- > gcc/config/rs6000/altivec.md | 11 +++-------- > gcc/config/rs6000/vsx.md | 8 ++++---- > 2 files changed, 7 insertions(+), 12 deletions(-) > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index c2312cc1e0f..d5c4ecfa9b7 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -3957,17 +3957,12 @@ (define_expand "altivec_vreveti2" > UNSPEC_VREVEV))] > "TARGET_ALTIVEC" > { > - int i, j, size, num_elements; > + int i; > rtvec v = rtvec_alloc (16); > rtx mask = gen_reg_rtx (V16QImode); > > - size = GET_MODE_UNIT_SIZE (TImode); > - num_elements = GET_MODE_NUNITS (TImode); > - > - for (j = 0; j < num_elements; j++) > - for (i = 0; i < size; i++) > - RTVEC_ELT (v, i + j * size) > - = GEN_INT (i + (num_elements - 1 - j) * size); > + for (i = 0; i < 16; i++) > + RTVEC_ELT (v, i) = GEN_INT (i); > > emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); > emit_insn (gen_altivec_vperm_ti (operands[0], operands[1], > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 802db0d112b..892b99c6d6b 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -3855,7 +3855,7 @@ (define_insn_and_split "*vsx_extract_si" > int value; > > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4231,7 +4231,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_df" > int value; > > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4274,7 +4274,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>" > int value; > > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4467,7 +4467,7 @@ (define_insn "*vsx_insert_extract_v4sf_p9" > int ele = INTVAL (operands[4]); > > if (!BYTES_BIG_ENDIAN) > - ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; > + ele = 3 - ele; > > operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); > return "xxinsertw %x0,%x2,%4"; > -- > 2.27.0 >
Hi David, on 2022/1/13 上午11:12, David Edelsohn wrote: > On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin <linkw@linux.ibm.com> wrote: >> >> Hi, >> >> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or >> GET_MODE_NUNITS, which can use known constant instead. > > I'll let Segher decide, but often the additional code is useful > self-documentation instead of magic constants. Or at least the change > requires comments documenting the derivation of the constants > currently described by the code itself. > Thanks for the comments, I added some comments as suggested, also removed the whole "altivec_vreveti2" since I noticed it's useless, it's not used by any built-in functions and even unused in the commit db042e1603db50573. The updated version has been tested as before. BR, Kewen ----- gcc/ChangeLog: * config/rs6000/altivec.md (altivec_vreveti2): Remove. * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): Use known constant values to simplify code. --- gcc/config/rs6000/altivec.md | 25 ------------------------- gcc/config/rs6000/vsx.md | 12 ++++++++---- 2 files changed, 8 insertions(+), 29 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index c2312cc1e0f..b7f056f8c60 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3950,31 +3950,6 @@ (define_expand "altivec_negv4sf2" DONE; }) -;; Vector reverse elements -(define_expand "altivec_vreveti2" - [(set (match_operand:TI 0 "register_operand" "=v") - (unspec:TI [(match_operand:TI 1 "register_operand" "v")] - UNSPEC_VREVEV))] - "TARGET_ALTIVEC" -{ - int i, j, size, num_elements; - rtvec v = rtvec_alloc (16); - rtx mask = gen_reg_rtx (V16QImode); - - size = GET_MODE_UNIT_SIZE (TImode); - num_elements = GET_MODE_NUNITS (TImode); - - for (j = 0; j < num_elements; j++) - for (i = 0; i < size; i++) - RTVEC_ELT (v, i + j * size) - = GEN_INT (i + (num_elements - 1 - j) * size); - - emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_ti (operands[0], operands[1], - operands[1], mask)); - DONE; -}) - ;; Vector reverse elements for V16QI V8HI V4SI V4SF (define_expand "altivec_vreve<mode>2" [(set (match_operand:VEC_K 0 "register_operand" "=v") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 802db0d112b..d246410880d 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3854,8 +3854,9 @@ (define_insn_and_split "*vsx_extract_si" rtx vec_tmp = operands[3]; int value; + /* Adjust index for LE element ordering. */ if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4230,8 +4231,9 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_df" rtx v4si_tmp = operands[3]; int value; + /* Adjust index for LE element ordering. */ if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4273,8 +4275,9 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>" rtx df_tmp = operands[4]; int value; + /* Adjust index for LE element ordering. */ if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4466,8 +4469,9 @@ (define_insn "*vsx_insert_extract_v4sf_p9" { int ele = INTVAL (operands[4]); + /* Adjust index for LE element ordering. */ if (!BYTES_BIG_ENDIAN) - ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; + ele = 3 - ele; operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); return "xxinsertw %x0,%x2,%4"; -- 2.27.0
On Thu, Jan 13, 2022 at 7:40 AM Kewen.Lin <linkw@linux.ibm.com> wrote: > > Hi David, > > on 2022/1/13 上午11:12, David Edelsohn wrote: > > On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin <linkw@linux.ibm.com> wrote: > >> > >> Hi, > >> > >> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or > >> GET_MODE_NUNITS, which can use known constant instead. > > > > I'll let Segher decide, but often the additional code is useful > > self-documentation instead of magic constants. Or at least the change > > requires comments documenting the derivation of the constants > > currently described by the code itself. > > > > Thanks for the comments, I added some comments as suggested, also removed > the whole "altivec_vreveti2" since I noticed it's useless, it's not used > by any built-in functions and even unused in the commit db042e1603db50573. > > The updated version has been tested as before. As we have discussed offline, the comments need to be clarified and expanded. And the removal of altivec_vreveti2 should be confirmed with Carl Love, who added the pattern less than a year ago. There may be another patch planning to use it. Thanks, David > > BR, > Kewen > ----- > gcc/ChangeLog: > > * config/rs6000/altivec.md (altivec_vreveti2): Remove. > * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, > *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): Use > known constant values to simplify code. > --- > gcc/config/rs6000/altivec.md | 25 ------------------------- > gcc/config/rs6000/vsx.md | 12 ++++++++---- > 2 files changed, 8 insertions(+), 29 deletions(-) > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index c2312cc1e0f..b7f056f8c60 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -3950,31 +3950,6 @@ (define_expand "altivec_negv4sf2" > DONE; > }) > > -;; Vector reverse elements > -(define_expand "altivec_vreveti2" > - [(set (match_operand:TI 0 "register_operand" "=v") > - (unspec:TI [(match_operand:TI 1 "register_operand" "v")] > - UNSPEC_VREVEV))] > - "TARGET_ALTIVEC" > -{ > - int i, j, size, num_elements; > - rtvec v = rtvec_alloc (16); > - rtx mask = gen_reg_rtx (V16QImode); > - > - size = GET_MODE_UNIT_SIZE (TImode); > - num_elements = GET_MODE_NUNITS (TImode); > - > - for (j = 0; j < num_elements; j++) > - for (i = 0; i < size; i++) > - RTVEC_ELT (v, i + j * size) > - = GEN_INT (i + (num_elements - 1 - j) * size); > - > - emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); > - emit_insn (gen_altivec_vperm_ti (operands[0], operands[1], > - operands[1], mask)); > - DONE; > -}) > - > ;; Vector reverse elements for V16QI V8HI V4SI V4SF > (define_expand "altivec_vreve<mode>2" > [(set (match_operand:VEC_K 0 "register_operand" "=v") > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index 802db0d112b..d246410880d 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -3854,8 +3854,9 @@ (define_insn_and_split "*vsx_extract_si" > rtx vec_tmp = operands[3]; > int value; > > + /* Adjust index for LE element ordering. */ > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4230,8 +4231,9 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_df" > rtx v4si_tmp = operands[3]; > int value; > > + /* Adjust index for LE element ordering. */ > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4273,8 +4275,9 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>" > rtx df_tmp = operands[4]; > int value; > > + /* Adjust index for LE element ordering. */ > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4466,8 +4469,9 @@ (define_insn "*vsx_insert_extract_v4sf_p9" > { > int ele = INTVAL (operands[4]); > > + /* Adjust index for LE element ordering. */ > if (!BYTES_BIG_ENDIAN) > - ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; > + ele = 3 - ele; > > operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); > return "xxinsertw %x0,%x2,%4"; > -- > 2.27.0 >
on 2022/1/13 下午11:15, David Edelsohn wrote: > On Thu, Jan 13, 2022 at 7:40 AM Kewen.Lin <linkw@linux.ibm.com> wrote: >> >> Hi David, >> >> on 2022/1/13 上午11:12, David Edelsohn wrote: >>> On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin <linkw@linux.ibm.com> wrote: >>>> >>>> Hi, >>>> >>>> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or >>>> GET_MODE_NUNITS, which can use known constant instead. >>> >>> I'll let Segher decide, but often the additional code is useful >>> self-documentation instead of magic constants. Or at least the change >>> requires comments documenting the derivation of the constants >>> currently described by the code itself. >>> >> >> Thanks for the comments, I added some comments as suggested, also removed >> the whole "altivec_vreveti2" since I noticed it's useless, it's not used >> by any built-in functions and even unused in the commit db042e1603db50573. >> >> The updated version has been tested as before. > > As we have discussed offline, the comments need to be clarified and expanded. > > And the removal of altivec_vreveti2 should be confirmed with Carl > Love, who added the pattern less than a year ago. There may be another > patch planning to use it. > Thanks for the suggestions David! The comments have been updated, and Carl also helped to confirm the altivec_vreveti2 pattern is not planned for any future work and looks reasonable to remove. Does this updated version look good to you? BR, Kewen ----- gcc/ChangeLog: * config/rs6000/altivec.md (altivec_vreveti2): Remove. * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): Use known constant values to simplify code. --- gcc/config/rs6000/altivec.md | 25 ------------------------- gcc/config/rs6000/vsx.md | 16 ++++++++++++---- 2 files changed, 12 insertions(+), 29 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 950b17862c4..4412175a0dc 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3950,31 +3950,6 @@ DONE; }) -;; Vector reverse elements -(define_expand "altivec_vreveti2" - [(set (match_operand:TI 0 "register_operand" "=v") - (unspec:TI [(match_operand:TI 1 "register_operand" "v")] - UNSPEC_VREVEV))] - "TARGET_ALTIVEC" -{ - int i, j, size, num_elements; - rtvec v = rtvec_alloc (16); - rtx mask = gen_reg_rtx (V16QImode); - - size = GET_MODE_UNIT_SIZE (TImode); - num_elements = GET_MODE_NUNITS (TImode); - - for (j = 0; j < num_elements; j++) - for (i = 0; i < size; i++) - RTVEC_ELT (v, i + j * size) - = GEN_INT (i + (num_elements - 1 - j) * size); - - emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); - emit_insn (gen_altivec_vperm_ti (operands[0], operands[1], - operands[1], mask)); - DONE; -}) - ;; Vector reverse elements for V16QI V8HI V4SI V4SF (define_expand "altivec_vreve<mode>2" [(set (match_operand:VEC_K 0 "register_operand" "=v") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index acd729d1687..ee748ff4ebd 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3854,8 +3854,10 @@ rtx vec_tmp = operands[3]; int value; + /* Adjust index for LE element ordering, the below minuend 3 is computed by + GET_MODE_NUNITS (V4SImode) - 1. */ if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4230,8 +4232,10 @@ rtx v4si_tmp = operands[3]; int value; + /* Adjust index for LE element ordering, the below minuend 3 is computed by + GET_MODE_NUNITS (V4SImode) - 1. */ if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4273,8 +4277,10 @@ rtx df_tmp = operands[4]; int value; + /* Adjust index for LE element ordering, the below minuend 3 is computed by + GET_MODE_NUNITS (V4SImode) - 1. */ if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4466,8 +4472,10 @@ { int ele = INTVAL (operands[4]); + /* Adjust index for LE element ordering, the below minuend 3 is computed by + GET_MODE_NUNITS (V4SFmode) - 1. */ if (!BYTES_BIG_ENDIAN) - ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; + ele = 3 - ele; operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); return "xxinsertw %x0,%x2,%4";
On Fri, Jan 14, 2022 at 5:42 AM Kewen.Lin <linkw@linux.ibm.com> wrote: > > on 2022/1/13 下午11:15, David Edelsohn wrote: > > On Thu, Jan 13, 2022 at 7:40 AM Kewen.Lin <linkw@linux.ibm.com> wrote: > >> > >> Hi David, > >> > >> on 2022/1/13 上午11:12, David Edelsohn wrote: > >>> On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin <linkw@linux.ibm.com> wrote: > >>>> > >>>> Hi, > >>>> > >>>> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or > >>>> GET_MODE_NUNITS, which can use known constant instead. > >>> > >>> I'll let Segher decide, but often the additional code is useful > >>> self-documentation instead of magic constants. Or at least the change > >>> requires comments documenting the derivation of the constants > >>> currently described by the code itself. > >>> > >> > >> Thanks for the comments, I added some comments as suggested, also removed > >> the whole "altivec_vreveti2" since I noticed it's useless, it's not used > >> by any built-in functions and even unused in the commit db042e1603db50573. > >> > >> The updated version has been tested as before. > > > > As we have discussed offline, the comments need to be clarified and expanded. > > > > And the removal of altivec_vreveti2 should be confirmed with Carl > > Love, who added the pattern less than a year ago. There may be another > > patch planning to use it. > > > > Thanks for the suggestions David! The comments have been updated, and Carl > also helped to confirm the altivec_vreveti2 pattern is not planned for any > future work and looks reasonable to remove. > > Does this updated version look good to you? The revised patch is okay. Thanks, David > > BR, > Kewen > ----- > gcc/ChangeLog: > > * config/rs6000/altivec.md (altivec_vreveti2): Remove. > * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, > *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): Use > known constant values to simplify code. > --- > gcc/config/rs6000/altivec.md | 25 ------------------------- > gcc/config/rs6000/vsx.md | 16 ++++++++++++---- > 2 files changed, 12 insertions(+), 29 deletions(-) > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index 950b17862c4..4412175a0dc 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -3950,31 +3950,6 @@ > DONE; > }) > > -;; Vector reverse elements > -(define_expand "altivec_vreveti2" > - [(set (match_operand:TI 0 "register_operand" "=v") > - (unspec:TI [(match_operand:TI 1 "register_operand" "v")] > - UNSPEC_VREVEV))] > - "TARGET_ALTIVEC" > -{ > - int i, j, size, num_elements; > - rtvec v = rtvec_alloc (16); > - rtx mask = gen_reg_rtx (V16QImode); > - > - size = GET_MODE_UNIT_SIZE (TImode); > - num_elements = GET_MODE_NUNITS (TImode); > - > - for (j = 0; j < num_elements; j++) > - for (i = 0; i < size; i++) > - RTVEC_ELT (v, i + j * size) > - = GEN_INT (i + (num_elements - 1 - j) * size); > - > - emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); > - emit_insn (gen_altivec_vperm_ti (operands[0], operands[1], > - operands[1], mask)); > - DONE; > -}) > - > ;; Vector reverse elements for V16QI V8HI V4SI V4SF > (define_expand "altivec_vreve<mode>2" > [(set (match_operand:VEC_K 0 "register_operand" "=v") > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index acd729d1687..ee748ff4ebd 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -3854,8 +3854,10 @@ > rtx vec_tmp = operands[3]; > int value; > > + /* Adjust index for LE element ordering, the below minuend 3 is computed by > + GET_MODE_NUNITS (V4SImode) - 1. */ > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4230,8 +4232,10 @@ > rtx v4si_tmp = operands[3]; > int value; > > + /* Adjust index for LE element ordering, the below minuend 3 is computed by > + GET_MODE_NUNITS (V4SImode) - 1. */ > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4273,8 +4277,10 @@ > rtx df_tmp = operands[4]; > int value; > > + /* Adjust index for LE element ordering, the below minuend 3 is computed by > + GET_MODE_NUNITS (V4SImode) - 1. */ > if (!BYTES_BIG_ENDIAN) > - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); > + element = GEN_INT (3 - INTVAL (element)); > > /* If the value is in the correct position, we can avoid doing the VSPLT<x> > instruction. */ > @@ -4466,8 +4472,10 @@ > { > int ele = INTVAL (operands[4]); > > + /* Adjust index for LE element ordering, the below minuend 3 is computed by > + GET_MODE_NUNITS (V4SFmode) - 1. */ > if (!BYTES_BIG_ENDIAN) > - ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; > + ele = 3 - ele; > > operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); > return "xxinsertw %x0,%x2,%4"; >
on 2022/1/14 下午9:53, David Edelsohn wrote: > On Fri, Jan 14, 2022 at 5:42 AM Kewen.Lin <linkw@linux.ibm.com> wrote: >> >> on 2022/1/13 下午11:15, David Edelsohn wrote: >>> On Thu, Jan 13, 2022 at 7:40 AM Kewen.Lin <linkw@linux.ibm.com> wrote: >>>> >>>> Hi David, >>>> >>>> on 2022/1/13 上午11:12, David Edelsohn wrote: >>>>> On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin <linkw@linux.ibm.com> wrote: >>>>>> >>>>>> Hi, >>>>>> >>>>>> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or >>>>>> GET_MODE_NUNITS, which can use known constant instead. >>>>> >>>>> I'll let Segher decide, but often the additional code is useful >>>>> self-documentation instead of magic constants. Or at least the change >>>>> requires comments documenting the derivation of the constants >>>>> currently described by the code itself. >>>>> >>>> >>>> Thanks for the comments, I added some comments as suggested, also removed >>>> the whole "altivec_vreveti2" since I noticed it's useless, it's not used >>>> by any built-in functions and even unused in the commit db042e1603db50573. >>>> >>>> The updated version has been tested as before. >>> >>> As we have discussed offline, the comments need to be clarified and expanded. >>> >>> And the removal of altivec_vreveti2 should be confirmed with Carl >>> Love, who added the pattern less than a year ago. There may be another >>> patch planning to use it. >>> >> >> Thanks for the suggestions David! The comments have been updated, and Carl >> also helped to confirm the altivec_vreveti2 pattern is not planned for any >> future work and looks reasonable to remove. >> >> Does this updated version look good to you? > > The revised patch is okay. Thanks! Committed as r12-6621. BR, Kewen
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index c2312cc1e0f..d5c4ecfa9b7 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3957,17 +3957,12 @@ (define_expand "altivec_vreveti2" UNSPEC_VREVEV))] "TARGET_ALTIVEC" { - int i, j, size, num_elements; + int i; rtvec v = rtvec_alloc (16); rtx mask = gen_reg_rtx (V16QImode); - size = GET_MODE_UNIT_SIZE (TImode); - num_elements = GET_MODE_NUNITS (TImode); - - for (j = 0; j < num_elements; j++) - for (i = 0; i < size; i++) - RTVEC_ELT (v, i + j * size) - = GEN_INT (i + (num_elements - 1 - j) * size); + for (i = 0; i < 16; i++) + RTVEC_ELT (v, i) = GEN_INT (i); emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_altivec_vperm_ti (operands[0], operands[1], diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 802db0d112b..892b99c6d6b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3855,7 +3855,7 @@ (define_insn_and_split "*vsx_extract_si" int value; if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4231,7 +4231,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_df" int value; if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4274,7 +4274,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>" int value; if (!BYTES_BIG_ENDIAN) - element = GEN_INT (GET_MODE_NUNITS (V4SImode) - 1 - INTVAL (element)); + element = GEN_INT (3 - INTVAL (element)); /* If the value is in the correct position, we can avoid doing the VSPLT<x> instruction. */ @@ -4467,7 +4467,7 @@ (define_insn "*vsx_insert_extract_v4sf_p9" int ele = INTVAL (operands[4]); if (!BYTES_BIG_ENDIAN) - ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; + ele = 3 - ele; operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); return "xxinsertw %x0,%x2,%4";