diff mbox series

[GCC12] Mention Intel AVX512-FP16 and _Float16 support.

Message ID 20210924011730.97039-1-hongtao.liu@intel.com
State New
Headers
Series [GCC12] Mention Intel AVX512-FP16 and _Float16 support. |

Commit Message

Liu, Hongtao Sept. 24, 2021, 1:17 a.m. UTC 
  Updated, mention _Float16 support.

---
 htdocs/gcc-12/changes.html | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

H.J. Lu Sept. 24, 2021, 1:20 a.m. UTC | #1 
On Thu, Sep 23, 2021 at 6:17 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Updated, mention _Float16 support.
>
> ---
>  htdocs/gcc-12/changes.html | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
> index 81f62fe3..f19c6718 100644
> --- a/htdocs/gcc-12/changes.html
> +++ b/htdocs/gcc-12/changes.html
> @@ -165,7 +165,18 @@ a work-in-progress.</p>
>    </li>
>  </ul>
>
> -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> +<h3 id="x86">IA-32/x86-64</h3>
> +<ul>
> +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> +      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
> +      compiler switch.
> +  </li>
> +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> +      <code>_Float16</code> type is storage only, all operations will be

I don't think _Float16 is storage only without AVX512FP16.

> +      emulated by software emulation and the <code>float</code> instructions.
> +  </li>
> +</ul>
>
>  <!-- <h3 id="mips">MIPS</h3> -->
>
> --
> 2.18.1
>
H.J. Lu Sept. 24, 2021, 1:41 a.m. UTC | #2 
On Thu, Sep 23, 2021 at 6:38 PM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Fri, Sep 24, 2021 at 9:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Thu, Sep 23, 2021 at 6:17 PM liuhongt <hongtao.liu@intel.com> wrote:
> > >
> > > Updated, mention _Float16 support.
> > >
> > > ---
> > >  htdocs/gcc-12/changes.html | 13 ++++++++++++-
> > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
> > > index 81f62fe3..f19c6718 100644
> > > --- a/htdocs/gcc-12/changes.html
> > > +++ b/htdocs/gcc-12/changes.html
> > > @@ -165,7 +165,18 @@ a work-in-progress.</p>
> > >    </li>
> > >  </ul>
> > >
> > > -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> > > +<h3 id="x86">IA-32/x86-64</h3>
> > > +<ul>
> > > +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> > > +      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
> > > +      compiler switch.
> > > +  </li>
> > > +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> > > +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> > > +      <code>_Float16</code> type is storage only, all operations will be
> >
> > I don't think _Float16 is storage only without AVX512FP16.
> >
> I guess you're meaning that psABI is available for _Float16 even w/o
> AVX512-FP16.
>
> How about
>
> +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> +      no real AVX512-FP16 instructions are generated, all operations will be

No need for "no real AVX512-FP16 instructions are generated".

> +      emulated by software emulation and the <code>float</code> instructions.
> +  </li>
>
> > > +      emulated by software emulation and the <code>float</code> instructions.
> > > +  </li>
> > > +</ul>
> > >
> > >  <!-- <h3 id="mips">MIPS</h3> -->
> > >
> > > --
> > > 2.18.1
> > >
> >
> >
> > --
> > H.J.
>
>
>
> --
> BR,
> Hongtao
Hongtao Liu Sept. 24, 2021, 1:44 a.m. UTC | #3 
On Fri, Sep 24, 2021 at 9:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Sep 23, 2021 at 6:17 PM liuhongt <hongtao.liu@intel.com> wrote:
> >
> > Updated, mention _Float16 support.
> >
> > ---
> >  htdocs/gcc-12/changes.html | 13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
> > index 81f62fe3..f19c6718 100644
> > --- a/htdocs/gcc-12/changes.html
> > +++ b/htdocs/gcc-12/changes.html
> > @@ -165,7 +165,18 @@ a work-in-progress.</p>
> >    </li>
> >  </ul>
> >
> > -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> > +<h3 id="x86">IA-32/x86-64</h3>
> > +<ul>
> > +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> > +      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
> > +      compiler switch.
> > +  </li>
> > +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> > +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> > +      <code>_Float16</code> type is storage only, all operations will be
>
> I don't think _Float16 is storage only without AVX512FP16.
>
I guess you're meaning that psABI is available for _Float16 even w/o
AVX512-FP16.

How about

+  <li>For both C and C++, The <code>_Float16</code> type is supported on
+      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
+      no real AVX512-FP16 instructions are generated, all operations will be
+      emulated by software emulation and the <code>float</code> instructions.
+  </li>

> > +      emulated by software emulation and the <code>float</code> instructions.
> > +  </li>
> > +</ul>
> >
> >  <!-- <h3 id="mips">MIPS</h3> -->
> >
> > --
> > 2.18.1
> >
>
>
> --
> H.J.
Hongtao Liu Sept. 24, 2021, 2:04 a.m. UTC | #4 
On Fri, Sep 24, 2021 at 9:42 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Sep 23, 2021 at 6:38 PM Hongtao Liu <crazylht@gmail.com> wrote:
> >
> > On Fri, Sep 24, 2021 at 9:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Thu, Sep 23, 2021 at 6:17 PM liuhongt <hongtao.liu@intel.com> wrote:
> > > >
> > > > Updated, mention _Float16 support.
> > > >
> > > > ---
> > > >  htdocs/gcc-12/changes.html | 13 ++++++++++++-
> > > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
> > > > index 81f62fe3..f19c6718 100644
> > > > --- a/htdocs/gcc-12/changes.html
> > > > +++ b/htdocs/gcc-12/changes.html
> > > > @@ -165,7 +165,18 @@ a work-in-progress.</p>
> > > >    </li>
> > > >  </ul>
> > > >
> > > > -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> > > > +<h3 id="x86">IA-32/x86-64</h3>
> > > > +<ul>
> > > > +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> > > > +      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
> > > > +      compiler switch.
> > > > +  </li>
> > > > +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> > > > +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> > > > +      <code>_Float16</code> type is storage only, all operations will be
> > >
> > > I don't think _Float16 is storage only without AVX512FP16.
> > >
> > I guess you're meaning that psABI is available for _Float16 even w/o
> > AVX512-FP16.
> >
> > How about
> >
> > +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> > +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> > +      no real AVX512-FP16 instructions are generated, all operations will be
>
> No need for "no real AVX512-FP16 instructions are generated".
Updated.

-<!-- <h3 id="x86">IA-32/x86-64</h3> -->
+<h3 id="x86">IA-32/x86-64</h3>
+<ul>
+  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
+      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
+      compiler switch.
+  </li>
+  <li>For both C and C++, The <code>_Float16</code> type is supported on
+      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
+      all operations will be emulated by software emulation and the
+      <code>float</code> instructions.
+  </li>
+</ul>

>
> > +      emulated by software emulation and the <code>float</code> instructions.
> > +  </li>
> >
> > > > +      emulated by software emulation and the <code>float</code> instructions.
> > > > +  </li>
> > > > +</ul>
> > > >
> > > >  <!-- <h3 id="mips">MIPS</h3> -->
> > > >
> > > > --
> > > > 2.18.1
> > > >
> > >
> > >
> > > --
> > > H.J.
> >
> >
> >
> > --
> > BR,
> > Hongtao
>
>
>
> --
> H.J.
H.J. Lu Sept. 24, 2021, 2:12 a.m. UTC | #5 
On Thu, Sep 23, 2021 at 6:58 PM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Fri, Sep 24, 2021 at 9:42 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Thu, Sep 23, 2021 at 6:38 PM Hongtao Liu <crazylht@gmail.com> wrote:
> > >
> > > On Fri, Sep 24, 2021 at 9:20 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Thu, Sep 23, 2021 at 6:17 PM liuhongt <hongtao.liu@intel.com> wrote:
> > > > >
> > > > > Updated, mention _Float16 support.
> > > > >
> > > > > ---
> > > > >  htdocs/gcc-12/changes.html | 13 ++++++++++++-
> > > > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
> > > > > index 81f62fe3..f19c6718 100644
> > > > > --- a/htdocs/gcc-12/changes.html
> > > > > +++ b/htdocs/gcc-12/changes.html
> > > > > @@ -165,7 +165,18 @@ a work-in-progress.</p>
> > > > >    </li>
> > > > >  </ul>
> > > > >
> > > > > -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> > > > > +<h3 id="x86">IA-32/x86-64</h3>
> > > > > +<ul>
> > > > > +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> > > > > +      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
> > > > > +      compiler switch.
> > > > > +  </li>
> > > > > +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> > > > > +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> > > > > +      <code>_Float16</code> type is storage only, all operations will be
> > > >
> > > > I don't think _Float16 is storage only without AVX512FP16.
> > > >
> > > I guess you're meaning that psABI is available for _Float16 even w/o
> > > AVX512-FP16.
> > >
> > > How about
> > >
> > > +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> > > +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> > > +      no real AVX512-FP16 instructions are generated, all operations will be
> >
> > No need for "no real AVX512-FP16 instructions are generated".
> Updated.
>
> -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> +<h3 id="x86">IA-32/x86-64</h3>
> +<ul>
> +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> +      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
> +      compiler switch.
> +  </li>
> +  <li>For both C and C++, The <code>_Float16</code> type is supported on
> +      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
> +      all operations will be emulated by software emulation and the
> +      <code>float</code> instructions.
> +  </li>
> +</ul>

LGTM.

Thanks.

> >
> > > +      emulated by software emulation and the <code>float</code> instructions.
> > > +  </li>
> > >
> > > > > +      emulated by software emulation and the <code>float</code> instructions.
> > > > > +  </li>
> > > > > +</ul>
> > > > >
> > > > >  <!-- <h3 id="mips">MIPS</h3> -->
> > > > >
> > > > > --
> > > > > 2.18.1
> > > > >
> > > >
> > > >
> > > > --
> > > > H.J.
> > >
> > >
> > >
> > > --
> > > BR,
> > > Hongtao
> >
> >
> >
> > --
> > H.J.
>
>
>
> --
> BR,
> Hongtao
Gerald Pfeifer Oct. 1, 2021, 10:13 a.m. UTC | #6 
On Fri, 24 Sep 2021, Hongtao Liu via Gcc-patches wrote:
> +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> +      AVX512FP16 intrinsics are available [...]

So, is it AVX512-FP16 or AVX512FP16? 

Gerald
Hongtao Liu Oct. 8, 2021, 1:25 a.m. UTC | #7 
On Fri, Oct 1, 2021 at 6:13 PM Gerald Pfeifer <gerald@pfeifer.com> wrote:
>
> On Fri, 24 Sep 2021, Hongtao Liu via Gcc-patches wrote:
> > +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
> > +      AVX512FP16 intrinsics are available [...]
>
> So, is it AVX512-FP16 or AVX512FP16?
Sorry for the confusion, the official name is AVX512-FP16[1], and for
simplicity, AVX512FP16 is used in the mail thread.
[1] https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
>
> Gerald
Gerald Pfeifer Jan. 28, 2023, 12:40 p.m. UTC | #8 
On Fri, 8 Oct 2021, Hongtao Liu wrote:
> > On Fri, 24 Sep 2021, Hongtao Liu via Gcc-patches wrote:
>>> +  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
>>> +      AVX512FP16 intrinsics are available [...]
>> So, is it AVX512-FP16 or AVX512FP16?
> Sorry for the confusion, the official name is AVX512-FP16[1], and for
> simplicity, AVX512FP16 is used in the mail thread.

Shouldn't we then consistently use AVX512-FP16 here (gcc-12/changes.html)
and in gcc/doc/invoke.texi where there are three instances of AVX512FP16
(without the dash)?

Gerald
diff mbox series

Patch

diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html
index 81f62fe3..f19c6718 100644
--- a/htdocs/gcc-12/changes.html
+++ b/htdocs/gcc-12/changes.html
@@ -165,7 +165,18 @@  a work-in-progress.</p>
   </li>
 </ul>
 
-<!-- <h3 id="x86">IA-32/x86-64</h3> -->
+<h3 id="x86">IA-32/x86-64</h3>
+<ul>
+  <li>New ISA extension support for Intel AVX512-FP16 was added to GCC.
+      AVX512FP16 intrinsics are available via the <code>-mavx512fp16</code>
+      compiler switch.
+  </li>
+  <li>For both C and C++, The <code>_Float16</code> type is supported on
+      x86 systems with SSE2 enabled. Without <code>{-mavx512fp16}</code>,
+      <code>_Float16</code> type is storage only, all operations will be
+      emulated by software emulation and the <code>float</code> instructions.
+  </li>
+</ul>
 
 <!-- <h3 id="mips">MIPS</h3> -->