Message ID | 87wo2g8639.fsf@oldenburg2.str.redhat.com |
---|---|
State | Committed |
Headers |
Return-Path: <libc-alpha-bounces@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 59AB1385DC1A; Mon, 3 Aug 2020 08:52:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 59AB1385DC1A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1596444725; bh=STi9ID2vSl9J5KbrhEg2m8K3CEnrb1kgKYtr+j27Qfs=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=lVLb6TtGNMKPg3VuxiZ1sD4H/WrjW28itxdBFji/M6TkmUNHeIfpAM/Un9ad4BIfJ e2K5HKixseAW/R/eaCw9wVf7K02Q4nBhQan4P9+nKupu9ANH4j7zjpYeVv/zTKri77 iSqLpaR4nCmImfsKTRzjAxS+Jws8myndxK0fmijw= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from us-smtp-delivery-1.mimecast.com (us-smtp-2.mimecast.com [207.211.31.81]) by sourceware.org (Postfix) with ESMTP id 257893857C54 for <libc-alpha@sourceware.org>; Mon, 3 Aug 2020 08:52:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 257893857C54 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-205-AcMXPsF5OHWmGNQu26dBNA-1; Mon, 03 Aug 2020 04:52:00 -0400 X-MC-Unique: AcMXPsF5OHWmGNQu26dBNA-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A7F6F59; Mon, 3 Aug 2020 08:51:59 +0000 (UTC) Received: from oldenburg2.str.redhat.com (ovpn-112-2.ams2.redhat.com [10.36.112.2]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D255B59; Mon, 3 Aug 2020 08:51:55 +0000 (UTC) To: libc-alpha@sourceware.org Subject: [PATCH] powerpc: Fix incorrect cache line size load in memset (bug 26332) Date: Mon, 03 Aug 2020 10:51:54 +0200 Message-ID: <87wo2g8639.fsf@oldenburg2.str.redhat.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list <libc-alpha.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/libc-alpha/> List-Post: <mailto:libc-alpha@sourceware.org> List-Help: <mailto:libc-alpha-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=subscribe> From: Florian Weimer via Libc-alpha <libc-alpha@sourceware.org> Reply-To: Florian Weimer <fweimer@redhat.com> Cc: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces@sourceware.org> |
Series |
powerpc: Fix incorrect cache line size load in memset (bug 26332)
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Commit Message
Florian Weimer
Aug. 3, 2020, 8:51 a.m. UTC
__GLRO loaded the word after the requested variable on big-endian PowerPC, where LOWORD is 4. This can cause the memset implement go wrong because the masking with the cache line size produces wrong results, particularly if the loaded value happens to be 1. The __GLRO macro is not used in any place where loading the lower 32-bit word of a 64-bit value is desired, so the +4 offset is always wrong. Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc ("powerpc: Move cache line size to rtld_global_ro") and bug 26332. --- sysdeps/powerpc/powerpc32/sysdep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Comments
On 8/3/20 4:51 AM, Florian Weimer wrote: > __GLRO loaded the word after the requested variable on big-endian > PowerPC, where LOWORD is 4. This can cause the memset implement > go wrong because the masking with the cache line size produces > wrong results, particularly if the loaded value happens to be 1. > > The __GLRO macro is not used in any place where loading the lower > 32-bit word of a 64-bit value is desired, so the +4 offset is always > wrong. Agreed. I reviewed sysdeps/powerpc/powerpc32/sysdep.h, and: sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h sysdeps/powerpc/powerpc32/sysdep.h sysdeps/powerpc/powerpc32/memset.S sysdeps/powerpc/powerpc32/a2/memcpy.S I see only 32-bit word accesses and so the +4 offset is wrong. This was likely just a copy-and-paste that came from similar code which accesses the 64-bit HWCAP/HWCAP2 e.g. uint64_t _dl_hwcap. The 64-bit sysdeps/powerpc/powerpc64/sysdep.h is different and doesn't have this problem for obvious reasons (it can load a 64-bit value). > Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc > ("powerpc: Move cache line size to rtld_global_ro") and bug 26332. Reviewed-by: Carlos O'Donell <carlos@redhat.com> > --- > sysdeps/powerpc/powerpc32/sysdep.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/sysdeps/powerpc/powerpc32/sysdep.h b/sysdeps/powerpc/powerpc32/sysdep.h > index 2ba009e919..829eec266a 100644 > --- a/sysdeps/powerpc/powerpc32/sysdep.h > +++ b/sysdeps/powerpc/powerpc32/sysdep.h > @@ -179,8 +179,8 @@ GOT_LABEL: ; \ > #else > /* Position-dependent code does not require access to the GOT. */ > # define __GLRO(rOUT, rGOT, member, offset) \ > - lis rOUT,(member+LOWORD)@ha; \ > - lwz rOUT,(member+LOWORD)@l(rOUT) > + lis rOUT,(member)@ha; \ > + lwz rOUT,(member)@l(rOUT) OK. > #endif /* PIC */ > > #endif /* __ASSEMBLER__ */ >
* Carlos O'Donell: > On 8/3/20 4:51 AM, Florian Weimer wrote: >> __GLRO loaded the word after the requested variable on big-endian >> PowerPC, where LOWORD is 4. This can cause the memset implement >> go wrong because the masking with the cache line size produces >> wrong results, particularly if the loaded value happens to be 1. >> >> The __GLRO macro is not used in any place where loading the lower >> 32-bit word of a 64-bit value is desired, so the +4 offset is always >> wrong. > > Agreed. > > I reviewed sysdeps/powerpc/powerpc32/sysdep.h, and: > sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h > sysdeps/powerpc/powerpc32/sysdep.h > sysdeps/powerpc/powerpc32/memset.S > sysdeps/powerpc/powerpc32/a2/memcpy.S > > I see only 32-bit word accesses and so the +4 offset is wrong. This > was likely just a copy-and-paste that came from similar code which > accesses the 64-bit HWCAP/HWCAP2 e.g. uint64_t _dl_hwcap. > > The 64-bit sysdeps/powerpc/powerpc64/sysdep.h is different and doesn't > have this problem for obvious reasons (it can load a 64-bit value). > >> Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc >> ("powerpc: Move cache line size to rtld_global_ro") and bug 26332. > > Reviewed-by: Carlos O'Donell <carlos@redhat.com> Pushed as 7650321ce037302bfc2f026aa19e0213b8d02fe6. Thanks, Florian
diff --git a/sysdeps/powerpc/powerpc32/sysdep.h b/sysdeps/powerpc/powerpc32/sysdep.h index 2ba009e919..829eec266a 100644 --- a/sysdeps/powerpc/powerpc32/sysdep.h +++ b/sysdeps/powerpc/powerpc32/sysdep.h @@ -179,8 +179,8 @@ GOT_LABEL: ; \ #else /* Position-dependent code does not require access to the GOT. */ # define __GLRO(rOUT, rGOT, member, offset) \ - lis rOUT,(member+LOWORD)@ha; \ - lwz rOUT,(member+LOWORD)@l(rOUT) + lis rOUT,(member)@ha; \ + lwz rOUT,(member)@l(rOUT) #endif /* PIC */ #endif /* __ASSEMBLER__ */