From patchwork Wed Sep 29 19:14:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 45581 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A4CBC3857C52 for ; Wed, 29 Sep 2021 19:14:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A4CBC3857C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1632942895; bh=Kpn/2cySJNyGzO8WZfUyCvDOb4CFifhB3S8QpLPTEF4=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=w6IY04GrU9L5qiBO5dQMPZmIaCkCs71mqLMPpcsci3oqeY3A0tKD8MLKlc0n8C9Oq 75fN1L1kvIBNLNsTL7fL1hH+5PccJD64ouIUjW3uL2vWKS69g/xxJd4srUNRhH0RcX T4iaaZE2O5SZXOhS7jbPtsHcoOpK2gF7QVo0LP0k= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-vk1-xa2b.google.com (mail-vk1-xa2b.google.com [IPv6:2607:f8b0:4864:20::a2b]) by sourceware.org (Postfix) with ESMTPS id 5CC573858C60 for ; Wed, 29 Sep 2021 19:14:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5CC573858C60 Received: by mail-vk1-xa2b.google.com with SMTP id t200so1693782vkt.0 for ; Wed, 29 Sep 2021 12:14:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=Kpn/2cySJNyGzO8WZfUyCvDOb4CFifhB3S8QpLPTEF4=; b=wTv7bI3L7PJjOhN9QZF0236KgEhYaG8cdbUnLgDwTm89BSLDRuImlXckFOc5RHxo0t MT+p/zlVWYgyBqSwTKHuVhahnL1c90OeJagaIbqRiS9R1NE1quO2kLga1gBWmzQBfYA/ 6TqUhWxcNETRILhCDTmgdTQku48N5rLEvyx//RX47h2jZyPwb7VTXAIqdQE/76v0SPhl 87Z9Rm4+FC0FWi9/EkqGhn19XHgkFvEzn9hD23k5RZjZrI086GoXqdvX1pkDCsentsyj Y1IwwOgZdd4+nMOhrzToNqqmT3fLiO6uYz7CaG0MF+hadpA61qtjvN1ssIcWCPIdcJmK WZ0A== X-Gm-Message-State: AOAM530obYEIMOxfznNhNGjliwrEyd5Va0ZH4UuZWNG/4ZeQU+Ofltw3 D+IQvNYeoBLnWA2ZbwcgKu5+DNQmOfFIsA== X-Google-Smtp-Source: ABdhPJzOhJyFH15Cmyp4VnsLJqjar1ap5IGQQMrIoW1HGwpYK58HfIzQAY63ZyHQsWuAQCGSrANfxw== X-Received: by 2002:a1f:ee0b:: with SMTP id m11mr280898vkh.19.1632942873561; Wed, 29 Sep 2021 12:14:33 -0700 (PDT) Received: from birita.. ([2804:431:c7cb:b338:4bf7:4eb8:abb4:7729]) by smtp.gmail.com with ESMTPSA id t64sm429706vke.24.2021.09.29.12.14.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 12:14:33 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH] arm: Enable USE_ATOMIC_COMPILER_BUILTINS (BZ #24774) Date: Wed, 29 Sep 2021 16:14:30 -0300 Message-Id: <20210929191430.884057-1-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Adhemerval Zanella via Libc-alpha From: Adhemerval Zanella Netto Reply-To: Adhemerval Zanella Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" As per other architectures. I have checked on a armv8 hardware with the following configurations: arm-linux-gnueabihf (gcc built with --with-float=hard --with-cpu=arm926ej-s) armv5-linux-gnueabihf (-march=armv5te -mfpu=vfpv3) armv7-linux-gnueabihf (-march=armv7-a -mfpu=vfpv3) armv7-thumb-linux-gnueabihf (-march=armv7-a -mfpu=vfpv3 -mthumb) armv7-neon-linux-gnueabihf (-march=armv7-a -mfpu=neon) armv7-neonhard-linux-gnueabihf (-march=armv7-a -mfpu=neon -mfloat-abi=hard) Without any regression. I haven't dig into the code, but since Linux atomic-machine.h handle pre-ARMv6 and ARMv6 I expect the compiler might have some small room to optimize. The code size also improves is most of the configurations: * master text data bss dec hex filename 1727801 9720 37928 1775449 1b1759 arm-linux-gnueabihf/libc.so 1691729 9720 37928 1739377 1a8a71 arm-linux-gnueabihf-armv7-disable-multi-arch/libc.so 1725509 9720 37928 1773157 1b0e65 armv5-linux-gnueabihf/libc.so 1700757 9720 37928 1748405 1aadb5 armv6-linux-gnueabihf/libc.so 1698973 9720 37928 1746621 1aa6bd armv6t2-linux-gnueabihf/libc.so 1695481 9752 37928 1743161 1a9939 armv7-linux-gnueabihf/libc.so 1692917 9744 37928 1740589 1a8f2d armv7-neonhard-linux-gnueabihf/libc.so 1692917 9744 37928 1740589 1a8f2d armv7-neon-linux-gnueabihf/libc.so 1225353 9752 37928 1273033 136cc9 armv7-thumb-linux-gnueabihf/libc.so * patched text data bss dec hex filename 1726805 9720 37928 1774453 1b1375 arm-linux-gnueabihf/libc.so 1689321 9720 37928 1736969 1a8109 arm-linux-gnueabihf-armv7-disable-multi-arch/libc.so 1724433 9720 37928 1772081 1b0a31 armv5-linux-gnueabihf/libc.so 1698301 9720 37928 1745949 1aa41d armv6-linux-gnueabihf/libc.so 1696525 9720 37928 1744173 1a9d2d armv6t2-linux-gnueabihf/libc.so 1693009 9752 37928 1740689 1a8f91 armv7-linux-gnueabihf/libc.so 1690493 9744 37928 1738165 1a85b5 armv7-neonhard-linux-gnueabihf/libc.so 1690493 9744 37928 1738165 1a85b5 armv7-neon-linux-gnueabihf/libc.so 1223837 9752 37928 1271517 1366dd armv7-thumb-linux-gnueabihf/libc.so The idea is eventually move all architectures to use compiler builtins. Reviewed-by: Aurelien Jarno Tested-by: Aurelien Jarno --- sysdeps/arm/atomic-machine.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/arm/atomic-machine.h b/sysdeps/arm/atomic-machine.h index 7928ff29d8..0275fcd2f7 100644 --- a/sysdeps/arm/atomic-machine.h +++ b/sysdeps/arm/atomic-machine.h @@ -34,7 +34,7 @@ typedef intmax_t atomic_max_t; typedef uintmax_t uatomic_max_t; #define __HAVE_64B_ATOMICS 0 -#define USE_ATOMIC_COMPILER_BUILTINS 0 +#define USE_ATOMIC_COMPILER_BUILTINS 1 #define ATOMIC_EXCHANGE_USES_CAS 1 void __arm_link_error (void);