From patchwork Wed Feb 14 10:42:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shahab Vahedi X-Patchwork-Id: 85707 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 09F3B385C6E8 for ; Wed, 14 Feb 2024 10:43:40 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from out-174.mta0.migadu.com (out-174.mta0.migadu.com [IPv6:2001:41d0:1004:224b::ae]) by sourceware.org (Postfix) with ESMTPS id 0554C3857011 for ; Wed, 14 Feb 2024 10:43:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0554C3857011 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=vahedi.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vahedi.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0554C3857011 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:41d0:1004:224b::ae ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707907393; cv=none; b=Ewjd765zl6rfJH0RyiAZcey12/mNJPYu/OGjekm2I8NH6XD6ucbbYsZPgMLcvfcPr4Z7HfFetD5iaJRT3f5unf5gCj4w9Mf9L9wgt8nZJl16rsGNAY1V4BJ1l619j7jyhwKe1ToROiXjne6/Jckjt3HgW3lIx2sfQCs0j/2EzLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707907393; c=relaxed/simple; bh=El8ewA6G8fl5vcZPTyMsY2DnIhlYQuF4aMdqNbxgtpY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=G8K+YUV2am4v90yviard1jGakYTws96OyoNbV5Ofr4qgBKIIASUewGROZ5oJhWj0TqQtqzxsh8kVVS9XFmnXNWcJzOgxAS0GjxVJdT34Ln4xAtiAATWSJDS8Ufer9vVjmK6JadxwUzdOC4wLyinrJF8rdlkgcKDyzmk8y5+OPEs= ARC-Authentication-Results: i=1; server2.sourceware.org X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vahedi.org; s=key1; t=1707907388; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wm/v/npOg++dXFflFM4gIPlaPcXiN3LNKCZpGFitcAY=; b=bc3Ime6oqiCTITcbzhANdiOxapUFRIGyupdARPphy/t4l3TYS4unGn1AItEwH8qgnRrB18 tzS58d3WQZR23KMAnFftJ9BSLmaYA/03LCRgvT4+kdqrqPYC3xFz9AXEVvHtIPVJnMxFQ2 BI4q5nA5pm9yAmocJgOKdtFZzvD1bXyC3KHlm5rm6kR3lu4zSqlvtLndniLNfFoSQL8ghU ZIguhCZncecc7s35NitMETqGFtpHb4X1zEuiXXNnFPcUWWW6ywX13pxYTrcXkv/iyd3bmH CSssss55H0Ng42GT4jLSg9zmrc/yPVEWe/bgIUhUfjYD3AuP1Z7eYF77ccbeDA== From: Shahab Vahedi To: gdb-patches@sourceware.org Cc: Yuriy Kolerov , Claudiu Zissulescu Ianculescu , Shahab Vahedi , Yuriy Kolerov Subject: [PUSHED] arc: Put DBNZ instruction to a separate class Date: Wed, 14 Feb 2024 11:42:55 +0100 Message-Id: <20240214104255.39410-1-list+bin@vahedi.org> In-Reply-To: References: MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-Spam-Status: No, score=-14.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Yuriy Kolerov DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ". --- gas/ChangeLog | 4 ++++ gas/config/tc-arc.c | 1 + include/ChangeLog | 4 ++++ include/opcode/arc.h | 1 + opcodes/ChangeLog | 5 +++++ opcodes/arc-dis.c | 1 + opcodes/arc-tbl.h | 2 +- 7 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index b1c8d09bf1b..b277f47b05d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2024-02-14 Yuriy Kolerov + + * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ". + 2024-01-29 Jose E. Marchesi * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index 69de96e43fc..f7d8e8938ce 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -109,6 +109,7 @@ enum arc_rlx_types || (op)->insn_class == BBIT0 \ || (op)->insn_class == BBIT1 \ || (op)->insn_class == BI \ + || (op)->insn_class == DBNZ \ || (op)->insn_class == EI \ || (op)->insn_class == ENTER \ || (op)->insn_class == JLI \ diff --git a/include/ChangeLog b/include/ChangeLog index 11c4b321a49..db5c258cbdf 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2024-02-14 Yuriy Kolerov + + * opcode/arc.h (enum insn_class_t): Add DBNZ class. + 2024-02-12 Frederic Cambus * elf/common.h (PT_OPENBSD_SYSCALLS): Define. diff --git a/include/opcode/arc.h b/include/opcode/arc.h index df2be17d839..c16e1298b89 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -52,6 +52,7 @@ typedef enum BRANCH, BRCC, CONTROL, + DBNZ, DIVREM, DMA, DPI, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4bc815780fd..4fb2d0de207 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2024-02-14 Yuriy Kolerov + + * arc-tbl.h (dbnz): Use "DBNZ" class. + * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. + 2024-01-29 Jose E. Marchesi * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index c75e4406046..16fbc8ab007 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -894,6 +894,7 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode) case BI: case BIH: case BRCC: + case DBNZ: case EI: case JLI: case JUMP: diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h index e0415c8021d..4572f7d6590 100644 --- a/opcodes/arc-tbl.h +++ b/opcodes/arc-tbl.h @@ -3656,7 +3656,7 @@ { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, /* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS. */ -{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }}, +{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DBNZ, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }}, /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DPX, { RA, RB, RC }, { C_F }},