From patchwork Sun Dec 24 10:17:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 82817 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F375C3858415 for ; Sun, 24 Dec 2023 10:18:04 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id 183BB3858D3C; Sun, 24 Dec 2023 10:17:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 183BB3858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 183BB3858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703413057; cv=none; b=W39Cdo5Oak1bskfbxrfYEKpMnixsITnpOXAzbEPPJHZS93W0vH5FJhJct84jicF1wyXEahkdJnIovyh48PkJuELy3Ax6dnQrjDZzfVFjbA8cLofacWfdkEY953CNPxJtBj2UWH9oKaik31DO0r5IxYP4hl4gds2emjyKgZT2em0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703413057; c=relaxed/simple; bh=XrbTaazurZKBonx9djsviPncB/hnR5zCwXUtIQ/HclU=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Y9vSt1oRxdf5zh6wSvx/gzoouicgoXXmMhNIz+oKAVNNBLiqQiQu0g/liktkBg4345+p/gDI+wNqkCipURNMybwT3GT/fDgLX49CEdN/RtpTQESjtrVOo6Wb83m1j73TgVTIg5l+zXmy+01WoxSJWEEFd/q+DXkYa83BxAFS4rk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by smtp.gentoo.org (Postfix, from userid 559) id 8C38333D9AD; Sun, 24 Dec 2023 10:17:35 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Cc: hp@sourceware.org Subject: [PATCH] sim: cris: add error fallbacks when decoding condition & swap codes Date: Sun, 24 Dec 2023 05:17:32 -0500 Message-ID: <20231224101732.21071-1-vapier@gentoo.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org The condition & swap code decoder only checks known bits and sets based on that. If the variable is out of range, it ends up returning uninitialized data. Turn that case into a hard error. This fixes build warnings like: sim/cris/semcrisv10f-switch.c:13115:11: error: variable 'tmp_condres' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized] --- cpu/cris.cpu | 6 ++++-- sim/cris/semcrisv10f-switch.c | 12 ++++++++++++ sim/cris/semcrisv32f-switch.c | 12 ++++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/cpu/cris.cpu b/cpu/cris.cpu index 2fcd04e8e361..5d50307e65bf 100644 --- a/cpu/cris.cpu +++ b/cpu/cris.cpu @@ -550,7 +550,8 @@ (condn condc) ((eq tmpcond condn) (set condres (.sym condc -condition)))) (.iota 16) - cris-condition-codes))) + cris-condition-codes)) + (else (error "Unknown condition code"))) condres) ) @@ -3710,7 +3711,8 @@ ((eq tmpcode x-swapcode) (set tmpres ((.sym swap- x-swap) tmpval)))) (.iota 16) - (.splice _ (.unsplice cris-swap-codes))))) + (.splice _ (.unsplice cris-swap-codes)))) + (else (error "Unknown swapcode"))) tmpres) ) diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c index a803809ddc6e..d3967435b20c 100644 --- a/sim/cris/semcrisv10f-switch.c +++ b/sim/cris/semcrisv10f-switch.c @@ -11090,6 +11090,9 @@ SET_H_VBIT_MOVE (0); ; ORSI (ANDSI (SLLSI (tmp_tmpw, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpw, 16), 65535)); }); ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); +} + else { +cgen_rtx_error (current_cpu, "Unknown swapcode"); } ; tmp_tmpres; }); { @@ -12109,6 +12112,9 @@ if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) { } else if (EQSI (tmp_tmpcond, 15)) { tmp_condres = CPU (h_pbit); +} + else { +cgen_rtx_error (current_cpu, "Unknown condition code"); } ; tmp_condres; }); crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval); @@ -12241,6 +12247,9 @@ if (tmp_truthval) { } else if (EQSI (tmp_tmpcond, 15)) { tmp_condres = CPU (h_pbit); +} + else { +cgen_rtx_error (current_cpu, "Unknown condition code"); } ; tmp_condres; }); crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval); @@ -13114,6 +13123,9 @@ SET_H_VBIT_MOVE (0); } else if (EQSI (tmp_tmpcond, 15)) { tmp_condres = CPU (h_pbit); +} + else { +cgen_rtx_error (current_cpu, "Unknown condition code"); } ; tmp_condres; }); { diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c index aa22ea24fd2b..6a23bd76fa51 100644 --- a/sim/cris/semcrisv32f-switch.c +++ b/sim/cris/semcrisv32f-switch.c @@ -11360,6 +11360,9 @@ SET_H_VBIT_MOVE (0); ; ORSI (ANDSI (SLLSI (tmp_tmpw, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpw, 16), 65535)); }); ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); +} + else { +cgen_rtx_error (current_cpu, "Unknown swapcode"); } ; tmp_tmpres; }); { @@ -12509,6 +12512,9 @@ crisv32f_rfg_handler (current_cpu, pc); } else if (EQSI (tmp_tmpcond, 15)) { tmp_condres = CPU (h_pbit); +} + else { +cgen_rtx_error (current_cpu, "Unknown condition code"); } ; tmp_condres; }); crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval); @@ -12641,6 +12647,9 @@ if (tmp_truthval) { } else if (EQSI (tmp_tmpcond, 15)) { tmp_condres = CPU (h_pbit); +} + else { +cgen_rtx_error (current_cpu, "Unknown condition code"); } ; tmp_condres; }); crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval); @@ -13429,6 +13438,9 @@ SET_H_VBIT_MOVE (0); } else if (EQSI (tmp_tmpcond, 15)) { tmp_condres = CPU (h_pbit); +} + else { +cgen_rtx_error (current_cpu, "Unknown condition code"); } ; tmp_condres; }); {