From patchwork Sat Dec 16 02:13:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 82279 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C57E3864C5B for ; Sat, 16 Dec 2023 02:14:08 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id F20EE3858424 for ; Sat, 16 Dec 2023 02:13:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F20EE3858424 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F20EE3858424 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702692836; cv=none; b=Znva+FBcdc7jItMJHzEbfCp+KKVad6+S4Ot+pVQE+uNlXy1SI3Ie+BEI13G7OB4IUBjI/HRzgSMQlZorj5pKsm2Qo3naErgGr4xblEs92K5y0O3+k0WHrUMoNwBpBejPnJWhlxQ3wmh2E6IKKOLuGFZLVNPE6FyTo9CR5tSmpoo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702692836; c=relaxed/simple; bh=INxDAQYO9ISlbvGGZRpdWX4jPNc6LBzLg+zJCn2KS4o=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=JJbrYRVq5lNw6ygqMkbpUPegf+iTvuoJYdENM2VKL9HqSuPJK4NbmpbXMoA5OM/htoAMPO6PONEFyY06tpFC2zOBmXA1sFAN3k6VAN+1s+wDPmV1CU2588BBex+4u91t8rDZgdkXWl4iLRWbcIpy5ffRU/aluldPX9HgpPSmQZU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by smtp.gentoo.org (Postfix, from userid 559) id 59992335DC2; Sat, 16 Dec 2023 02:13:53 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH/committed] sim: mn10300: fix incorrect implementation of a few insns Date: Fri, 15 Dec 2023 21:13:51 -0500 Message-ID: <20231216021351.22709-1-vapier@gentoo.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Fix a few problems caught by compiler warnings: * Some of the asr & lsr insns were setting up the c state flag, but then forgetting to set it in the PSW. Add it like the other asr & lsr variants. * Some of the dmulh insns were multiplying one of the source regs against itself instead of against the other source reg. * The sat16_cmp parallel insn was using the wrong register in the compare -- the reg1 src/dst pair are used in the sat16 op, and the reg2 src/dst pair are used in the add op. --- sim/mn10300/am33.igen | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen index da8f88fa599f..a3a40b78ca6c 100644 --- a/sim/mn10300/am33.igen +++ b/sim/mn10300/am33.igen @@ -2706,7 +2706,7 @@ n = (State.regs[dstreg] & 0x80000000); PSW &= ~(PSW_Z | PSW_N | PSW_C); - PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); } // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd @@ -2730,7 +2730,7 @@ n = (State.regs[dstreg] & 0x80000000); PSW &= ~(PSW_Z | PSW_N | PSW_C); - PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); } // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd @@ -3252,10 +3252,10 @@ dstreg2 = translate_rreg (SD_, RD2); temp = ((int32_t)(State.regs[srcreg1] & 0xffff) - * (int32_t)(State.regs[srcreg1] & 0xffff)); + * (int32_t)(State.regs[srcreg2] & 0xffff)); State.regs[dstreg2] = temp; temp = ((int32_t)((State.regs[srcreg1] >> 16) & 0xffff) - * (int32_t)((State.regs[srcreg1] >>16) & 0xffff)); + * (int32_t)((State.regs[srcreg2] >> 16) & 0xffff)); State.regs[dstreg1] = temp; } @@ -3275,10 +3275,10 @@ dstreg2 = translate_rreg (SD_, RD2); temp = ((uint32_t)(State.regs[srcreg1] & 0xffff) - * (uint32_t)(State.regs[srcreg1] & 0xffff)); + * (uint32_t)(State.regs[srcreg2] & 0xffff)); State.regs[dstreg2] = temp; temp = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff) - * (uint32_t)((State.regs[srcreg1] >>16) & 0xffff)); + * (uint32_t)((State.regs[srcreg2] >> 16) & 0xffff)); State.regs[dstreg1] = temp; } @@ -8646,7 +8646,7 @@ dstreg1 = translate_rreg (SD_, RN1); dstreg2 = translate_rreg (SD_, RN2); - genericCmp (State.regs[dstreg2], State.regs[dstreg1]); + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); if (State.regs[srcreg1] >= 0x7fff) State.regs[dstreg1] = 0x7fff; else if (State.regs[srcreg1] <= 0xffff8000)