From patchwork Thu Dec 7 13:24:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 81672 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 18FA73861816 for ; Thu, 7 Dec 2023 13:24:29 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id 5459F385DC05 for ; Thu, 7 Dec 2023 13:24:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5459F385DC05 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5459F385DC05 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701955456; cv=none; b=UqA4GBTnQGabT4BFLcSUNKlkE1gn3b0lyq6g/tpNQkC1yFfKNUINnCGPmlyh/Tl0xdl1bA5aPCSvdKYcFq54vybI6FJ9rs1MYSUU6GZ8VtnKYSA79P1PhDlLDH6UeupCKLpFkOpG4K4bxNXFl7STLfH9Qm+fAdX6cVoPr7InOSw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701955456; c=relaxed/simple; bh=1V/BMfEdA6WdoEF19GLsHEGloLXbuaSQoLOQrnGVaNk=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=nwwl/ILgRgDiGxQn11v3Y0ciYB+u9emtNCnSYzL34G2y2KjnVJjoNhxlcyK2sbU2TW9K+b5qkV7+7PFqYTPx17ng8zv/gtnw+xr8Wx8LNQf7ibMXM9WirsPMaGzPXK4zxQ9b2FEXdxKw+xk9z9UVHMOKm1RXPnCnLzMh+7/O1Ok= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by smtp.gentoo.org (Postfix, from userid 559) id 99C4C33BE3B; Thu, 7 Dec 2023 13:24:13 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH/committed] sim: m32r: add more cgen prototypes to enable -Werror in most files Date: Thu, 7 Dec 2023 06:24:11 -0700 Message-ID: <20231207132411.31814-1-vapier@gentoo.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org --- sim/Makefile.in | 11 ----------- sim/m32r/local.mk | 11 ----------- sim/m32r/m32r-sim.h | 29 +++++++++++++++++++++++++++-- 3 files changed, 27 insertions(+), 24 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index ec24aa196acf..7fa32b805faa 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -2472,17 +2472,6 @@ testsuite_common_CPPFLAGS = \ # opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable # leak detection while running it. @SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT) -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu2.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpux.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r2.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32rx.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop2.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloopx.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sem.o = -Wno-error -@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sim_if.o = -Wno-error @SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_traps.o = -Wno-error @SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \ @SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.c diff --git a/sim/m32r/local.mk b/sim/m32r/local.mk index db5456753210..182d8879b434 100644 --- a/sim/m32r/local.mk +++ b/sim/m32r/local.mk @@ -17,17 +17,6 @@ ## along with this program. If not, see . ## Some modules don't build cleanly yet. -AM_CFLAGS_%C%_cpu.o = -Wno-error -AM_CFLAGS_%C%_cpu2.o = -Wno-error -AM_CFLAGS_%C%_cpux.o = -Wno-error -AM_CFLAGS_%C%_m32r.o = -Wno-error -AM_CFLAGS_%C%_m32r2.o = -Wno-error -AM_CFLAGS_%C%_m32rx.o = -Wno-error -AM_CFLAGS_%C%_mloop.o = -Wno-error -AM_CFLAGS_%C%_mloop2.o = -Wno-error -AM_CFLAGS_%C%_mloopx.o = -Wno-error -AM_CFLAGS_%C%_sem.o = -Wno-error -AM_CFLAGS_%C%_sim_if.o = -Wno-error AM_CFLAGS_%C%_traps.o = -Wno-error nodist_%C%_libsim_a_SOURCES = \ diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h index 0e1bf82ace54..c72be52e18ae 100644 --- a/sim/m32r/m32r-sim.h +++ b/sim/m32r/m32r-sim.h @@ -39,24 +39,42 @@ extern int m32r_decode_gdb_ctrl_regnum (int); +/* The other cpu cores reuse m32rbf funcs to avoid duplication, but they don't + provide externs to access, and we can't e.g. include decode.h in decodex.h + because of all the redefinitions of cgen macros. */ + +extern void m32rbf_model_insn_before (SIM_CPU *, int); +extern void m32rbf_model_insn_after (SIM_CPU *, int, int); +extern CPUREG_FETCH_FN m32rbf_fetch_register; +extern CPUREG_STORE_FN m32rbf_store_register; +extern void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); + /* Cover macros for hardware accesses. FIXME: Eventually move to cgen. */ #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0) -#ifndef GET_H_CR extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT); extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); +extern USI m32r2f_h_cr_get_handler (SIM_CPU *, UINT); +extern void m32r2f_h_cr_set_handler (SIM_CPU *, UINT, USI); +extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT); +extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI); +#ifndef GET_H_CR #define GET_H_CR(regno) \ XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno)) #define SET_H_CR(regno, val) \ XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val)) #endif -#ifndef GET_H_PSW extern UQI m32rbf_h_psw_get_handler (SIM_CPU *); extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); +extern UQI m32r2f_h_psw_get_handler (SIM_CPU *); +extern void m32r2f_h_psw_set_handler (SIM_CPU *, UQI); +extern UQI m32rxf_h_psw_get_handler (SIM_CPU *); +extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI); +#ifndef GET_H_PSW #define GET_H_PSW() \ XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu) #define SET_H_PSW(val) \ @@ -72,8 +90,15 @@ extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); prototypes for each of the functions it generates. */ extern DI m32rbf_h_accum_get_handler (SIM_CPU *); extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI); +extern DI m32r2f_h_accum_get_handler (SIM_CPU *); +extern void m32r2f_h_accum_set_handler (SIM_CPU *, DI); +extern DI m32rxf_h_accum_get_handler (SIM_CPU *); +extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI); + extern DI m32r2f_h_accums_get_handler (SIM_CPU *, UINT); extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI); +extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT); +extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI); #ifndef GET_H_ACCUM #define GET_H_ACCUM() \