From patchwork Mon Oct 23 21:36:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 78380 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8F1773857C44 for ; Mon, 23 Oct 2023 21:37:21 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by sourceware.org (Postfix) with ESMTPS id 03E083858C2C for ; Mon, 23 Oct 2023 21:37:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 03E083858C2C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 03E083858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::430 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097028; cv=none; b=sM63r0TmI7hP25ti2bGec/eO8EXab9zXoK4DM/bnUlQMZF3leS1xMILWvWXPP6SAVTCZCL2JEj5/++yGDwow6vst/KG7I+gohoVrftIE7iEvav67Gu6D/9mZQHcNJ4mbUols8Er+Q2SmtqKEZ1b5uWB/axK3NkxWYyrZ8YN09gk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097028; c=relaxed/simple; bh=BoHvN498rhA/tBAAwfSg43+0rL0NtgPiLxrEzE2+mgk=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=iEmYQZP3mOxzsHCtkYDW7TNx5UCTh1Z63coF2UBPf0ZYIxu9AErmxBjkYykrhL9vd8+ekEe/ARxfMmitZjEYZCOKXOtUknYt/zUe78J4ZZJUZA1O9gLhCxnkrl8hWdroFpUWV6lmdVsaAMcaNtmpMK2kUIl/pMFXDvmnEME23rU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b7f0170d7bso3617342b3a.2 for ; Mon, 23 Oct 2023 14:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698097025; x=1698701825; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; b=x87WUIAdu3j9yu5UBOOW+mk1ZMGRe2zggm81AsQqD6aUeIRZLQ7dHicDIevxKzbhu6 ZwyM9CiK/UMJgj9zQwfQPzJxoZVXhlQDFHUu2suoQMx6NuVD3yAp3fTRck6hlFLNl/zo aiFCFjRx+Fo171kAVnVFTF4EhV8YbdGsuEd1BLjnubZwQmRtFPSVr0hyS3wNbaDdNhyq 43H++piDWKtqRHgKxTLipbXIe6FGexmQfMy6LrNtqTdrv3VY5utm+LGGXe5oUO0aZ8mY msiWcwZXuxN2Zi+99iUGdmh7+ZlWS2s4tGNg9oEznf6glOzSmrQhf1EHrUWVBue+R+UW x4fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698097025; x=1698701825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NOvdAysXA05qPpMnEVH8JkFq4y3flQAfl9BCWlDaPAI=; b=IfGxjv32ydi9ZVIHQR+79ju2+RTWrdslyDJtbP9cJOdvMaSTKfJfJ8SfUgU7SZ4Obo foSlEwaR7lo4m5MPOF5hqIEK93H9wsMf68WSl2BbSyqpcsCVnrpnvPMVLgAezBHm12s3 brG+ALVNHcivqyYrE/+FxW/A0u8D2Q1OXiRtTKa0ZEjOwEzL/FMEXhBERttsOmRuZvOf fQfc8BVdaa0J6my/ExA8lOx3Gl3geJkBIi3Q2Ud9SAIHdSo61FgzmgNjJHuB3YyDe3Po VBW5bUPIEx2dcU9Q98JXTDnKEDrIhTlb/66pr527CUhRJSUkaOAMsrQc8EtBl+KNWmdy CmEQ== X-Gm-Message-State: AOJu0YyTplnrVdJ3RwBh51ng2E25Ago7n53cVSC4LL8U/PzyXlRO86xb EYRAWiRItuzh/jhkmnfTgu/zZOUwDzXTTbukOzNd2A== X-Google-Smtp-Source: AGHT+IHcx6NqbsjMV10w4Uo96uXAgWEYNbF9WrTmtbxhl7VsGCv7xUtavKBoEJolJ6vh7g6DpAo7iw== X-Received: by 2002:a05:6a21:193:b0:17e:1f9a:91f5 with SMTP id le19-20020a056a21019300b0017e1f9a91f5mr1015543pzb.44.1698097025499; Mon, 23 Oct 2023 14:37:05 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:232:4b54:1e33:3494]) by smtp.gmail.com with ESMTPSA id fe12-20020a056a002f0c00b0066a4e561beesm6819443pfb.173.2023.10.23.14.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 14:37:04 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH 1/3] powerpc: Do not raise exception traps for fesetexcept/fesetexceptflag (BZ 30988) Date: Mon, 23 Oct 2023 18:36:57 -0300 Message-Id: <20231023213659.3236496-2-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> References: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). This is a side-effect of how we implement the GNU extension feenableexcept, where feenableexcept/fesetenv/fesetmode/feupdateenv might issue prctl (PR_SET_FPEXC, PR_FP_EXC_PRECISE) depending of the argument. And on PR_FP_EXC_PRECISE, setting a floating-point exception flag triggers a trap. To make the both functions follow the C23, fesetexcept and fesetexceptflag now fail if the argument may trigger a trap. The math tests now check for an value different than 0, instead of bail out as unsupported for EXCEPTION_SET_FORCES_TRAP. Checked on powerpc64le-linux-gnu. --- math/test-fesetexcept-traps.c | 11 ++++------- math/test-fexcept-traps.c | 11 ++++------- sysdeps/powerpc/fpu/fesetexcept.c | 5 +++++ sysdeps/powerpc/fpu/fsetexcptflg.c | 9 ++++++++- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 71b6e45b33..96f6c4752f 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -39,16 +39,13 @@ do_test (void) return result; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* Verify fesetexcept does not cause exception traps. */ + /* Verify fesetexcept does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); - else + else if (!EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexcept (FE_ALL_EXCEPT) failed"); if (EXCEPTION_TESTS (float)) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9701c3c320..9b8f583ae6 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -63,14 +63,11 @@ do_test (void) result = 1; } - if (EXCEPTION_SET_FORCES_TRAP) - { - puts ("setting exceptions traps, cannot test on this architecture"); - return 77; - } - /* The test is that this does not cause exception traps. */ + /* The test is that this does not cause exception traps. For architectures + where setting the exception might result in traps the function should + return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); - if (ret != 0) + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); result = 1; diff --git a/sysdeps/powerpc/fpu/fesetexcept.c b/sysdeps/powerpc/fpu/fesetexcept.c index 609a148a95..2850156d3a 100644 --- a/sysdeps/powerpc/fpu/fesetexcept.c +++ b/sysdeps/powerpc/fpu/fesetexcept.c @@ -31,6 +31,11 @@ fesetexcept (int excepts) & FE_INVALID_SOFTWARE)); if (n.l != u.l) { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + fesetenv_register (n.fenv); /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index 2b22f913c0..6517e8ea03 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -44,7 +44,14 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) This may cause floating-point exceptions if the restored state requests it. */ if (n.l != u.l) - fesetenv_register (n.fenv); + { + if (n.l & fenv_exceptions_to_reg (excepts)) + /* Setting the exception flags may trigger a trap. ISO C 23 § 7.6.4.4 + does not allow it. */ + return -1; + + fesetenv_register (n.fenv); + } /* Deal with FE_INVALID_SOFTWARE not being implemented on some chips. */ if (flag & FE_INVALID) From patchwork Mon Oct 23 21:36:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 78381 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D67953856DC6 for ; Mon, 23 Oct 2023 21:37:40 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id D32B43858410 for ; Mon, 23 Oct 2023 21:37:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D32B43858410 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D32B43858410 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::42f ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097030; cv=none; b=s20lJ6Hkjp62bitrVrimV18rOimtMqD38C1Ejr9DFJq3s63aoE+lCineGxvKhpGuzVb+BMhJzl5wObd6JGAvkDiEM0oGLYwMaDGA2khWRfd5wEcCuPEcjclhCWNmSdG5PbYnRALPrOa2UorvPGnVZWDLl1RCOO+pQjRjLU/ON1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097030; c=relaxed/simple; bh=8U8Nhj1fuh3PG40nimc7iSYU1s2WrtmRJcqYWR8ax7E=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=lSUFqyDiScNQqTBFli53IkcA82GB9mZj7DoBAf8cy3qNnFQEn1AYcF6OoBRUpB+5bYrWSwtt/1Yk4xwac+NvHK8qcCFJoHG7fGDuncjAtU1zNFAb1ISCGGBjA70uqS0JM6MWZE3KjJehBBfECziO7kiMv1Po4HHHtIpF0KFYlgk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6b87c1edfd5so2916222b3a.1 for ; Mon, 23 Oct 2023 14:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698097027; x=1698701827; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rf/HRFBHeyiybHiS9O3Be3TfMfF1DsAPHz9Yj4poVI0=; b=opxZvSVMiSgcwFDZU5Gcp41HMwzBF+AQjZ8LfDSS3I9H/NR51XcF8Wf7cTUaopY84b zvlZ1A+CwzIt3vrkxKQdrb/TD3hQyniWGmitZeytURInobZh7cI5WIrA51xKeCdMCFHV 7vKUJeDCA/562hH9XFEjIcS/2YUEUQFOx/eZjeqg7sUkpZqKWg7JxEjAkCW1eAeuPJ+6 vmJFMKTi1YHyCpRjKa9yZLEd5bm5JFGHE/2JIruteHYpZ0sjKOnxBQ0zjP20F4q4c+s2 tc+MFiwUflUOXchLWbrN+XY6y9T/9gEDmuNZxpqRC9hw8ATMZsl4182/TVdF94lnZb+o Ljcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698097027; x=1698701827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rf/HRFBHeyiybHiS9O3Be3TfMfF1DsAPHz9Yj4poVI0=; b=rcypxgWXNReGVp9sOsNSGA3IEYpj/ezawFKhvM9cTzVpp2hkdBtsuAQ4f4XVCPsyK5 XkrfMVyCbpRNybOmOwzlW/Sj7aNuP9eOuImYL2YOnCw+fgIxnC5u/kFHc0GnhS+hjwxT kPNXCU+7KIdfUhiFNnZ15Ed6xrGK+0t8rQzwIPIch9csD2UWL1mXFjU69K/wpKLeTTUj hAAD6I4Fr9yezS/8xWUiWVv4aJB1IMf9XlZ2yo44VTnRENvwzwUsgcrpecntHAfTWtxM QOiLGRj9tH53BrYJildIZWTvToCKuAKDeh7oCHdcMLTqjMa880iAeQIw32l++sQqnneD 3TBQ== X-Gm-Message-State: AOJu0YzTqLCCFm34oRObis+eI+I8shKhxZzZkxhwoniM9YuLiZayRzcP 42y+uONor6EADASjIKEeUbZgkXpOBtCi6sXRW6v0CQ== X-Google-Smtp-Source: AGHT+IFiICOcSChbw+ehjKAUWuc35iwkNMR4SW8uhls5cFYNTWlhDoy0pSA+nDUtwbKDAxAqEuV6Ug== X-Received: by 2002:a05:6a20:158b:b0:17a:eddb:ac65 with SMTP id h11-20020a056a20158b00b0017aeddbac65mr893683pzj.9.1698097027266; Mon, 23 Oct 2023 14:37:07 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:232:4b54:1e33:3494]) by smtp.gmail.com with ESMTPSA id fe12-20020a056a002f0c00b0066a4e561beesm6819443pfb.173.2023.10.23.14.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 14:37:06 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH 2/3] i686: Do not raise exception traps on fesetexcept (BZ 30989) Date: Mon, 23 Oct 2023 18:36:58 -0300 Message-Id: <20231023213659.3236496-3-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> References: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org According to ISO C23 (7.6.4.4), fesetexcept is supposed to set floating-point exception flags without raising a trap (unlike feraiseexcept, which is supposed to raise a trap if feenableexcept was called with the appropriate argument). The flags can be set in the 387 unit or in the SSE unit. To set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Checked on i686-linux-gnu. --- math/test-fesetexcept-traps.c | 11 ++++++ sysdeps/i386/fpu/fesetexcept.c | 43 ++++++++++++++++++++++-- sysdeps/i386/fpu/math-tests-trap-force.h | 29 ++++++++++++++++ 3 files changed, 81 insertions(+), 2 deletions(-) create mode 100644 sysdeps/i386/fpu/math-tests-trap-force.h diff --git a/math/test-fesetexcept-traps.c b/math/test-fesetexcept-traps.c index 96f6c4752f..122c23eb7e 100644 --- a/math/test-fesetexcept-traps.c +++ b/math/test-fesetexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -43,6 +44,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexcept (FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + double a = 1.0; + double b = a + a; + math_force_eval (b); + long double al = 1.0L; + long double bl = al + al; + math_force_eval (bl); + if (ret == 0) puts ("fesetexcept (FE_ALL_EXCEPT) succeeded"); else if (!EXCEPTION_SET_FORCES_TRAP) diff --git a/sysdeps/i386/fpu/fesetexcept.c b/sysdeps/i386/fpu/fesetexcept.c index 18949e982a..a4c70cd1d1 100644 --- a/sysdeps/i386/fpu/fesetexcept.c +++ b/sysdeps/i386/fpu/fesetexcept.c @@ -17,15 +17,54 @@ . */ #include +#include int fesetexcept (int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. To set a flag, + it is sufficient to do it in the SSE unit, because that is guaranteed to + not trap. However, on i386 CPUs that have only a 387 unit, set the flags + in the 387, as long as this cannot trap. */ + fenv_t temp; + excepts &= FE_ALL_EXCEPT; + __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word |= excepts & FE_ALL_EXCEPT; - __asm__ ("fldenv %0" : : "m" (*&temp)); + + if (CPU_FEATURE_USABLE (SSE)) + { + /* Clear relevant flags. */ + temp.__status_word &= ~excepts; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + + /* And now similarly for SSE. */ + unsigned int mxcsr; + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Set relevant flags. */ + mxcsr |= excepts & FE_ALL_EXCEPT; + + /* Put the new data in effect. */ + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= temp.__status_word & excepts; + + if (temp.__control_word & temp.__status_word & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); + } return 0; } diff --git a/sysdeps/i386/fpu/math-tests-trap-force.h b/sysdeps/i386/fpu/math-tests-trap-force.h new file mode 100644 index 0000000000..d88229c271 --- /dev/null +++ b/sysdeps/i386/fpu/math-tests-trap-force.h @@ -0,0 +1,29 @@ +/* Configuration for math tests: support for setting exception flags + without causing enabled traps. i686 version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef I386_FPU_MATH_TESTS_TRAP_FORCE_H +#define I386_FPU_MATH_TESTS_TRAP_FORCE_H 1 + +#include + +/* Setting exception flags in FPSCR results in enabled traps for those + exceptions being taken. */ +#define EXCEPTION_SET_FORCES_TRAP (CPU_FEATURE_USABLE (SSE)) + +#endif /* math-tests-trap-force.h. */ From patchwork Mon Oct 23 21:36:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 78382 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 34E183857712 for ; Mon, 23 Oct 2023 21:37:49 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id D10263857009 for ; Mon, 23 Oct 2023 21:37:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D10263857009 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D10263857009 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::436 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097034; cv=none; b=QBiAg+Z8OSDMPjvL++v0fd5EYx4TLRkK7EmWEGDTKzVfv5EMsR245x6YrqL+zFbG1uf96du5CCbotipQjJ2Q30g92Niqj5W62J3XGmjvgrYK/A3n/6hv8ZHR0B7s56Qc9+Ted/EZP9FQyERlov0nPFvkyGK7i3tatX0JBey5AuI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097034; c=relaxed/simple; bh=mzOfBSSLNJoBa8H8yXePyTj4wP8ZGeTsQXSgokPD+hw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=dyaZx7vm66/A1qbNIUc+tDxsYeiPB2djR34EbyBTMStHqhAXhSA7kZzmTJsZU+MwDVYjRZvbP8o1vBVDJ6hpHapl684ERW7blXr7aiyEWAJGXSSrDGMaPhbPKTid0HwB/y90ztV4au1xpvdovCO7ku2b1amB1+WzBgv/rAz1Cx4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6b709048d8eso2905367b3a.2 for ; Mon, 23 Oct 2023 14:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698097031; x=1698701831; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fVL3fJeVFgDyC8rls6M1r3FJNHubHp4CEVWJzTH5jeQ=; b=v8+D0nwnQTNt4WPppzNzL2OPk7iHKTzhvwmyq14lmXF0xOEQmgpVpElgugQtON6rC4 Dp998E1BvbJEtz7y6Tewmk6iNDCOkGHY76HbYN46EpGiFZlgBJKpsJp+6i0TG9nvThJo Oc1R6d3A01lQ5nJrBcHpim2r4GUmMklF5bGr35Iapd/tHjO+zuH+1zkcI0IQahDzeI99 rDJuX3nB7giXIs7igiSA6DSr8eBtqalm/orDN1kEwiBjNPxLt2g0uG7jfk0CYSlnibSY uE6BAUlBLRdmjMsHjMQqqJZ4ieWF1H7c8VN2nk+4JQ+nyj6CXPbwvJGFbVBG3vlCTElC /eLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698097031; x=1698701831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fVL3fJeVFgDyC8rls6M1r3FJNHubHp4CEVWJzTH5jeQ=; b=WLDbPomBGwhRORnyHngnqYFaHOIN8xqgwbJvHpgqclj42bU78Vh75Av+Bpn6HGdQ7v SaOBpcvgxUYyYUKXPhhu1ADZvUuN23yjbEsCIsdMwjw/xmxjEJFL9hIbIVM79ytK/8sF T5vCtOcIyTu/8LrCJ5tSEMnTpQ4YpVQ85XWweMzvC49UW6AbcCzGvmiLz6fh4CNWYVSz 4k4WNzOGX9ITFcXNQ3C5H0y9iHdOzc3wpzoI3qHyXoTTao2dWz8u8VCrFetj7804dfg/ g6jruMSsn6sQD0PPSpWPIAKp9wIMYjKu62sm0kp1cJryYtVhOnz653fE/HCBanqmJZs6 u8/Q== X-Gm-Message-State: AOJu0YxIXmJQc4atRSrS2eQIpRR36FbzQ/3BbVZBOEVPe5CZLwWF5CK8 8E+FXY2xncfWYxaIgARtOpUSGoxkARRDqxfJ4LD1hg== X-Google-Smtp-Source: AGHT+IHWFmsQqk5DrkUtsy1p+RIB6ngbk70gEvaa6vYPAAoS4Hhf01jdHQHTFkGOjlZO7QnqTcxWlA== X-Received: by 2002:a05:6a00:1953:b0:6be:b7c:f703 with SMTP id s19-20020a056a00195300b006be0b7cf703mr8560800pfk.5.1698097031234; Mon, 23 Oct 2023 14:37:11 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:232:4b54:1e33:3494]) by smtp.gmail.com with ESMTPSA id fe12-20020a056a002f0c00b0066a4e561beesm6819443pfb.173.2023.10.23.14.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 14:37:10 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH 3/3] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Mon, 23 Oct 2023 18:36:59 -0300 Message-Id: <20231023213659.3236496-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> References: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.5), fesetexceptflag is supposed to set floating-point exception flags without raising a trap. The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella --- math/test-fexcept-traps.c | 11 ++++++ sysdeps/i386/fpu/fsetexcptflg.c | 58 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++------ 3 files changed, 62 insertions(+), 31 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..a486d17951 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -67,6 +68,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + double a = 1.0; + double b = a + a; + math_force_eval (b); + long double al = 1.0L; + long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..ccbcf35e8e 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,58 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 § 7.6.4.5 does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */