From patchwork Thu Jul 1 17:11:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 44071 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 015CC396EC7E for ; Thu, 1 Jul 2021 17:12:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 015CC396EC7E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1625159558; bh=jBBjudixQgJ1MKUjPTmuV7XBwq1Ock6HELEd1w2qsac=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=DxlvJe/cxdowuQjtNa3cCT7wDyuWvCbw0Y6T0ygSV/H+jg+k0xF1pEVnRmrpTJiR5 hYZXLTzSyQVnkCexwHX6Nrlql3xTu/9gWHEiIIUoaISUXNoOIW237Fe9Y+XR6vJ+Tq s9xRzyUOLmZkAPZmXNwUXoO0HxWp0xQbCVOa2Ulw= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by sourceware.org (Postfix) with ESMTPS id A756D3857419 for ; Thu, 1 Jul 2021 17:12:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A756D3857419 Received: by mail-pg1-x529.google.com with SMTP id w15so6669871pgk.13 for ; Thu, 01 Jul 2021 10:12:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jBBjudixQgJ1MKUjPTmuV7XBwq1Ock6HELEd1w2qsac=; b=FZTmpzI9KB3PjkmlqWw0cuY0K9T+mFnptL8mxXDoLg5UnCbvY25gqgxIm9nF72XkjM /wIDLowmeLaZKErP9ZE6B3PzGbhTCHIKtbztUXlOpwkN2fUbYbprKoX2o/SJz/z7azxV +48ou77CVXtHGOs+zQSwMkOp82qyHeDWn6f+Li6MBNwOrANHUiMdWWt8GoCNbm8fESd1 6EOPUI2j7qixWPcwMwQnMRBTP1WhBPlIdM4mBNuhBK1NhlchX2IrjRvggFYO0pAeQwOq X/3PeYEXTUxoFl4PSzyz6lpqLEAhASNJk8l1WBh9O8FesYM5Q3r5qSjK46q9uPFjKZZY ghmQ== X-Gm-Message-State: AOAM53082SzSKRLOQ5j0qTjk7NRYjX/TX1JaXiZPuSVBQgoGVV0H8sMU lcSvuvN+d5L37yNq7HWrUr79P637d9sxVAEhUoY= X-Google-Smtp-Source: ABdhPJw/SD/wjWDZ8eLpdVbUWaUJxyFHuxUl+SUbIH8Wv4WM+a14iMm/rlNtS6bwLwRPvlrjmzlfoOZ69cwscGnzCIk= X-Received: by 2002:a62:7f91:0:b029:312:658d:b593 with SMTP id a139-20020a627f910000b0290312658db593mr1048393pfd.48.1625159533728; Thu, 01 Jul 2021 10:12:13 -0700 (PDT) MIME-Version: 1.0 References: <20210630183919.1004153-1-hjl.tools@gmail.com> <87a6n62e5c.fsf@oldenburg.str.redhat.com> In-Reply-To: <87a6n62e5c.fsf@oldenburg.str.redhat.com> Date: Thu, 1 Jul 2021 10:11:37 -0700 Message-ID: Subject: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] To: Florian Weimer X-Spam-Status: No, score=-3032.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Libc-alpha" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: "H.J. Lu via Libc-alpha" Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" On Thu, Jul 1, 2021 at 9:27 AM Florian Weimer wrote: > > * H. J. Lu via Libc-alpha: > > > From > > > > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html > > > > A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, > > which is set to indicate to updated software that the loaded microcode is > > forcing RTM abort. > > > > 1. Add RTM_ALWAYS_ABORT to CPUID features. > > 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. > > 3. Check RTM feature, instead of usability, against /proc/cpuinfo. > > Maybe not that this fixes the string/tst-memchr-rtm etc. test cases > after a microcde update? I changed it to 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. > > diff --git a/manual/platform.texi b/manual/platform.texi > > index 4cd029cfad..8ec7f385e9 100644 > > --- a/manual/platform.texi > > +++ b/manual/platform.texi > > @@ -525,6 +525,9 @@ capability. > > @item > > @code{RTM} -- RTM instruction extensions. > > > > +@item > > +@code{RTM_ALWAYS_ABORT} -- Abort all transactions. > > I think this means “Transactions always abort, making RTM unusable.” > (with unusable in both senses, !CPU_FEATURE_USABLE, and not useful). Fixed. > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > > index a1d8d11cc4..d9093f11ac 100644 > > --- a/sysdeps/x86/cpu-features.c > > +++ b/sysdeps/x86/cpu-features.c > > @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features) > > CPU_FEATURE_SET_USABLE (cpu_features, HLE); > > CPU_FEATURE_SET_USABLE (cpu_features, BMI2); > > CPU_FEATURE_SET_USABLE (cpu_features, ERMS); > > - CPU_FEATURE_SET_USABLE (cpu_features, RTM); > > CPU_FEATURE_SET_USABLE (cpu_features, RDSEED); > > CPU_FEATURE_SET_USABLE (cpu_features, ADX); > > CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT); > > @@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features) > > CPU_FEATURE_SET_USABLE (cpu_features, FSRCS); > > CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE); > > > > + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT)) > > + CPU_FEATURE_SET_USABLE (cpu_features, RTM); > > + > > #if CET_ENABLED > > CPU_FEATURE_SET_USABLE (cpu_features, IBT); > > CPU_FEATURE_SET_USABLE (cpu_features, SHSTK); > > Is some change necessary to copy RTM_ALWAYS_ABORT to USABLE as well? Added. > Any idea why the microcode update doesn't just clear the RPM bit in > CPUID? This is a bit awkward. I asked it internally. > Thanks, > Florian > Here is the v2 patch. OK for master? Thanks. From 233a9d8ca75b56e35f6dc4ccd64f72872edf9d95 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Wed, 30 Jun 2021 10:47:06 -0700 Subject: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] From https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html * Intel TSX will be disabled by default. * The processor will force abort all Restricted Transactional Memory (RTM) transactions by default. * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. * On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to be set by default after microcode update. * Workloads that were benefited from Intel TSX might experience a change in performance. * System software may use a new bit in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled. 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. This fixes BZ #28033. --- manual/platform.texi | 3 +++ sysdeps/x86/bits/platform/x86.h | 2 +- sysdeps/x86/cpu-features.c | 5 ++++- sysdeps/x86/include/cpu-features.h | 6 +++--- sysdeps/x86/tst-cpu-features-supports.c | 2 +- sysdeps/x86/tst-get-cpu-features.c | 2 ++ 6 files changed, 14 insertions(+), 6 deletions(-) diff --git a/manual/platform.texi b/manual/platform.texi index 4cd029cfad..037dfc4f20 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -525,6 +525,9 @@ capability. @item @code{RTM} -- RTM instruction extensions. +@item +@code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable. + @item @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug. diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h index 26e3b67ede..5509b1ad87 100644 --- a/sysdeps/x86/bits/platform/x86.h +++ b/sysdeps/x86/bits/platform/x86.h @@ -211,7 +211,7 @@ enum x86_cpu_AVX512_VP2INTERSECT = x86_cpu_index_7_edx + 8, x86_cpu_INDEX_7_EDX_9 = x86_cpu_index_7_edx + 9, x86_cpu_MD_CLEAR = x86_cpu_index_7_edx + 10, - x86_cpu_INDEX_7_EDX_11 = x86_cpu_index_7_edx + 11, + x86_cpu_RTM_ALWAYS_ABORT = x86_cpu_index_7_edx + 11, x86_cpu_INDEX_7_EDX_12 = x86_cpu_index_7_edx + 12, x86_cpu_INDEX_7_EDX_13 = x86_cpu_index_7_edx + 13, x86_cpu_SERIALIZE = x86_cpu_index_7_edx + 14, diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index a1d8d11cc4..563a206ac1 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, HLE); CPU_FEATURE_SET_USABLE (cpu_features, BMI2); CPU_FEATURE_SET_USABLE (cpu_features, ERMS); - CPU_FEATURE_SET_USABLE (cpu_features, RTM); CPU_FEATURE_SET_USABLE (cpu_features, RDSEED); CPU_FEATURE_SET_USABLE (cpu_features, ADX); CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT); @@ -83,6 +82,7 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, MOVDIRI); CPU_FEATURE_SET_USABLE (cpu_features, MOVDIR64B); CPU_FEATURE_SET_USABLE (cpu_features, FSRM); + CPU_FEATURE_SET_USABLE (cpu_features, RTM_ALWAYS_ABORT); CPU_FEATURE_SET_USABLE (cpu_features, SERIALIZE); CPU_FEATURE_SET_USABLE (cpu_features, TSXLDTRK); CPU_FEATURE_SET_USABLE (cpu_features, LAHF64_SAHF64); @@ -97,6 +97,9 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, FSRCS); CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE); + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT)) + CPU_FEATURE_SET_USABLE (cpu_features, RTM); + #if CET_ENABLED CPU_FEATURE_SET_USABLE (cpu_features, IBT); CPU_FEATURE_SET_USABLE (cpu_features, SHSTK); diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 4f1c4ee402..59e01df543 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -229,7 +229,7 @@ enum #define bit_cpu_AVX512_VP2INTERSECT (1u << 8) #define bit_cpu_INDEX_7_EDX_9 (1u << 9) #define bit_cpu_MD_CLEAR (1u << 10) -#define bit_cpu_INDEX_7_EDX_11 (1u << 11) +#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11) #define bit_cpu_INDEX_7_EDX_12 (1u << 12) #define bit_cpu_INDEX_7_EDX_13 (1u << 13) #define bit_cpu_SERIALIZE (1u << 14) @@ -463,7 +463,7 @@ enum #define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7 #define index_cpu_MD_CLEAR CPUID_INDEX_7 -#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7 +#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7 #define index_cpu_SERIALIZE CPUID_INDEX_7 @@ -697,7 +697,7 @@ enum #define reg_AVX512_VP2INTERSECT edx #define reg_INDEX_7_EDX_9 edx #define reg_MD_CLEAR edx -#define reg_INDEX_7_EDX_11 edx +#define reg_RTM_ALWAYS_ABORT edx #define reg_INDEX_7_EDX_12 edx #define reg_INDEX_7_EDX_13 edx #define reg_SERIALIZE edx diff --git a/sysdeps/x86/tst-cpu-features-supports.c b/sysdeps/x86/tst-cpu-features-supports.c index a2cabc90be..867ea6b8e8 100644 --- a/sysdeps/x86/tst-cpu-features-supports.c +++ b/sysdeps/x86/tst-cpu-features-supports.c @@ -153,7 +153,7 @@ do_test (int argc, char **argv) fails += CHECK_SUPPORTS (rdpid, RDPID); fails += CHECK_SUPPORTS (rdrnd, RDRAND); fails += CHECK_SUPPORTS (rdseed, RDSEED); - fails += CHECK_SUPPORTS (rtm, RTM); + fails += CHECK_CPU_SUPPORTS (rtm, RTM); fails += CHECK_SUPPORTS (serialize, SERIALIZE); fails += CHECK_SUPPORTS (sha, SHA); fails += CHECK_CPU_SUPPORTS (shstk, SHSTK); diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c index 583e1e6d49..11fa3054b9 100644 --- a/sysdeps/x86/tst-get-cpu-features.c +++ b/sysdeps/x86/tst-get-cpu-features.c @@ -158,6 +158,7 @@ do_test (void) CHECK_CPU_FEATURE (UINTR); CHECK_CPU_FEATURE (AVX512_VP2INTERSECT); CHECK_CPU_FEATURE (MD_CLEAR); + CHECK_CPU_FEATURE (RTM_ALWAYS_ABORT); CHECK_CPU_FEATURE (SERIALIZE); CHECK_CPU_FEATURE (HYBRID); CHECK_CPU_FEATURE (TSXLDTRK); @@ -322,6 +323,7 @@ do_test (void) CHECK_CPU_FEATURE_USABLE (FSRM); CHECK_CPU_FEATURE_USABLE (AVX512_VP2INTERSECT); CHECK_CPU_FEATURE_USABLE (MD_CLEAR); + CHECK_CPU_FEATURE_USABLE (RTM_ALWAYS_ABORT); CHECK_CPU_FEATURE_USABLE (SERIALIZE); CHECK_CPU_FEATURE_USABLE (HYBRID); CHECK_CPU_FEATURE_USABLE (TSXLDTRK); -- 2.31.1