From patchwork Fri Jul 14 15:51:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72705 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 503513852648 for ; Fri, 14 Jul 2023 15:57:04 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id 7D6123858C78 for ; Fri, 14 Jul 2023 15:55:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7D6123858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 848031A84C70; Fri, 14 Jul 2023 11:55:49 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Cc: Aleksandar Paunovic Subject: [PATCH v6 01/15] x86: Add an x86_xsave_layout structure to handle variable XSAVE layouts. Date: Fri, 14 Jul 2023 08:51:37 -0700 Message-Id: <20230714155151.21723-2-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:49 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" The standard layout of the XSAVE extended state area consists of three regions. The first 512 bytes (legacy region) match the layout of the FXSAVE instruction including floating point registers, MMX registers, and SSE registers. The next 64 bytes (XSAVE header) contains a header with a fixed layout. The final region (extended region) contains zero or more optional state components. Examples of these include the upper 128 bits of YMM registers for AVX. These optional state components generally have an architecturally-fixed size, but they are not assigned architectural offsets in the extended region. Instead, processors provide additional CPUID leafs describing the size and offset of each component in the "standard" layout for a given CPU. (There is also a "compact" format which uses an alternate layout, but existing OS's currently export the "standard" layout when exporting XSAVE data via ptrace() and core dumps.) To date, GDB has assumed the layout used on current Intel processors for state components in the extended region and hardcoded those offsets in the tables in i387-tdep.c and i387-fp.cc. However, this fails on recent AMD processors which use a different layout. Specifically, AMD Zen3 and later processors do not leave space for the MPX register set in between the AVX and AVX512 register sets. To rectify this, add an x86_xsave_layout structure which contains the total size of the XSAVE extended state area as well as the offset of each known optional state component. Subsequent commits will modify XSAVE parsing in both gdb and gdbserver to use x86_xsave_layout. Co-authored-by: Aleksandar Paunovic --- gdbsupport/x86-xstate.h | 65 +++++++++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 9 deletions(-) diff --git a/gdbsupport/x86-xstate.h b/gdbsupport/x86-xstate.h index b8740fd8701..27fc0bd12f2 100644 --- a/gdbsupport/x86-xstate.h +++ b/gdbsupport/x86-xstate.h @@ -20,22 +20,69 @@ #ifndef COMMON_X86_XSTATE_H #define COMMON_X86_XSTATE_H +/* The extended state feature IDs in the state component bitmap. */ +#define X86_XSTATE_X87_ID 0 +#define X86_XSTATE_SSE_ID 1 +#define X86_XSTATE_AVX_ID 2 +#define X86_XSTATE_BNDREGS_ID 3 +#define X86_XSTATE_BNDCFG_ID 4 +#define X86_XSTATE_K_ID 5 +#define X86_XSTATE_ZMM_H_ID 6 +#define X86_XSTATE_ZMM_ID 7 +#define X86_XSTATE_PKRU_ID 9 + /* The extended state feature bits. */ -#define X86_XSTATE_X87 (1ULL << 0) -#define X86_XSTATE_SSE (1ULL << 1) -#define X86_XSTATE_AVX (1ULL << 2) -#define X86_XSTATE_BNDREGS (1ULL << 3) -#define X86_XSTATE_BNDCFG (1ULL << 4) +#define X86_XSTATE_X87 (1ULL << X86_XSTATE_X87_ID) +#define X86_XSTATE_SSE (1ULL << X86_XSTATE_SSE_ID) +#define X86_XSTATE_AVX (1ULL << X86_XSTATE_AVX_ID) +#define X86_XSTATE_BNDREGS (1ULL << X86_XSTATE_BNDREGS_ID) +#define X86_XSTATE_BNDCFG (1ULL << X86_XSTATE_BNDCFG_ID) #define X86_XSTATE_MPX (X86_XSTATE_BNDREGS | X86_XSTATE_BNDCFG) /* AVX 512 adds three feature bits. All three must be enabled. */ -#define X86_XSTATE_K (1ULL << 5) -#define X86_XSTATE_ZMM_H (1ULL << 6) -#define X86_XSTATE_ZMM (1ULL << 7) +#define X86_XSTATE_K (1ULL << X86_XSTATE_K_ID) +#define X86_XSTATE_ZMM_H (1ULL << X86_XSTATE_ZMM_H_ID) +#define X86_XSTATE_ZMM (1ULL << X86_XSTATE_ZMM_ID) #define X86_XSTATE_AVX512 (X86_XSTATE_K | X86_XSTATE_ZMM_H \ | X86_XSTATE_ZMM) -#define X86_XSTATE_PKRU (1ULL << 9) +#define X86_XSTATE_PKRU (1ULL << X86_XSTATE_PKRU_ID) + +/* Size and offsets of register states in the XSAVE area extended + region. Offsets are set to 0 to indicate the absence of the + associated registers. */ + +struct x86_xsave_layout +{ + int sizeof_xsave = 0; + int avx_offset = 0; + int bndregs_offset = 0; + int bndcfg_offset = 0; + int k_offset = 0; + int zmm_h_offset = 0; + int zmm_offset = 0; + int pkru_offset = 0; +}; + +constexpr bool operator== (const x86_xsave_layout &lhs, + const x86_xsave_layout &rhs) +{ + return lhs.sizeof_xsave == rhs.sizeof_xsave + && lhs.avx_offset == rhs.avx_offset + && lhs.bndregs_offset == rhs.bndregs_offset + && lhs.bndcfg_offset == rhs.bndcfg_offset + && lhs.k_offset == rhs.k_offset + && lhs.zmm_h_offset == rhs.zmm_h_offset + && lhs.zmm_offset == rhs.zmm_offset + && lhs.pkru_offset == rhs.pkru_offset; +} + +constexpr bool operator!= (const x86_xsave_layout &lhs, + const x86_xsave_layout &rhs) +{ + return !(lhs == rhs); +} + /* Supported mask and size of the extended state. */ #define X86_XSTATE_X87_MASK X86_XSTATE_X87 From patchwork Fri Jul 14 15:51:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72699 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CC5FB385AF8F for ; Fri, 14 Jul 2023 15:56:26 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id 3A5473858C54 for ; Fri, 14 Jul 2023 15:55:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3A5473858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 281811A84C72; Fri, 14 Jul 2023 11:55:50 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Cc: Simon Marchi Subject: [PATCH v6 02/15] gdb: Store an x86_xsave_layout in i386_gdbarch_tdep. Date: Fri, 14 Jul 2023 08:51:38 -0700 Message-Id: <20230714155151.21723-3-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:50 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" This structure is fetched from the current target in i386_gdbarch_init via a new "fetch_x86_xsave_layout" target method. Approved-By: Simon Marchi --- gdb/i386-tdep.c | 18 +++++++++++++++--- gdb/i386-tdep.h | 4 ++++ gdb/target-debug.h | 20 ++++++++++++++++++++ gdb/target-delegates.c | 27 +++++++++++++++++++++++++++ gdb/target.c | 6 ++++++ gdb/target.h | 7 +++++++ 6 files changed, 79 insertions(+), 3 deletions(-) diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index a97e11647b9..d5423681802 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -8504,10 +8504,21 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) int bnd0_regnum; int num_bnd_cooked; + x86_xsave_layout xsave_layout = target_fetch_x86_xsave_layout (); + /* If there is already a candidate, use it. */ - arches = gdbarch_list_lookup_by_info (arches, &info); - if (arches != NULL) - return arches->gdbarch; + for (arches = gdbarch_list_lookup_by_info (arches, &info); + arches != NULL; + arches = gdbarch_list_lookup_by_info (arches->next, &info)) + { + /* Check that the XSAVE layout of ARCHES matches the layout for + the current target. */ + i386_gdbarch_tdep *other_tdep + = gdbarch_tdep (arches->gdbarch); + + if (other_tdep->xsave_layout == xsave_layout) + return arches->gdbarch; + } /* Allocate space for the new architecture. Assume i386 for now. */ gdbarch *gdbarch @@ -8762,6 +8773,7 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) gdbarch_free (gdbarch); return NULL; } + tdep->xsave_layout = xsave_layout; num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index bf52020ab67..34dc53db8d9 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -23,6 +23,7 @@ #include "gdbarch.h" #include "infrun.h" #include "expression.h" +#include "gdbsupport/x86-xstate.h" class frame_info_ptr; struct gdbarch; @@ -145,6 +146,9 @@ struct i386_gdbarch_tdep : gdbarch_tdep_base /* Offset of XCR0 in XSAVE extended state. */ int xsave_xcr0_offset = 0; + /* Layout of the XSAVE area extended region. */ + x86_xsave_layout xsave_layout; + /* Register names. */ const char * const *register_names = nullptr; diff --git a/gdb/target-debug.h b/gdb/target-debug.h index acb01d47e7c..6b8983104ea 100644 --- a/gdb/target-debug.h +++ b/gdb/target-debug.h @@ -236,4 +236,24 @@ target_debug_print_gdb_byte_vector_r (gdb::byte_vector &vector) { target_debug_print_const_gdb_byte_vector_r (vector); } + +static void +target_debug_print_x86_xsave_layout (const x86_xsave_layout &layout) +{ + gdb_puts ("{", gdb_stdlog); + gdb_printf (gdb_stdlog, " sizeof_xsave=%d", layout.sizeof_xsave); +#define POFFS(region) \ + if (layout.region##_offset != 0) \ + gdb_printf (gdb_stdlog, ", %s_offset=%d", #region, \ + layout.region##_offset) + POFFS(avx); + POFFS(bndregs); + POFFS(bndcfg); + POFFS(k); + POFFS(zmm_h); + POFFS(zmm); + POFFS(pkru); +#undef POFFS + gdb_puts (" }", gdb_stdlog); +} #endif /* TARGET_DEBUG_H */ diff --git a/gdb/target-delegates.c b/gdb/target-delegates.c index 57b66ce87b1..1d1f8c60f4e 100644 --- a/gdb/target-delegates.c +++ b/gdb/target-delegates.c @@ -196,6 +196,7 @@ struct dummy_target : public target_ops bool supports_memory_tagging () override; bool fetch_memtags (CORE_ADDR arg0, size_t arg1, gdb::byte_vector &arg2, int arg3) override; bool store_memtags (CORE_ADDR arg0, size_t arg1, const gdb::byte_vector &arg2, int arg3) override; + x86_xsave_layout fetch_x86_xsave_layout () override; }; struct debug_target : public target_ops @@ -370,6 +371,7 @@ struct debug_target : public target_ops bool supports_memory_tagging () override; bool fetch_memtags (CORE_ADDR arg0, size_t arg1, gdb::byte_vector &arg2, int arg3) override; bool store_memtags (CORE_ADDR arg0, size_t arg1, const gdb::byte_vector &arg2, int arg3) override; + x86_xsave_layout fetch_x86_xsave_layout () override; }; void @@ -4536,3 +4538,28 @@ debug_target::store_memtags (CORE_ADDR arg0, size_t arg1, const gdb::byte_vector return result; } +x86_xsave_layout +target_ops::fetch_x86_xsave_layout () +{ + return this->beneath ()->fetch_x86_xsave_layout (); +} + +x86_xsave_layout +dummy_target::fetch_x86_xsave_layout () +{ + return x86_xsave_layout (); +} + +x86_xsave_layout +debug_target::fetch_x86_xsave_layout () +{ + x86_xsave_layout result; + gdb_printf (gdb_stdlog, "-> %s->fetch_x86_xsave_layout (...)\n", this->beneath ()->shortname ()); + result = this->beneath ()->fetch_x86_xsave_layout (); + gdb_printf (gdb_stdlog, "<- %s->fetch_x86_xsave_layout (", this->beneath ()->shortname ()); + gdb_puts (") = ", gdb_stdlog); + target_debug_print_x86_xsave_layout (result); + gdb_puts ("\n", gdb_stdlog); + return result; +} + diff --git a/gdb/target.c b/gdb/target.c index 16f43d072cd..f650e5ccb51 100644 --- a/gdb/target.c +++ b/gdb/target.c @@ -832,6 +832,12 @@ target_store_memtags (CORE_ADDR address, size_t len, return current_inferior ()->top_target ()->store_memtags (address, len, tags, type); } +x86_xsave_layout +target_fetch_x86_xsave_layout () +{ + return current_inferior ()->top_target ()->fetch_x86_xsave_layout (); +} + void target_log_command (const char *p) { diff --git a/gdb/target.h b/gdb/target.h index 6ae400e2cc2..9325b111c5b 100644 --- a/gdb/target.h +++ b/gdb/target.h @@ -82,6 +82,7 @@ struct inferior; #include "disasm-flags.h" #include "tracepoint.h" #include "gdbsupport/fileio.h" +#include "gdbsupport/x86-xstate.h" #include "gdbsupport/break-common.h" /* For enum target_hw_bp_type. */ @@ -1321,6 +1322,10 @@ struct target_ops virtual bool store_memtags (CORE_ADDR address, size_t len, const gdb::byte_vector &tags, int type) TARGET_DEFAULT_NORETURN (tcomplain ()); + + /* Return the x86 XSAVE extended state area layout. */ + virtual x86_xsave_layout fetch_x86_xsave_layout () + TARGET_DEFAULT_RETURN (x86_xsave_layout ()); }; /* Deleter for std::unique_ptr. See comments in @@ -2301,6 +2306,8 @@ extern bool target_fetch_memtags (CORE_ADDR address, size_t len, extern bool target_store_memtags (CORE_ADDR address, size_t len, const gdb::byte_vector &tags, int type); +extern x86_xsave_layout target_fetch_x86_xsave_layout (); + /* Command logging facility. */ extern void target_log_command (const char *p); From patchwork Fri Jul 14 15:51:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72702 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 40BA13857014 for ; Fri, 14 Jul 2023 15:56:45 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id 320EB3858C53 for ; Fri, 14 Jul 2023 15:55:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 320EB3858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id C730D1A84C5E for ; Fri, 14 Jul 2023 11:55:50 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 03/15] core: Support fetching x86 XSAVE layout from architectures. Date: Fri, 14 Jul 2023 08:51:39 -0700 Message-Id: <20230714155151.21723-4-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:51 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Add gdbarch_core_read_x86_xsave_layout to fetch the x86 XSAVE layout structure from a core file. Current OS's do not export the offsets of XSAVE state components in core dumps, so provide an i387_set_xsave_layout helper function to set offsets based on known combinations of XCR0 masks and total state sizes. Eventually when core dumps do contain this information this function should only be used as a fall back for older core dumps. --- gdb/corelow.c | 21 +++++++++++++++ gdb/gdbarch-gen.h | 9 +++++++ gdb/gdbarch.c | 32 +++++++++++++++++++++++ gdb/gdbarch.h | 1 + gdb/gdbarch_components.py | 11 ++++++++ gdb/i387-tdep.c | 55 +++++++++++++++++++++++++++++++++++++++ gdb/i387-tdep.h | 8 ++++++ 7 files changed, 137 insertions(+) diff --git a/gdb/corelow.c b/gdb/corelow.c index 46bb1077b6d..3d666a6d311 100644 --- a/gdb/corelow.c +++ b/gdb/corelow.c @@ -47,6 +47,7 @@ #include "build-id.h" #include "gdbsupport/pathstuff.h" #include "gdbsupport/scoped_fd.h" +#include "gdbsupport/x86-xstate.h" #include "debuginfod-support.h" #include #include @@ -109,6 +110,8 @@ class core_target final : public process_stratum_target bool fetch_memtags (CORE_ADDR address, size_t len, gdb::byte_vector &tags, int type) override; + x86_xsave_layout fetch_x86_xsave_layout () override; + /* A few helpers. */ /* Getter, see variable definition. */ @@ -1387,6 +1390,24 @@ core_target::fetch_memtags (CORE_ADDR address, size_t len, return false; } +/* Implementation of the "fetch_x86_xsave_layout" target_ops method. */ + +x86_xsave_layout +core_target::fetch_x86_xsave_layout () +{ + if (m_core_gdbarch != nullptr && + gdbarch_core_read_x86_xsave_layout_p (m_core_gdbarch)) + { + x86_xsave_layout layout; + if (!gdbarch_core_read_x86_xsave_layout (m_core_gdbarch, layout)) + return {}; + + return layout; + } + + return {}; +} + /* Get a pointer to the current core target. If not connected to a core target, return NULL. */ diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h index 101b1b73636..d62eefa1c5b 100644 --- a/gdb/gdbarch-gen.h +++ b/gdb/gdbarch-gen.h @@ -1013,6 +1013,15 @@ typedef LONGEST (gdbarch_core_xfer_siginfo_ftype) (struct gdbarch *gdbarch, gdb_ extern LONGEST gdbarch_core_xfer_siginfo (struct gdbarch *gdbarch, gdb_byte *readbuf, ULONGEST offset, ULONGEST len); extern void set_gdbarch_core_xfer_siginfo (struct gdbarch *gdbarch, gdbarch_core_xfer_siginfo_ftype *core_xfer_siginfo); +/* Read x86 XSAVE layout information from core file into XSAVE_LAYOUT. + Returns true if the layout was read successfully. */ + +extern bool gdbarch_core_read_x86_xsave_layout_p (struct gdbarch *gdbarch); + +typedef bool (gdbarch_core_read_x86_xsave_layout_ftype) (struct gdbarch *gdbarch, x86_xsave_layout &xsave_layout); +extern bool gdbarch_core_read_x86_xsave_layout (struct gdbarch *gdbarch, x86_xsave_layout &xsave_layout); +extern void set_gdbarch_core_read_x86_xsave_layout (struct gdbarch *gdbarch, gdbarch_core_read_x86_xsave_layout_ftype *core_read_x86_xsave_layout); + /* BFD target to use when generating a core file. */ extern bool gdbarch_gcore_bfd_target_p (struct gdbarch *gdbarch); diff --git a/gdb/gdbarch.c b/gdb/gdbarch.c index 30199a0b03d..1fc254d3d6e 100644 --- a/gdb/gdbarch.c +++ b/gdb/gdbarch.c @@ -182,6 +182,7 @@ struct gdbarch gdbarch_core_pid_to_str_ftype *core_pid_to_str = nullptr; gdbarch_core_thread_name_ftype *core_thread_name = nullptr; gdbarch_core_xfer_siginfo_ftype *core_xfer_siginfo = nullptr; + gdbarch_core_read_x86_xsave_layout_ftype *core_read_x86_xsave_layout = nullptr; const char * gcore_bfd_target = 0; int vtable_function_descriptors = 0; int vbit_in_delta = 0; @@ -443,6 +444,7 @@ verify_gdbarch (struct gdbarch *gdbarch) /* Skip verify of core_pid_to_str, has predicate. */ /* Skip verify of core_thread_name, has predicate. */ /* Skip verify of core_xfer_siginfo, has predicate. */ + /* Skip verify of core_read_x86_xsave_layout, has predicate. */ /* Skip verify of gcore_bfd_target, has predicate. */ /* Skip verify of vtable_function_descriptors, invalid_p == 0 */ /* Skip verify of vbit_in_delta, invalid_p == 0 */ @@ -1071,6 +1073,12 @@ gdbarch_dump (struct gdbarch *gdbarch, struct ui_file *file) gdb_printf (file, "gdbarch_dump: core_xfer_siginfo = <%s>\n", host_address_to_string (gdbarch->core_xfer_siginfo)); + gdb_printf (file, + "gdbarch_dump: gdbarch_core_read_x86_xsave_layout_p() = %d\n", + gdbarch_core_read_x86_xsave_layout_p (gdbarch)); + gdb_printf (file, + "gdbarch_dump: core_read_x86_xsave_layout = <%s>\n", + host_address_to_string (gdbarch->core_read_x86_xsave_layout)); gdb_printf (file, "gdbarch_dump: gdbarch_gcore_bfd_target_p() = %d\n", gdbarch_gcore_bfd_target_p (gdbarch)); @@ -3958,6 +3966,30 @@ set_gdbarch_core_xfer_siginfo (struct gdbarch *gdbarch, gdbarch->core_xfer_siginfo = core_xfer_siginfo; } +bool +gdbarch_core_read_x86_xsave_layout_p (struct gdbarch *gdbarch) +{ + gdb_assert (gdbarch != NULL); + return gdbarch->core_read_x86_xsave_layout != NULL; +} + +bool +gdbarch_core_read_x86_xsave_layout (struct gdbarch *gdbarch, x86_xsave_layout &xsave_layout) +{ + gdb_assert (gdbarch != NULL); + gdb_assert (gdbarch->core_read_x86_xsave_layout != NULL); + if (gdbarch_debug >= 2) + gdb_printf (gdb_stdlog, "gdbarch_core_read_x86_xsave_layout called\n"); + return gdbarch->core_read_x86_xsave_layout (gdbarch, xsave_layout); +} + +void +set_gdbarch_core_read_x86_xsave_layout (struct gdbarch *gdbarch, + gdbarch_core_read_x86_xsave_layout_ftype core_read_x86_xsave_layout) +{ + gdbarch->core_read_x86_xsave_layout = core_read_x86_xsave_layout; +} + bool gdbarch_gcore_bfd_target_p (struct gdbarch *gdbarch) { diff --git a/gdb/gdbarch.h b/gdb/gdbarch.h index 3d97919bc9b..a9d6a4b175c 100644 --- a/gdb/gdbarch.h +++ b/gdb/gdbarch.h @@ -57,6 +57,7 @@ struct syscalls_info; struct thread_info; struct ui_out; struct inferior; +struct x86_xsave_layout; #include "regcache.h" diff --git a/gdb/gdbarch_components.py b/gdb/gdbarch_components.py index 23e5789327c..846467b8d83 100644 --- a/gdb/gdbarch_components.py +++ b/gdb/gdbarch_components.py @@ -1709,6 +1709,17 @@ of bytes read (zero indicates EOF, a negative value indicates failure). predicate=True, ) +Method( + comment=""" +Read x86 XSAVE layout information from core file into XSAVE_LAYOUT. +Returns true if the layout was read successfully. +""", + type="bool", + name="core_read_x86_xsave_layout", + params=[("x86_xsave_layout &", "xsave_layout")], + predicate=True, +) + Value( comment=""" BFD target to use when generating a core file. diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c index df0a6058adc..f25579c1a9a 100644 --- a/gdb/i387-tdep.c +++ b/gdb/i387-tdep.c @@ -898,6 +898,61 @@ static int xsave_pkeys_offset[] = (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) +/* See i387-tdep.h. */ + +bool +i387_set_xsave_layout (uint64_t xcr0, size_t xsave_size, + x86_xsave_layout &layout) +{ + if (HAS_PKRU (xcr0) && xsave_size == 2696) + { + /* Intel CPUs supporting PKRU. */ + layout.avx_offset = 576; + layout.bndregs_offset = 960; + layout.bndcfg_offset = 1024; + layout.k_offset = 1088; + layout.zmm_h_offset = 1152; + layout.zmm_offset = 1664; + layout.pkru_offset = 2688; + } + else if (HAS_PKRU (xcr0) && xsave_size == 2440) + { + /* AMD CPUs supporting PKRU. */ + layout.avx_offset = 576; + layout.k_offset = 832; + layout.zmm_h_offset = 896; + layout.zmm_offset = 1408; + layout.pkru_offset = 2432; + } + else if (HAS_AVX512 (xcr0) && xsave_size == 2688) + { + /* Intel CPUs supporting AVX512. */ + layout.avx_offset = 576; + layout.bndregs_offset = 960; + layout.bndcfg_offset = 1024; + layout.k_offset = 1088; + layout.zmm_h_offset = 1152; + layout.zmm_offset = 1664; + } + else if (HAS_MPX (xcr0) && xsave_size == 1088) + { + /* Intel CPUs supporting MPX. */ + layout.avx_offset = 576; + layout.bndregs_offset = 960; + layout.bndcfg_offset = 1024; + } + else if (HAS_AVX (xcr0) && xsave_size == 832) + { + /* Intel and AMD CPUs supporting AVX. */ + layout.avx_offset = 576; + } + else + return false; + + layout.sizeof_xsave = xsave_size; + return true; +} + /* Extract from XSAVE a bitset of the features that are available on the target, but which have not yet been enabled. */ diff --git a/gdb/i387-tdep.h b/gdb/i387-tdep.h index 2e890e71a2b..b7674155255 100644 --- a/gdb/i387-tdep.h +++ b/gdb/i387-tdep.h @@ -25,6 +25,7 @@ class frame_info_ptr; struct regcache; struct type; struct ui_file; +struct x86_xsave_layout; /* Number of i387 floating point registers. */ #define I387_NUM_REGS 16 @@ -138,6 +139,13 @@ extern void i387_collect_fsave (const struct regcache *regcache, int regnum, extern void i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave); +/* Select an XSAVE layout based on the XCR0 bitmask and total XSAVE + extended state size. Returns true if the bitmask and size matched + a known layout. */ + +extern bool i387_set_xsave_layout (uint64_t xcr0, size_t xsave_size, + x86_xsave_layout &layout); + /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ extern void i387_supply_xsave (struct regcache *regcache, int regnum, From patchwork Fri Jul 14 15:51:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72698 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A512A3857400 for ; Fri, 14 Jul 2023 15:56:08 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id 8DAA03858CD1 for ; Fri, 14 Jul 2023 15:55:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8DAA03858CD1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 6846B1A84E2E for ; Fri, 14 Jul 2023 11:55:51 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 04/15] nat/x86-cpuid.h: Add x86_cpuid_count wrapper around __get_cpuid_count. Date: Fri, 14 Jul 2023 08:51:40 -0700 Message-Id: <20230714155151.21723-5-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:51 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" --- gdb/nat/x86-cpuid.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/gdb/nat/x86-cpuid.h b/gdb/nat/x86-cpuid.h index 0955afba577..517113d45e8 100644 --- a/gdb/nat/x86-cpuid.h +++ b/gdb/nat/x86-cpuid.h @@ -48,6 +48,30 @@ x86_cpuid (unsigned int __level, return __get_cpuid (__level, __eax, __ebx, __ecx, __edx); } +/* Return cpuid data for requested cpuid level and sub-level, as found + in returned eax, ebx, ecx and edx registers. The function checks + if cpuid is supported and returns 1 for valid cpuid information or + 0 for unsupported cpuid level. Pointers may be non-null. */ + +static __inline int +x86_cpuid_count (unsigned int __level, unsigned int __sublevel, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + unsigned int __scratch; + + if (__eax == nullptr) + __eax = &__scratch; + if (__ebx == nullptr) + __ebx = &__scratch; + if (__ecx == nullptr) + __ecx = &__scratch; + if (__edx == nullptr) + __edx = &__scratch; + + return __get_cpuid_count (__level, __sublevel, __eax, __ebx, __ecx, __edx); +} + #else static __inline int @@ -58,6 +82,14 @@ x86_cpuid (unsigned int __level, return 0; } +static __inline int +x86_cpuid_count (unsigned int __level, unsigned int __sublevel, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + return 0; +} + #endif /* i386 && x86_64 */ #endif /* NAT_X86_CPUID_H */ From patchwork Fri Jul 14 15:51:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72700 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C64E3854E83 for ; Fri, 14 Jul 2023 15:56:34 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id ABDC23858C52 for ; Fri, 14 Jul 2023 15:55:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ABDC23858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id F09E71A84E32 for ; Fri, 14 Jul 2023 11:55:51 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 05/15] x86 nat: Add helper functions to save the XSAVE layout for the host. Date: Fri, 14 Jul 2023 08:51:41 -0700 Message-Id: <20230714155151.21723-6-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:52 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" x86_xsave_length returns the total length of the XSAVE state area standard format as queried from CPUID. x86_fetch_xsave_layout uses CPUID to query the offsets of XSAVE extended regions from the running host. The total length of the XSAVE state area can either be supplied the caller if known (e.g. from FreeBSD's PT_GETXSTATEINFO) or it can be queried from the running host using x86_xsave_length. --- gdb/nat/x86-xstate.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ gdb/nat/x86-xstate.h | 35 +++++++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 gdb/nat/x86-xstate.c create mode 100644 gdb/nat/x86-xstate.h diff --git a/gdb/nat/x86-xstate.c b/gdb/nat/x86-xstate.c new file mode 100644 index 00000000000..9fdc572356a --- /dev/null +++ b/gdb/nat/x86-xstate.c @@ -0,0 +1,67 @@ +/* x86 XSAVE extended state functions. + + Copyright (C) 2022-2023 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "gdbsupport/common-defs.h" +#include "gdbsupport/x86-xstate.h" +#include "nat/x86-cpuid.h" +#include "nat/x86-xstate.h" + +/* Fetch the offset of a specific XSAVE extended region. */ + +static int +xsave_feature_offset (uint64_t xcr0, int feature) +{ + uint32_t ebx; + + if ((xcr0 & (1ULL << feature)) == 0) + return 0; + + if (!x86_cpuid_count (0xd, feature, nullptr, &ebx, nullptr, nullptr)) + return 0; + return ebx; +} + +/* See x86-xstate.h. */ + +int +x86_xsave_length () +{ + uint32_t ecx; + + if (!x86_cpuid_count (0xd, 0, nullptr, nullptr, &ecx, nullptr)) + return 0; + return ecx; +} + +/* See x86-xstate.h. */ + +x86_xsave_layout +x86_fetch_xsave_layout (uint64_t xcr0, int len) +{ + x86_xsave_layout layout; + layout.sizeof_xsave = len; + layout.avx_offset = xsave_feature_offset (xcr0, X86_XSTATE_AVX_ID); + layout.bndregs_offset = xsave_feature_offset (xcr0, X86_XSTATE_BNDREGS_ID); + layout.bndcfg_offset = xsave_feature_offset (xcr0, X86_XSTATE_BNDCFG_ID); + layout.k_offset = xsave_feature_offset (xcr0, X86_XSTATE_K_ID); + layout.zmm_h_offset = xsave_feature_offset (xcr0, X86_XSTATE_ZMM_H_ID); + layout.zmm_offset = xsave_feature_offset (xcr0, X86_XSTATE_ZMM_ID); + layout.pkru_offset = xsave_feature_offset (xcr0, X86_XSTATE_PKRU_ID); + return layout; +} diff --git a/gdb/nat/x86-xstate.h b/gdb/nat/x86-xstate.h new file mode 100644 index 00000000000..30f3a35087e --- /dev/null +++ b/gdb/nat/x86-xstate.h @@ -0,0 +1,35 @@ +/* x86 XSAVE extended state functions. + + Copyright (C) 2022-2023 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef NAT_X86_XSTATE_H +#define NAT_X86_XSTATE_H + +#include "gdbsupport/x86-xstate.h" + +/* Return the size of the XSAVE extended state fetched via CPUID. */ + +int x86_xsave_length (); + +/* Return the layout (size and offsets) of the XSAVE extended regions + for the running host. Offsets of each of the enabled regions in + XCR0 are fetched via CPUID. */ + +x86_xsave_layout x86_fetch_xsave_layout (uint64_t xcr0, int len); + +#endif /* NAT_X86_XSTATE_H */ From patchwork Fri Jul 14 15:51:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72707 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ED3D03857011 for ; Fri, 14 Jul 2023 15:57:21 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id AC0D33858C2B for ; Fri, 14 Jul 2023 15:55:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AC0D33858C2B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 861EC1A84E34 for ; Fri, 14 Jul 2023 11:55:52 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 06/15] gdb: Update x86 FreeBSD architectures to support XSAVE layouts. Date: Fri, 14 Jul 2023 08:51:42 -0700 Message-Id: <20230714155151.21723-7-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:52 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Refactor i386fbsd_core_read_xcr0 to fetch and return a corresponding x86_xsave_layout as well as xcr0 using the size of an existing NT_X86_XSTATE core dump to determine the offsets via i387_set_xsave_layout. Use this to add an implementation of gdbarch_core_xfer_x86_xsave_layout. Use tdep->xsave_layout.sizeof_xsave as the size of the XSTATE register set and only fetch/store the register set if this size is non-zero. --- gdb/amd64-fbsd-tdep.c | 12 ++++++-- gdb/i386-fbsd-tdep.c | 72 ++++++++++++++++++++++++------------------- gdb/i386-fbsd-tdep.h | 14 +++++++-- 3 files changed, 62 insertions(+), 36 deletions(-) diff --git a/gdb/amd64-fbsd-tdep.c b/gdb/amd64-fbsd-tdep.c index 0d5ce004fb1..5dc519d7d6e 100644 --- a/gdb/amd64-fbsd-tdep.c +++ b/gdb/amd64-fbsd-tdep.c @@ -224,7 +224,9 @@ amd64fbsd_core_read_description (struct gdbarch *gdbarch, struct target_ops *target, bfd *abfd) { - return amd64_target_description (i386fbsd_core_read_xcr0 (abfd), true); + x86_xsave_layout layout; + return amd64_target_description (i386_fbsd_core_read_xsave_info (abfd, layout), + true); } /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */ @@ -271,8 +273,10 @@ amd64fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg-x86-segbases", AMD64_FBSD_SIZEOF_SEGBASES_REGSET, AMD64_FBSD_SIZEOF_SEGBASES_REGSET, &amd64_fbsd_segbases_regset, "segment bases", cb_data); - cb (".reg-xstate", X86_XSTATE_SIZE (tdep->xcr0), X86_XSTATE_SIZE (tdep->xcr0), - &amd64fbsd_xstateregset, "XSAVE extended state", cb_data); + if (tdep->xsave_layout.sizeof_xsave != 0) + cb (".reg-xstate", tdep->xsave_layout.sizeof_xsave, + tdep->xsave_layout.sizeof_xsave, &amd64fbsd_xstateregset, + "XSAVE extended state", cb_data); } /* Implement the get_thread_local_address gdbarch method. */ @@ -313,6 +317,8 @@ amd64fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tramp_frame_prepend_unwinder (gdbarch, &amd64_fbsd_sigframe); tdep->xsave_xcr0_offset = I386_FBSD_XSAVE_XCR0_OFFSET; + set_gdbarch_core_read_x86_xsave_layout + (gdbarch, i386_fbsd_core_read_x86_xsave_layout); /* Iterate over core file register note sections. */ set_gdbarch_iterate_over_regset_sections diff --git a/gdb/i386-fbsd-tdep.c b/gdb/i386-fbsd-tdep.c index fb9030413ab..df842f16bfc 100644 --- a/gdb/i386-fbsd-tdep.c +++ b/gdb/i386-fbsd-tdep.c @@ -18,13 +18,13 @@ along with this program. If not, see . */ #include "defs.h" +#include "gdbcore.h" #include "osabi.h" #include "regcache.h" #include "regset.h" #include "trad-frame.h" #include "tramp-frame.h" #include "i386-fbsd-tdep.h" -#include "gdbsupport/x86-xstate.h" #include "i386-tdep.h" #include "i387-tdep.h" @@ -241,43 +241,49 @@ static const struct tramp_frame i386_fbsd64_sigframe = i386_fbsd_sigframe_init }; -/* Get XSAVE extended state xcr0 from core dump. */ +/* See i386-fbsd-tdep.h. */ uint64_t -i386fbsd_core_read_xcr0 (bfd *abfd) +i386_fbsd_core_read_xsave_info (bfd *abfd, x86_xsave_layout &layout) { asection *xstate = bfd_get_section_by_name (abfd, ".reg-xstate"); - uint64_t xcr0; + if (xstate == nullptr) + return X86_XSTATE_SSE_MASK; - if (xstate) + /* Check extended state size. */ + size_t size = bfd_section_size (xstate); + if (size < X86_XSTATE_AVX_SIZE) + return X86_XSTATE_SSE_MASK; + + char contents[8]; + if (! bfd_get_section_contents (abfd, xstate, contents, + I386_FBSD_XSAVE_XCR0_OFFSET, 8)) { - size_t size = bfd_section_size (xstate); - - /* Check extended state size. */ - if (size < X86_XSTATE_AVX_SIZE) - xcr0 = X86_XSTATE_SSE_MASK; - else - { - char contents[8]; - - if (! bfd_get_section_contents (abfd, xstate, contents, - I386_FBSD_XSAVE_XCR0_OFFSET, - 8)) - { - warning (_("Couldn't read `xcr0' bytes from " - "`.reg-xstate' section in core file.")); - return X86_XSTATE_SSE_MASK; - } - - xcr0 = bfd_get_64 (abfd, contents); - } + warning (_("Couldn't read `xcr0' bytes from " + "`.reg-xstate' section in core file.")); + return X86_XSTATE_SSE_MASK; } - else - xcr0 = X86_XSTATE_SSE_MASK; + + uint64_t xcr0 = bfd_get_64 (abfd, contents); + + if (!i387_set_xsave_layout (xcr0, size, layout)) + return X86_XSTATE_SSE_MASK; return xcr0; } +/* Implement the core_read_x86_xsave_layout gdbarch method. */ + +bool +i386_fbsd_core_read_x86_xsave_layout (struct gdbarch *gdbarch, + x86_xsave_layout &layout) +{ + if (i386_fbsd_core_read_xsave_info (core_bfd, layout) == X86_XSTATE_SSE_MASK) + return false; + + return true; +} + /* Implement the core_read_description gdbarch method. */ static const struct target_desc * @@ -285,7 +291,9 @@ i386fbsd_core_read_description (struct gdbarch *gdbarch, struct target_ops *target, bfd *abfd) { - return i386_target_description (i386fbsd_core_read_xcr0 (abfd), true); + x86_xsave_layout layout; + return i386_target_description (i386_fbsd_core_read_xsave_info (abfd, layout), + true); } /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ @@ -335,9 +343,9 @@ i386fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, I386_FBSD_SIZEOF_SEGBASES_REGSET, &i386_fbsd_segbases_regset, "segment bases", cb_data); - if (tdep->xcr0 & X86_XSTATE_AVX) - cb (".reg-xstate", X86_XSTATE_SIZE (tdep->xcr0), - X86_XSTATE_SIZE (tdep->xcr0), &i386fbsd_xstateregset, + if (tdep->xsave_layout.sizeof_xsave != 0) + cb (".reg-xstate", tdep->xsave_layout.sizeof_xsave, + tdep->xsave_layout.sizeof_xsave, &i386fbsd_xstateregset, "XSAVE extended state", cb_data); } @@ -386,6 +394,8 @@ i386fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) i386_elf_init_abi (info, gdbarch); tdep->xsave_xcr0_offset = I386_FBSD_XSAVE_XCR0_OFFSET; + set_gdbarch_core_read_x86_xsave_layout + (gdbarch, i386_fbsd_core_read_x86_xsave_layout); /* Iterate over core file register note sections. */ set_gdbarch_iterate_over_regset_sections diff --git a/gdb/i386-fbsd-tdep.h b/gdb/i386-fbsd-tdep.h index cb991af9e49..cc2af4a0600 100644 --- a/gdb/i386-fbsd-tdep.h +++ b/gdb/i386-fbsd-tdep.h @@ -20,10 +20,20 @@ #ifndef I386_FBSD_TDEP_H #define I386_FBSD_TDEP_H +#include "gdbsupport/x86-xstate.h" #include "regset.h" -/* Get XSAVE extended state xcr0 from core dump. */ -extern uint64_t i386fbsd_core_read_xcr0 (bfd *abfd); +/* Read the XSAVE extended state xcr0 value from the ABFD core file. + If it appears to be valid, return it and fill LAYOUT with values + inferred from that value. + + Otherwise, return X86_XSTATE_SSE_MASK as a fallback and leave + LAYOUT untouched. */ +uint64_t i386_fbsd_core_read_xsave_info (bfd *abfd, x86_xsave_layout &layout); + +/* Implement the core_read_x86_xsave_layout gdbarch method. */ +bool i386_fbsd_core_read_x86_xsave_layout (struct gdbarch *gdbarch, + x86_xsave_layout &layout); /* The format of the XSAVE extended area is determined by hardware. Cores store the XSAVE extended area in a NT_X86_XSTATE note that From patchwork Fri Jul 14 15:51:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72701 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 21FE6385AF84 for ; Fri, 14 Jul 2023 15:56:42 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id B094B3858C3A for ; Fri, 14 Jul 2023 15:55:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B094B3858C3A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 2558E1A84E36 for ; Fri, 14 Jul 2023 11:55:53 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 07/15] gdb: Support XSAVE layouts for the current host in the FreeBSD x86 targets. Date: Fri, 14 Jul 2023 08:51:43 -0700 Message-Id: <20230714155151.21723-8-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:53 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Use the CPUID instruction to fetch the offsets of supported state components. --- gdb/amd64-fbsd-nat.c | 40 ++++++++++------------------------------ gdb/configure.nat | 5 +++-- gdb/i386-fbsd-nat.c | 39 +++++++++------------------------------ gdb/x86-fbsd-nat.c | 21 +++++++++++++++++++++ gdb/x86-fbsd-nat.h | 19 +++++++++++++++++++ 5 files changed, 62 insertions(+), 62 deletions(-) diff --git a/gdb/amd64-fbsd-nat.c b/gdb/amd64-fbsd-nat.c index 43e83ff2485..5821d94e27e 100644 --- a/gdb/amd64-fbsd-nat.c +++ b/gdb/amd64-fbsd-nat.c @@ -31,9 +31,9 @@ #include "amd64-tdep.h" #include "amd64-fbsd-tdep.h" +#include "i387-tdep.h" #include "amd64-nat.h" #include "x86-nat.h" -#include "gdbsupport/x86-xstate.h" #include "x86-fbsd-nat.h" class amd64_fbsd_nat_target final : public x86_fbsd_nat_target @@ -47,10 +47,6 @@ class amd64_fbsd_nat_target final : public x86_fbsd_nat_target static amd64_fbsd_nat_target the_amd64_fbsd_nat_target; -#ifdef PT_GETXSTATE_INFO -static size_t xsave_len; -#endif - /* This is a layout of the amd64 'struct reg' but with i386 registers. */ @@ -146,9 +142,9 @@ amd64_fbsd_nat_target::fetch_registers (struct regcache *regcache, int regnum) fetching the FPU/XSAVE state unnecessarily. */ #ifdef PT_GETXSTATE_INFO - if (xsave_len != 0) + if (m_xsave_info.xsave_len != 0) { - void *xstateregs = alloca (xsave_len); + void *xstateregs = alloca (m_xsave_info.xsave_len); if (ptrace (PT_GETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, 0) == -1) perror_with_name (_("Couldn't get extended state status")); @@ -223,9 +219,9 @@ amd64_fbsd_nat_target::store_registers (struct regcache *regcache, int regnum) fetching the FPU/XSAVE state unnecessarily. */ #ifdef PT_GETXSTATE_INFO - if (xsave_len != 0) + if (m_xsave_info.xsave_len != 0) { - void *xstateregs = alloca (xsave_len); + void *xstateregs = alloca (m_xsave_info.xsave_len); if (ptrace (PT_GETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, 0) == -1) perror_with_name (_("Couldn't get extended state status")); @@ -233,7 +229,7 @@ amd64_fbsd_nat_target::store_registers (struct regcache *regcache, int regnum) amd64_collect_xsave (regcache, regnum, xstateregs, 0); if (ptrace (PT_SETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, - xsave_len) == -1) + m_xsave_info.xsave_len) == -1) perror_with_name (_("Couldn't write extended state status")); return; } @@ -303,10 +299,6 @@ amd64fbsd_supply_pcb (struct regcache *regcache, struct pcb *pcb) const struct target_desc * amd64_fbsd_nat_target::read_description () { -#ifdef PT_GETXSTATE_INFO - static int xsave_probed; - static uint64_t xcr0; -#endif struct reg regs; int is64; @@ -318,25 +310,13 @@ amd64_fbsd_nat_target::read_description () perror_with_name (_("Couldn't get registers")); is64 = (regs.r_cs == GSEL (GUCODE_SEL, SEL_UPL)); #ifdef PT_GETXSTATE_INFO - if (!xsave_probed) - { - struct ptrace_xstate_info info; - - if (ptrace (PT_GETXSTATE_INFO, inferior_ptid.pid (), - (PTRACE_TYPE_ARG3) &info, sizeof (info)) == 0) - { - xsave_len = info.xsave_len; - xcr0 = info.xsave_mask; - } - xsave_probed = 1; - } - - if (xsave_len != 0) + probe_xsave_layout (inferior_ptid.pid ()); + if (m_xsave_info.xsave_len != 0) { if (is64) - return amd64_target_description (xcr0, true); + return amd64_target_description (m_xsave_info.xsave_mask, true); else - return i386_target_description (xcr0, true); + return i386_target_description (m_xsave_info.xsave_mask, true); } #endif if (is64) diff --git a/gdb/configure.nat b/gdb/configure.nat index aabcdeff989..b371ad89afe 100644 --- a/gdb/configure.nat +++ b/gdb/configure.nat @@ -166,7 +166,8 @@ case ${gdb_host} in i386) # Host: FreeBSD/i386 NATDEPFILES="${NATDEPFILES} x86-nat.o nat/x86-dregs.o \ - x86-bsd-nat.o x86-fbsd-nat.o i386-fbsd-nat.o bsd-kvm.o" + nat/x86-xstate.o x86-bsd-nat.o x86-fbsd-nat.o i386-fbsd-nat.o \ + bsd-kvm.o" ;; mips) # Host: FreeBSD/mips @@ -195,7 +196,7 @@ case ${gdb_host} in # Host: FreeBSD/amd64 NATDEPFILES="${NATDEPFILES} amd64-nat.o \ amd64-fbsd-nat.o bsd-kvm.o x86-nat.o nat/x86-dregs.o \ - x86-bsd-nat.o x86-fbsd-nat.o" + nat/x86-xstate.o x86-bsd-nat.o x86-fbsd-nat.o" ;; esac ;; diff --git a/gdb/i386-fbsd-nat.c b/gdb/i386-fbsd-nat.c index a2255c3c26b..e2c0e611717 100644 --- a/gdb/i386-fbsd-nat.c +++ b/gdb/i386-fbsd-nat.c @@ -31,7 +31,6 @@ #include "i386-fbsd-tdep.h" #include "i387-tdep.h" #include "x86-nat.h" -#include "gdbsupport/x86-xstate.h" #include "x86-fbsd-nat.h" class i386_fbsd_nat_target final : public x86_fbsd_nat_target @@ -47,10 +46,6 @@ class i386_fbsd_nat_target final : public x86_fbsd_nat_target static i386_fbsd_nat_target the_i386_fbsd_nat_target; -#ifdef PT_GETXSTATE_INFO -static size_t xsave_len; -#endif - static int have_ptrace_xmmregs; /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this @@ -102,9 +97,9 @@ i386_fbsd_nat_target::fetch_registers (struct regcache *regcache, int regnum) fetching the FPU/XSAVE state unnecessarily. */ #ifdef PT_GETXSTATE_INFO - if (xsave_len != 0) + if (m_xsave_info.xsave_len != 0) { - void *xstateregs = alloca (xsave_len); + void *xstateregs = alloca (m_xsave_info.xsave_len); if (ptrace (PT_GETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, 0) == -1) perror_with_name (_("Couldn't get extended state status")); @@ -181,17 +176,17 @@ i386_fbsd_nat_target::store_registers (struct regcache *regcache, int regnum) fetching the FPU/XSAVE state unnecessarily. */ #ifdef PT_GETXSTATE_INFO - if (xsave_len != 0) + if (m_xsave_info.xsave_len != 0) { - void *xstateregs = alloca (xsave_len); + void *xstateregs = alloca (m_xsave_info.xsave_len); if (ptrace (PT_GETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, 0) == -1) perror_with_name (_("Couldn't get extended state status")); i387_collect_xsave (regcache, regnum, xstateregs, 0); - if (ptrace (PT_SETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, xsave_len) - == -1) + if (ptrace (PT_SETXSTATE, pid, (PTRACE_TYPE_ARG3) xstateregs, + m_xsave_info.xsave_len) == -1) perror_with_name (_("Couldn't write extended state status")); return; } @@ -309,31 +304,15 @@ i386fbsd_supply_pcb (struct regcache *regcache, struct pcb *pcb) const struct target_desc * i386_fbsd_nat_target::read_description () { -#ifdef PT_GETXSTATE_INFO - static int xsave_probed; - static uint64_t xcr0; -#endif static int xmm_probed; if (inferior_ptid == null_ptid) return this->beneath ()->read_description (); #ifdef PT_GETXSTATE_INFO - if (!xsave_probed) - { - struct ptrace_xstate_info info; - - if (ptrace (PT_GETXSTATE_INFO, inferior_ptid.pid (), - (PTRACE_TYPE_ARG3) &info, sizeof (info)) == 0) - { - xsave_len = info.xsave_len; - xcr0 = info.xsave_mask; - } - xsave_probed = 1; - } - - if (xsave_len != 0) - return i386_target_description (xcr0, true); + probe_xsave_layout (inferior_ptid.pid ()); + if (m_xsave_info.xsave_len != 0) + return i386_target_description (m_xsave_info.xsave_mask, true); #endif if (!xmm_probed) diff --git a/gdb/x86-fbsd-nat.c b/gdb/x86-fbsd-nat.c index 5d1c9fc7665..240e228976c 100644 --- a/gdb/x86-fbsd-nat.c +++ b/gdb/x86-fbsd-nat.c @@ -19,6 +19,9 @@ #include "defs.h" #include "x86-fbsd-nat.h" +#ifdef PT_GETXSTATE_INFO +#include "nat/x86-xstate.h" +#endif /* Implement the virtual fbsd_nat_target::low_new_fork method. */ @@ -43,3 +46,21 @@ x86_fbsd_nat_target::low_new_fork (ptid_t parent, pid_t child) child_state = x86_debug_reg_state (child); *child_state = *parent_state; } + +#ifdef PT_GETXSTATE_INFO +void +x86_fbsd_nat_target::probe_xsave_layout (pid_t pid) +{ + if (m_xsave_probed) + return; + + m_xsave_probed = true; + + if (ptrace (PT_GETXSTATE_INFO, pid, (PTRACE_TYPE_ARG3) &m_xsave_info, + sizeof (m_xsave_info)) != 0) + return; + if (m_xsave_info.xsave_len != 0) + m_xsave_layout = x86_fetch_xsave_layout (m_xsave_info.xsave_mask, + m_xsave_info.xsave_len); +} +#endif diff --git a/gdb/x86-fbsd-nat.h b/gdb/x86-fbsd-nat.h index a424323f399..723bb6cf305 100644 --- a/gdb/x86-fbsd-nat.h +++ b/gdb/x86-fbsd-nat.h @@ -20,6 +20,11 @@ #ifndef X86_FBSD_NAT_H #define X86_FBSD_NAT_H +#include + +#ifdef PT_GETXSTATE_INFO +#include "gdbsupport/x86-xstate.h" +#endif #include "fbsd-nat.h" #include "x86-bsd-nat.h" @@ -32,6 +37,20 @@ class x86_fbsd_nat_target : public x86bsd_nat_target { return true; } void low_new_fork (ptid_t parent, pid_t child) override; + +#ifdef PT_GETXSTATE_INFO + x86_xsave_layout fetch_x86_xsave_layout () override + { return m_xsave_layout; } + +protected: + void probe_xsave_layout (pid_t pid); + + struct ptrace_xstate_info m_xsave_info; + x86_xsave_layout m_xsave_layout; + +private: + bool m_xsave_probed; +#endif }; #endif /* x86-bsd-nat.h */ From patchwork Fri Jul 14 15:51:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72710 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2D62C38714AD for ; Fri, 14 Jul 2023 15:57:51 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id BED413858407 for ; Fri, 14 Jul 2023 15:55:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BED413858407 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id B78751A84E37 for ; Fri, 14 Jul 2023 11:55:53 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 08/15] gdb: Update x86 Linux architectures to support XSAVE layouts. Date: Fri, 14 Jul 2023 08:51:44 -0700 Message-Id: <20230714155151.21723-9-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:54 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Refactor i386_linux_core_read_xcr0 to fetch and return a corresponding x86_xsave_layout as well as xcr0 using the size of an existing NT_X86_XSTATE core dump to determine the offsets via i387_set_xsave_layout. Use this to add an implementation of gdbarch_core_xfer_x86_xsave_layout. Use tdep->xsave_layout.sizeof_xsave as the size of the XSTATE register set. --- gdb/amd64-linux-tdep.c | 11 +++++-- gdb/i386-linux-tdep.c | 67 ++++++++++++++++++++++++------------------ gdb/i386-linux-tdep.h | 25 +++++++++------- 3 files changed, 61 insertions(+), 42 deletions(-) diff --git a/gdb/amd64-linux-tdep.c b/gdb/amd64-linux-tdep.c index cbbac1a0c64..d51f4d5af53 100644 --- a/gdb/amd64-linux-tdep.c +++ b/gdb/amd64-linux-tdep.c @@ -1616,7 +1616,8 @@ amd64_linux_core_read_description (struct gdbarch *gdbarch, bfd *abfd) { /* Linux/x86-64. */ - uint64_t xcr0 = i386_linux_core_read_xcr0 (abfd); + x86_xsave_layout layout; + uint64_t xcr0 = i386_linux_core_read_xsave_info (abfd, layout); return amd64_linux_read_description (xcr0 & X86_XSTATE_ALL_MASK, gdbarch_ptr_bit (gdbarch) == 32); @@ -1661,8 +1662,10 @@ amd64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg", 27 * 8, 27 * 8, &i386_gregset, NULL, cb_data); cb (".reg2", 512, 512, &amd64_fpregset, NULL, cb_data); - cb (".reg-xstate", X86_XSTATE_SIZE (tdep->xcr0), X86_XSTATE_SIZE (tdep->xcr0), - &amd64_linux_xstateregset, "XSAVE extended state", cb_data); + if (tdep->xsave_layout.sizeof_xsave != 0) + cb (".reg-xstate", tdep->xsave_layout.sizeof_xsave, + tdep->xsave_layout.sizeof_xsave, &amd64_linux_xstateregset, + "XSAVE extended state", cb_data); } /* The instruction sequences used in x86_64 machines for a @@ -1804,6 +1807,8 @@ amd64_linux_init_abi_common(struct gdbarch_info info, struct gdbarch *gdbarch, tdep->sc_num_regs = ARRAY_SIZE (amd64_linux_sc_reg_offset); tdep->xsave_xcr0_offset = I386_LINUX_XSAVE_XCR0_OFFSET; + set_gdbarch_core_read_x86_xsave_layout + (gdbarch, i386_linux_core_read_x86_xsave_layout); /* Add the %orig_rax register used for syscall restarting. */ set_gdbarch_write_pc (gdbarch, amd64_linux_write_pc); diff --git a/gdb/i386-linux-tdep.c b/gdb/i386-linux-tdep.c index 554c1455a5f..f27efbb1d59 100644 --- a/gdb/i386-linux-tdep.c +++ b/gdb/i386-linux-tdep.c @@ -638,45 +638,51 @@ static int i386_linux_sc_reg_offset[] = 0 * 4 /* %gs */ }; -/* Get XSAVE extended state xcr0 from core dump. */ +/* See i386-linux-tdep.h. */ uint64_t -i386_linux_core_read_xcr0 (bfd *abfd) +i386_linux_core_read_xsave_info (bfd *abfd, x86_xsave_layout &layout) { asection *xstate = bfd_get_section_by_name (abfd, ".reg-xstate"); - uint64_t xcr0; + if (xstate == nullptr) + return X86_XSTATE_SSE_MASK; - if (xstate) + /* Check extended state size. */ + size_t size = bfd_section_size (xstate); + if (size < X86_XSTATE_AVX_SIZE) + return X86_XSTATE_SSE_MASK; + + char contents[8]; + if (! bfd_get_section_contents (abfd, xstate, contents, + I386_LINUX_XSAVE_XCR0_OFFSET, 8)) { - size_t size = bfd_section_size (xstate); - - /* Check extended state size. */ - if (size < X86_XSTATE_AVX_SIZE) - xcr0 = X86_XSTATE_SSE_MASK; - else - { - char contents[8]; - - if (! bfd_get_section_contents (abfd, xstate, contents, - I386_LINUX_XSAVE_XCR0_OFFSET, - 8)) - { - warning (_("Couldn't read `xcr0' bytes from " - "`.reg-xstate' section in core file.")); - return 0; - } - - xcr0 = bfd_get_64 (abfd, contents); - } + warning (_("Couldn't read `xcr0' bytes from " + "`.reg-xstate' section in core file.")); + return X86_XSTATE_SSE_MASK; } - else - xcr0 = 0; + + uint64_t xcr0 = bfd_get_64 (abfd, contents); + + if (!i387_set_xsave_layout (xcr0, size, layout)) + return X86_XSTATE_SSE_MASK; return xcr0; } /* See i386-linux-tdep.h. */ +bool +i386_linux_core_read_x86_xsave_layout (struct gdbarch *gdbarch, + x86_xsave_layout &layout) +{ + if (i386_linux_core_read_xsave_info (core_bfd, layout) == X86_XSTATE_SSE_MASK) + return false; + + return true; +} + +/* See i386-linux-tdep.h. */ + const struct target_desc * i386_linux_read_description (uint64_t xcr0) { @@ -708,7 +714,8 @@ i386_linux_core_read_description (struct gdbarch *gdbarch, bfd *abfd) { /* Linux/i386. */ - uint64_t xcr0 = i386_linux_core_read_xcr0 (abfd); + x86_xsave_layout layout; + uint64_t xcr0 = i386_linux_core_read_xsave_info (abfd, layout); const struct target_desc *tdesc = i386_linux_read_description (xcr0); if (tdesc != NULL) @@ -768,8 +775,8 @@ i386_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg", 68, 68, &i386_gregset, NULL, cb_data); if (tdep->xcr0 & X86_XSTATE_AVX) - cb (".reg-xstate", X86_XSTATE_SIZE (tdep->xcr0), - X86_XSTATE_SIZE (tdep->xcr0), &i386_linux_xstateregset, + cb (".reg-xstate", tdep->xsave_layout.sizeof_xsave, + tdep->xsave_layout.sizeof_xsave, &i386_linux_xstateregset, "XSAVE extended state", cb_data); else if (tdep->xcr0 & X86_XSTATE_SSE) cb (".reg-xfp", 512, 512, &i386_fpregset, "extended floating-point", @@ -872,6 +879,8 @@ i386_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdep->sc_num_regs = ARRAY_SIZE (i386_linux_sc_reg_offset); tdep->xsave_xcr0_offset = I386_LINUX_XSAVE_XCR0_OFFSET; + set_gdbarch_core_read_x86_xsave_layout + (gdbarch, i386_linux_core_read_x86_xsave_layout); set_gdbarch_process_record (gdbarch, i386_process_record); set_gdbarch_process_record_signal (gdbarch, i386_linux_record_signal); diff --git a/gdb/i386-linux-tdep.h b/gdb/i386-linux-tdep.h index c0fd1f7f300..66f08aae22d 100644 --- a/gdb/i386-linux-tdep.h +++ b/gdb/i386-linux-tdep.h @@ -20,6 +20,8 @@ #ifndef I386_LINUX_TDEP_H #define I386_LINUX_TDEP_H +#include "gdbsupport/x86-xstate.h" + /* The Linux kernel pretends there is an additional "orig_eax" register. Since GDB needs access to that register to be able to properly restart system calls when necessary (see @@ -34,8 +36,18 @@ /* Total number of registers for GNU/Linux. */ #define I386_LINUX_NUM_REGS (I386_LINUX_ORIG_EAX_REGNUM + 1) -/* Get XSAVE extended state xcr0 from core dump. */ -extern uint64_t i386_linux_core_read_xcr0 (bfd *abfd); +/* Read the XSAVE extended state xcr0 value from the ABFD core file. + If it appears to be valid, return it and fill LAYOUT with values + inferred from that value. + + Otherwise, return X86_XSTATE_SSE_MASK as a fallback and leave + LAYOUT untouched. */ +extern uint64_t i386_linux_core_read_xsave_info (bfd *abfd, + x86_xsave_layout &layout); + +/* Implement the core_read_x86_xsave_layout gdbarch method. */ +extern bool i386_linux_core_read_x86_xsave_layout (struct gdbarch *gdbarch, + x86_xsave_layout &layout); /* Handle and display information related to the MPX bound violation to the user. */ @@ -52,14 +64,7 @@ extern const struct target_desc *i386_linux_read_description (uint64_t xcr0); fxsave_bytes[0..463] sw_usable_bytes[464..511] xstate_hdr_bytes[512..575] - avx_bytes[576..831] - mpx_bytes [960..1032] - avx512_k_regs[1088..1152] - avx512_zmmh_regs0-7[1153..1407] - avx512_zmmh_regs8-15[1408..1663] - avx512_zmm_regs16-31[1664..2687] - pkru[2688..2752] - future_state etc + extended state regions (AVX, MPX, AVX512, PKRU, etc.) }; Same memory layout will be used for the coredump NT_X86_XSTATE From patchwork Fri Jul 14 15:51:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72703 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C12B385E021 for ; Fri, 14 Jul 2023 15:56:54 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id 742533858410 for ; Fri, 14 Jul 2023 15:55:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 742533858410 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 5DE7B1A84E38 for ; Fri, 14 Jul 2023 11:55:54 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 09/15] gdb: Support XSAVE layouts for the current host in the Linux x86 targets. Date: Fri, 14 Jul 2023 08:51:45 -0700 Message-Id: <20230714155151.21723-10-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:54 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Note that this uses the CPUID instruction to determine the total size of the XSAVE register set. If there is a way to fetch the register set size using ptrace that would probably be better. --- gdb/amd64-linux-nat.c | 6 ++++-- gdb/configure.nat | 3 ++- gdb/i386-linux-nat.c | 8 ++++++-- gdb/x86-linux-nat.c | 3 +++ gdb/x86-linux-nat.h | 7 +++++++ 5 files changed, 22 insertions(+), 5 deletions(-) diff --git a/gdb/amd64-linux-nat.c b/gdb/amd64-linux-nat.c index b5b0703879b..6571be40bb5 100644 --- a/gdb/amd64-linux-nat.c +++ b/gdb/amd64-linux-nat.c @@ -210,6 +210,7 @@ void amd64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = regcache->arch (); + const i386_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); int tid; /* GNU/Linux LWP ID's are process ID's. */ @@ -235,7 +236,7 @@ amd64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) if (have_ptrace_getregset == TRIBOOL_TRUE) { - char xstateregs[X86_XSTATE_MAX_SIZE]; + char xstateregs[tdep->xsave_layout.sizeof_xsave]; struct iovec iov; /* Pre-4.14 kernels have a bug (fixed by commit 0852b374173b @@ -270,6 +271,7 @@ void amd64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = regcache->arch (); + const i386_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); int tid; /* GNU/Linux LWP ID's are process ID's. */ @@ -299,7 +301,7 @@ amd64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) if (have_ptrace_getregset == TRIBOOL_TRUE) { - char xstateregs[X86_XSTATE_MAX_SIZE]; + char xstateregs[tdep->xsave_layout.sizeof_xsave]; struct iovec iov; iov.iov_base = xstateregs; diff --git a/gdb/configure.nat b/gdb/configure.nat index b371ad89afe..2739d14a1c4 100644 --- a/gdb/configure.nat +++ b/gdb/configure.nat @@ -254,6 +254,7 @@ case ${gdb_host} in i386) # Host: Intel 386 running GNU/Linux. NATDEPFILES="${NATDEPFILES} x86-nat.o nat/x86-dregs.o \ + nat/x86-xstate.o \ i386-linux-nat.o x86-linux-nat.o nat/linux-btrace.o \ nat/x86-linux.o nat/x86-linux-dregs.o" ;; @@ -319,7 +320,7 @@ case ${gdb_host} in i386) # Host: GNU/Linux x86-64 NATDEPFILES="${NATDEPFILES} x86-nat.o nat/x86-dregs.o \ - amd64-nat.o amd64-linux-nat.o x86-linux-nat.o \ + nat/x86-xstate.o amd64-nat.o amd64-linux-nat.o x86-linux-nat.o \ nat/linux-btrace.o \ nat/x86-linux.o nat/x86-linux-dregs.o \ nat/amd64-linux-siginfo.o" diff --git a/gdb/i386-linux-nat.c b/gdb/i386-linux-nat.c index a524fdc9a1d..7e0572e1907 100644 --- a/gdb/i386-linux-nat.c +++ b/gdb/i386-linux-nat.c @@ -330,7 +330,9 @@ store_fpregs (const struct regcache *regcache, int tid, int regno) static int fetch_xstateregs (struct regcache *regcache, int tid) { - char xstateregs[X86_XSTATE_MAX_SIZE]; + struct gdbarch *gdbarch = regcache->arch (); + const i386_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + char xstateregs[tdep->xsave_layout.sizeof_xsave]; struct iovec iov; if (have_ptrace_getregset != TRIBOOL_TRUE) @@ -353,7 +355,9 @@ fetch_xstateregs (struct regcache *regcache, int tid) static int store_xstateregs (const struct regcache *regcache, int tid, int regno) { - char xstateregs[X86_XSTATE_MAX_SIZE]; + struct gdbarch *gdbarch = regcache->arch (); + const i386_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + char xstateregs[tdep->xsave_layout.sizeof_xsave]; struct iovec iov; if (have_ptrace_getregset != TRIBOOL_TRUE) diff --git a/gdb/x86-linux-nat.c b/gdb/x86-linux-nat.c index ca4eaf5b645..cd8fd9c1dcd 100644 --- a/gdb/x86-linux-nat.c +++ b/gdb/x86-linux-nat.c @@ -36,6 +36,7 @@ #include "amd64-linux-tdep.h" #endif #include "gdbsupport/x86-xstate.h" +#include "nat/x86-xstate.h" #include "nat/linux-btrace.h" #include "nat/linux-nat.h" #include "nat/x86-linux.h" @@ -179,6 +180,8 @@ x86_linux_nat_target::read_description () /* Get XCR0 from XSAVE extended state. */ xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET / sizeof (uint64_t))]; + + m_xsave_layout = x86_fetch_xsave_layout (xcr0, x86_xsave_length ()); } } diff --git a/gdb/x86-linux-nat.h b/gdb/x86-linux-nat.h index fcb5f08d251..a99de6c29ea 100644 --- a/gdb/x86-linux-nat.h +++ b/gdb/x86-linux-nat.h @@ -22,6 +22,7 @@ #include "gdb_proc_service.h" /* For ps_err_e. */ #include "linux-nat.h" +#include "gdbsupport/x86-xstate.h" #include "x86-nat.h" #include "nat/x86-linux.h" @@ -41,6 +42,9 @@ struct x86_linux_nat_target : public x86_nat_target enum btrace_read_type type) override; const struct btrace_config *btrace_conf (const struct btrace_target_info *) override; + x86_xsave_layout fetch_x86_xsave_layout () override + { return m_xsave_layout; } + /* These two are rewired to low_ versions. linux-nat.c queries stopped-by-watchpoint info as soon as an lwp stops (via the low_ methods) and caches the result, to be returned via the normal @@ -74,6 +78,9 @@ struct x86_linux_nat_target : public x86_nat_target protected: /* Override the GNU/Linux inferior startup hook. */ void post_startup_inferior (ptid_t) override; + +private: + x86_xsave_layout m_xsave_layout; }; From patchwork Fri Jul 14 15:51:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72711 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5B2503856948 for ; Fri, 14 Jul 2023 15:57:54 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id 7A9B83858418 for ; Fri, 14 Jul 2023 15:55:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A9B83858418 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id EF7531A84E3A for ; Fri, 14 Jul 2023 11:55:54 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 10/15] gdb: Use x86_xstate_layout to parse the XSAVE extended state area. Date: Fri, 14 Jul 2023 08:51:46 -0700 Message-Id: <20230714155151.21723-11-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:55 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" All of the tables describing the offsets of individual registers for XSAVE state components now hold relative offsets rather than absolute offsets. Some tables (those for MPX registers and ZMMH registers) had to be split into separate tables as they held entries that spanned multiple state components. --- gdb/i387-tdep.c | 467 ++++++++++++++++++++++++++++-------------------- gdb/i387-tdep.h | 1 + 2 files changed, 278 insertions(+), 190 deletions(-) diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c index f25579c1a9a..389cf11bfbd 100644 --- a/gdb/i387-tdep.c +++ b/gdb/i387-tdep.c @@ -732,170 +732,204 @@ i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) /* `xstate_bv' is at byte offset 512. */ #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) -/* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in - the upper 128bit of AVX register data structure used by the "xsave" - instruction where GDB register REGNUM is stored. */ +/* At xsave_avxh_offset[REGNUM] you'll find the relative offset within + the AVX region of the XSAVE extended state where the upper 128bits + of GDB register YMM0 + REGNUM is stored. */ static int xsave_avxh_offset[] = { - 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */ - 576 + 1 * 16, - 576 + 2 * 16, - 576 + 3 * 16, - 576 + 4 * 16, - 576 + 5 * 16, - 576 + 6 * 16, - 576 + 7 * 16, - 576 + 8 * 16, - 576 + 9 * 16, - 576 + 10 * 16, - 576 + 11 * 16, - 576 + 12 * 16, - 576 + 13 * 16, - 576 + 14 * 16, - 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ + 0 * 16, /* Upper 128bit of %ymm0 through ... */ + 1 * 16, + 2 * 16, + 3 * 16, + 4 * 16, + 5 * 16, + 6 * 16, + 7 * 16, + 8 * 16, + 9 * 16, + 10 * 16, + 11 * 16, + 12 * 16, + 13 * 16, + 14 * 16, + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ }; -#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) +#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.avx_offset \ + + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) -/* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in - the upper 128bit of ZMM register data structure used by the "xsave" - instruction where GDB register REGNUM is stored. */ +/* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset + within the ZMM region of the XSAVE extended state where the second + 128bits of GDB register YMM16 + REGNUM is stored. */ static int xsave_ymm_avx512_offset[] = { - /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */ - 1664 + 16 + 0 * 64, /* %ymm16 through... */ - 1664 + 16 + 1 * 64, - 1664 + 16 + 2 * 64, - 1664 + 16 + 3 * 64, - 1664 + 16 + 4 * 64, - 1664 + 16 + 5 * 64, - 1664 + 16 + 6 * 64, - 1664 + 16 + 7 * 64, - 1664 + 16 + 8 * 64, - 1664 + 16 + 9 * 64, - 1664 + 16 + 10 * 64, - 1664 + 16 + 11 * 64, - 1664 + 16 + 12 * 64, - 1664 + 16 + 13 * 64, - 1664 + 16 + 14 * 64, - 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ + 16 + 0 * 64, /* %ymm16 through... */ + 16 + 1 * 64, + 16 + 2 * 64, + 16 + 3 * 64, + 16 + 4 * 64, + 16 + 5 * 64, + 16 + 6 * 64, + 16 + 7 * 64, + 16 + 8 * 64, + 16 + 9 * 64, + 16 + 10 * 64, + 16 + 11 * 64, + 16 + 12 * 64, + 16 + 13 * 64, + 16 + 14 * 64, + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ }; -#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) +#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.zmm_offset \ + + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) + +/* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset + within the ZMM region of the XSAVE extended state where the first + 128bits of GDB register XMM16 + REGNUM is stored. */ static int xsave_xmm_avx512_offset[] = { - 1664 + 0 * 64, /* %ymm16 through... */ - 1664 + 1 * 64, - 1664 + 2 * 64, - 1664 + 3 * 64, - 1664 + 4 * 64, - 1664 + 5 * 64, - 1664 + 6 * 64, - 1664 + 7 * 64, - 1664 + 8 * 64, - 1664 + 9 * 64, - 1664 + 10 * 64, - 1664 + 11 * 64, - 1664 + 12 * 64, - 1664 + 13 * 64, - 1664 + 14 * 64, - 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */ + 0 * 64, /* %xmm16 through... */ + 1 * 64, + 2 * 64, + 3 * 64, + 4 * 64, + 5 * 64, + 6 * 64, + 7 * 64, + 8 * 64, + 9 * 64, + 10 * 64, + 11 * 64, + 12 * 64, + 13 * 64, + 14 * 64, + 15 * 64 /* ... %xmm31 (128 bits each). */ }; -#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) +#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.zmm_offset \ + + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) -static int xsave_mpx_offset[] = { - 960 + 0 * 16, /* bnd0r...bnd3r registers. */ - 960 + 1 * 16, - 960 + 2 * 16, - 960 + 3 * 16, - 1024 + 0 * 8, /* bndcfg ... bndstatus. */ - 1024 + 1 * 8, +/* At xsave_bndregs_offset[REGNUM] you'll find the relative offset + within the BNDREGS region of the XSAVE extended state where the GDB + register BND0R + REGNUM is stored. */ + +static int xsave_bndregs_offset[] = { + 0 * 16, /* bnd0r...bnd3r registers. */ + 1 * 16, + 2 * 16, + 3 * 16 +}; + +#define XSAVE_BNDREGS_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.bndregs_offset \ + + xsave_bndregs_offset[regnum - I387_BND0R_REGNUM (tdep)]) + +static int xsave_bndcfg_offset[] = { + 0 * 8, /* bndcfg ... bndstatus. */ + 1 * 8, }; -#define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) +#define XSAVE_BNDCFG_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.bndcfg_offset \ + + xsave_bndcfg_offset[regnum - I387_BNDCFGU_REGNUM (tdep)]) - /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location - of the AVX512 opmask register data structure used by the "xsave" - instruction where GDB register REGNUM is stored. */ +/* At xsave_avx512_k_offset[REGNUM] you'll find the relative offset + within the K region of the XSAVE extended state where the AVX512 + opmask register K0 + REGNUM is stored. */ static int xsave_avx512_k_offset[] = { - 1088 + 0 * 8, /* %k0 through... */ - 1088 + 1 * 8, - 1088 + 2 * 8, - 1088 + 3 * 8, - 1088 + 4 * 8, - 1088 + 5 * 8, - 1088 + 6 * 8, - 1088 + 7 * 8 /* %k7 (64 bits each). */ + 0 * 8, /* %k0 through... */ + 1 * 8, + 2 * 8, + 3 * 8, + 4 * 8, + 5 * 8, + 6 * 8, + 7 * 8 /* %k7 (64 bits each). */ }; -#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) +#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.k_offset \ + + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) -/* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in - the upper 256bit of AVX512 ZMMH register data structure used by the "xsave" - instruction where GDB register REGNUM is stored. */ -static int xsave_avx512_zmm_h_offset[] = +/* At xsave_avx512_zmm0_h_offset[REGNUM] you find the relative offset + within the ZMM_H region of the XSAVE extended state where the upper + 256bits of the GDB register ZMM0 + REGNUM is stored. */ + +static int xsave_avx512_zmm0_h_offset[] = +{ + 0 * 32, /* Upper 256bit of %zmmh0 through... */ + 1 * 32, + 2 * 32, + 3 * 32, + 4 * 32, + 5 * 32, + 6 * 32, + 7 * 32, + 8 * 32, + 9 * 32, + 10 * 32, + 11 * 32, + 12 * 32, + 13 * 32, + 14 * 32, + 15 * 32 /* Upper 256bit of... %zmmh15 (256 bits each). */ +}; + +#define XSAVE_AVX512_ZMM0_H_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.zmm_h_offset \ + + xsave_avx512_zmm0_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) + +/* At xsave_avx512_zmm16_h_offset[REGNUM] you find the relative offset + within the ZMM_H region of the XSAVE extended state where the upper + 256bits of the GDB register ZMM16 + REGNUM is stored. */ + +static int xsave_avx512_zmm16_h_offset[] = { - 1152 + 0 * 32, - 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */ - 1152 + 2 * 32, - 1152 + 3 * 32, - 1152 + 4 * 32, - 1152 + 5 * 32, - 1152 + 6 * 32, - 1152 + 7 * 32, - 1152 + 8 * 32, - 1152 + 9 * 32, - 1152 + 10 * 32, - 1152 + 11 * 32, - 1152 + 12 * 32, - 1152 + 13 * 32, - 1152 + 14 * 32, - 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */ - 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ - 1664 + 32 + 1 * 64, - 1664 + 32 + 2 * 64, - 1664 + 32 + 3 * 64, - 1664 + 32 + 4 * 64, - 1664 + 32 + 5 * 64, - 1664 + 32 + 6 * 64, - 1664 + 32 + 7 * 64, - 1664 + 32 + 8 * 64, - 1664 + 32 + 9 * 64, - 1664 + 32 + 10 * 64, - 1664 + 32 + 11 * 64, - 1664 + 32 + 12 * 64, - 1664 + 32 + 13 * 64, - 1664 + 32 + 14 * 64, - 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ + 32 + 1 * 64, + 32 + 2 * 64, + 32 + 3 * 64, + 32 + 4 * 64, + 32 + 5 * 64, + 32 + 6 * 64, + 32 + 7 * 64, + 32 + 8 * 64, + 32 + 9 * 64, + 32 + 10 * 64, + 32 + 11 * 64, + 32 + 12 * 64, + 32 + 13 * 64, + 32 + 14 * 64, + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ }; -#define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) +#define XSAVE_AVX512_ZMM16_H_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.zmm_offset \ + + xsave_avx512_zmm16_h_offset[regnum - I387_ZMM16H_REGNUM (tdep)]) -/* At xsave_pkeys_offset[REGNUM] you find the offset to the location - of the PKRU register data structure used by the "xsave" - instruction where GDB register REGNUM is stored. */ +/* At xsave_pkeys_offset[REGNUM] you'll find the relative offset + within the PKEYS region of the XSAVE extended state where the PKRU + register is stored. */ static int xsave_pkeys_offset[] = { -2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by instructions and applications). */ }; -#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ - (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) +#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ + (xsave + (tdep)->xsave_layout.pkru_offset \ + + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) /* See i387-tdep.h. */ @@ -998,14 +1032,16 @@ i387_supply_xsave (struct regcache *regcache, int regnum, x87 = 0x1, sse = 0x2, avxh = 0x4, - mpx = 0x8, - avx512_k = 0x10, - avx512_zmm_h = 0x20, - avx512_ymmh_avx512 = 0x40, - avx512_xmm_avx512 = 0x80, - pkeys = 0x100, - all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h - | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys + bndregs = 0x8, + bndcfg = 0x10, + avx512_k = 0x20, + avx512_zmm0_h = 0x40, + avx512_zmm16_h = 0x80, + avx512_ymmh_avx512 = 0x100, + avx512_xmm_avx512 = 0x200, + pkeys = 0x400, + all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h + | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys } regclass; gdb_assert (regs != NULL); @@ -1018,8 +1054,11 @@ i387_supply_xsave (struct regcache *regcache, int regnum, && regnum < I387_PKEYSEND_REGNUM (tdep)) regclass = pkeys; else if (regnum >= I387_ZMM0H_REGNUM (tdep) + && regnum < I387_ZMM16H_REGNUM (tdep)) + regclass = avx512_zmm0_h; + else if (regnum >= I387_ZMM16H_REGNUM (tdep) && regnum < I387_ZMMENDH_REGNUM (tdep)) - regclass = avx512_zmm_h; + regclass = avx512_zmm16_h; else if (regnum >= I387_K0_REGNUM (tdep) && regnum < I387_KEND_REGNUM (tdep)) regclass = avx512_k; @@ -1033,8 +1072,11 @@ i387_supply_xsave (struct regcache *regcache, int regnum, && regnum < I387_YMMENDH_REGNUM (tdep)) regclass = avxh; else if (regnum >= I387_BND0R_REGNUM (tdep) + && regnum < I387_BNDCFGU_REGNUM (tdep)) + regclass = bndregs; + else if (regnum >= I387_BNDCFGU_REGNUM (tdep) && regnum < I387_MPXEND_REGNUM (tdep)) - regclass = mpx; + regclass = bndcfg; else if (regnum >= I387_XMM0_REGNUM (tdep) && regnum < I387_MXCSR_REGNUM (tdep)) regclass = sse; @@ -1067,13 +1109,20 @@ i387_supply_xsave (struct regcache *regcache, int regnum, regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum)); return; - case avx512_zmm_h: - if ((clear_bv & (regnum < zmm_endlo_regnum ? X86_XSTATE_ZMM_H - : X86_XSTATE_ZMM))) + case avx512_zmm0_h: + if ((clear_bv & X86_XSTATE_ZMM_H)) regcache->raw_supply (regnum, zero); else regcache->raw_supply (regnum, - XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum)); + XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum)); + return; + + case avx512_zmm16_h: + if ((clear_bv & X86_XSTATE_ZMM)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum)); return; case avx512_k: @@ -1106,11 +1155,18 @@ i387_supply_xsave (struct regcache *regcache, int regnum, regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum)); return; - case mpx: + case bndcfg: + if ((clear_bv & X86_XSTATE_BNDCFG)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_BNDCFG_ADDR (tdep, regs, regnum)); + return; + + case bndregs: if ((clear_bv & X86_XSTATE_BNDREGS)) regcache->raw_supply (regnum, zero); else - regcache->raw_supply (regnum, XSAVE_MPX_ADDR (tdep, regs, regnum)); + regcache->raw_supply (regnum, XSAVE_BNDREGS_ADDR (tdep, regs, regnum)); return; case sse: @@ -1159,7 +1215,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum, { for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) regcache->raw_supply (i, - XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); + XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i)); } } @@ -1187,7 +1243,8 @@ i387_supply_xsave (struct regcache *regcache, int regnum, { if ((clear_bv & X86_XSTATE_ZMM)) { - for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + for (i = I387_ZMM16H_REGNUM (tdep); + i < I387_ZMMENDH_REGNUM (tdep); i++) regcache->raw_supply (i, zero); for (i = I387_YMM16H_REGNUM (tdep); i < I387_YMMH_AVX512_END_REGNUM (tdep); @@ -1200,9 +1257,10 @@ i387_supply_xsave (struct regcache *regcache, int regnum, } else { - for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + for (i = I387_ZMM16H_REGNUM (tdep); + i < I387_ZMMENDH_REGNUM (tdep); i++) regcache->raw_supply (i, - XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); + XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i)); for (i = I387_YMM16H_REGNUM (tdep); i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) @@ -1245,7 +1303,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum, { for (i = I387_BND0R_REGNUM (tdep); i < I387_BNDCFGU_REGNUM (tdep); i++) - regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); + regcache->raw_supply (i, XSAVE_BNDREGS_ADDR (tdep, regs, i)); } } @@ -1262,7 +1320,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum, { for (i = I387_BNDCFGU_REGNUM (tdep); i < I387_MPXEND_REGNUM (tdep); i++) - regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); + regcache->raw_supply (i, XSAVE_BNDCFG_ADDR (tdep, regs, i)); } } @@ -1418,14 +1476,16 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, x87 = 0x2, sse = 0x4, avxh = 0x8, - mpx = 0x10, - avx512_k = 0x20, - avx512_zmm_h = 0x40, - avx512_ymmh_avx512 = 0x80, - avx512_xmm_avx512 = 0x100, - pkeys = 0x200, - all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h - | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys + bndregs = 0x10, + bndcfg = 0x20, + avx512_k = 0x40, + avx512_zmm0_h = 0x80, + avx512_zmm16_h = 0x100, + avx512_ymmh_avx512 = 0x200, + avx512_xmm_avx512 = 0x400, + pkeys = 0x800, + all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h + | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys } regclass; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); @@ -1437,8 +1497,11 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, && regnum < I387_PKEYSEND_REGNUM (tdep)) regclass = pkeys; else if (regnum >= I387_ZMM0H_REGNUM (tdep) + && regnum < I387_ZMM16H_REGNUM (tdep)) + regclass = avx512_zmm0_h; + else if (regnum >= I387_ZMM16H_REGNUM (tdep) && regnum < I387_ZMMENDH_REGNUM (tdep)) - regclass = avx512_zmm_h; + regclass = avx512_zmm16_h; else if (regnum >= I387_K0_REGNUM (tdep) && regnum < I387_KEND_REGNUM (tdep)) regclass = avx512_k; @@ -1452,8 +1515,11 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, && regnum < I387_YMMENDH_REGNUM (tdep)) regclass = avxh; else if (regnum >= I387_BND0R_REGNUM (tdep) + && regnum < I387_BNDCFGU_REGNUM (tdep)) + regclass = bndregs; + else if (regnum >= I387_BNDCFGU_REGNUM (tdep) && regnum < I387_MPXEND_REGNUM (tdep)) - regclass = mpx; + regclass = bndcfg; else if (regnum >= I387_XMM0_REGNUM (tdep) && regnum < I387_MXCSR_REGNUM (tdep)) regclass = sse; @@ -1470,7 +1536,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, if (gcore) { /* Clear XSAVE extended state. */ - memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0)); + memset (regs, 0, tdep->xsave_layout.sizeof_xsave); /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ if (tdep->xsave_xcr0_offset != -1) @@ -1505,16 +1571,16 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, if ((clear_bv & X86_XSTATE_BNDREGS)) for (i = I387_BND0R_REGNUM (tdep); i < I387_BNDCFGU_REGNUM (tdep); i++) - memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); + memset (XSAVE_BNDREGS_ADDR (tdep, regs, i), 0, 16); if ((clear_bv & X86_XSTATE_BNDCFG)) for (i = I387_BNDCFGU_REGNUM (tdep); i < I387_MPXEND_REGNUM (tdep); i++) - memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); + memset (XSAVE_BNDCFG_ADDR (tdep, regs, i), 0, 8); if ((clear_bv & X86_XSTATE_ZMM_H)) for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) - memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); + memset (XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i), 0, 32); if ((clear_bv & X86_XSTATE_K)) for (i = I387_K0_REGNUM (tdep); @@ -1523,8 +1589,9 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, if ((clear_bv & X86_XSTATE_ZMM)) { - for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) - memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); + for (i = I387_ZMM16H_REGNUM (tdep); i < I387_ZMMENDH_REGNUM (tdep); + i++) + memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32); for (i = I387_YMM16H_REGNUM (tdep); i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); @@ -1587,15 +1654,27 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, } /* Check if any ZMMH registers are changed. */ - if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) - for (i = I387_ZMM0H_REGNUM (tdep); + if ((tdep->xcr0 & X86_XSTATE_ZMM)) + for (i = I387_ZMM16H_REGNUM (tdep); i < I387_ZMMENDH_REGNUM (tdep); i++) { regcache->raw_collect (i, raw); - p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i); + p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i); if (memcmp (raw, p, 32) != 0) { - xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 32); + } + } + + if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i); + if (memcmp (raw, p, 32) != 0) + { + xstate_bv |= X86_XSTATE_ZMM_H; memcpy (p, raw, 32); } } @@ -1647,7 +1726,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, i < I387_BNDCFGU_REGNUM (tdep); i++) { regcache->raw_collect (i, raw); - p = XSAVE_MPX_ADDR (tdep, regs, i); + p = XSAVE_BNDREGS_ADDR (tdep, regs, i); if (memcmp (raw, p, 16)) { xstate_bv |= X86_XSTATE_BNDREGS; @@ -1661,7 +1740,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, i < I387_MPXEND_REGNUM (tdep); i++) { regcache->raw_collect (i, raw); - p = XSAVE_MPX_ADDR (tdep, regs, i); + p = XSAVE_BNDCFG_ADDR (tdep, regs, i); if (memcmp (raw, p, 8)) { xstate_bv |= X86_XSTATE_BNDCFG; @@ -1750,15 +1829,26 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, } break; - case avx512_zmm_h: - /* This is a ZMM register. */ - p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum); + case avx512_zmm16_h: + /* This is a ZMM16-31 register. */ + p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum); if (memcmp (raw, p, 32) != 0) { - xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); + xstate_bv |= X86_XSTATE_ZMM; memcpy (p, raw, 32); } break; + + case avx512_zmm0_h: + /* This is a ZMM0-15 register. */ + p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 32) != 0) + { + xstate_bv |= X86_XSTATE_ZMM_H; + memcpy (p, raw, 32); + } + break; + case avx512_k: /* This is a AVX512 mask register. */ p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); @@ -1799,25 +1889,22 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, } break; - case mpx: - if (regnum < I387_BNDCFGU_REGNUM (tdep)) + case bndregs: + regcache->raw_collect (regnum, raw); + p = XSAVE_BNDREGS_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) { - regcache->raw_collect (regnum, raw); - p = XSAVE_MPX_ADDR (tdep, regs, regnum); - if (memcmp (raw, p, 16)) - { - xstate_bv |= X86_XSTATE_BNDREGS; - memcpy (p, raw, 16); - } - } - else - { - p = XSAVE_MPX_ADDR (tdep, regs, regnum); - xstate_bv |= X86_XSTATE_BNDCFG; - memcpy (p, raw, 8); + xstate_bv |= X86_XSTATE_BNDREGS; + memcpy (p, raw, 16); } break; + case bndcfg: + p = XSAVE_BNDCFG_ADDR (tdep, regs, regnum); + xstate_bv |= X86_XSTATE_BNDCFG; + memcpy (p, raw, 8); + break; + case sse: /* This is an SSE register. */ p = FXSAVE_ADDR (tdep, regs, regnum); diff --git a/gdb/i387-tdep.h b/gdb/i387-tdep.h index b7674155255..55651a497df 100644 --- a/gdb/i387-tdep.h +++ b/gdb/i387-tdep.h @@ -51,6 +51,7 @@ struct x86_xsave_layout; #define I387_K0_REGNUM(tdep) ((tdep)->k0_regnum) #define I387_NUM_ZMMH_REGS(tdep) ((tdep)->num_zmm_regs) #define I387_ZMM0H_REGNUM(tdep) ((tdep)->zmm0h_regnum) +#define I387_ZMM16H_REGNUM(tdep) ((tdep)->zmm0h_regnum + 16) #define I387_NUM_YMM_AVX512_REGS(tdep) ((tdep)->num_ymm_avx512_regs) #define I387_YMM16H_REGNUM(tdep) ((tdep)->ymm16h_regnum) From patchwork Fri Jul 14 15:51:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72709 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 49FE33857735 for ; Fri, 14 Jul 2023 15:57:38 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id A9DA8385842D for ; Fri, 14 Jul 2023 15:55:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A9DA8385842D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id A692F1A84E3B for ; Fri, 14 Jul 2023 11:55:55 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 11/15] gdbserver: Add a function to set the XSAVE mask and size. Date: Fri, 14 Jul 2023 08:51:47 -0700 Message-Id: <20230714155151.21723-12-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:55 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Make x86_xcr0 private to i387-fp.cc and use i387_set_xsave_mask to set the value instead. Add a static global instance of x86_xsave_layout and initialize it in the new function as well to be used in a future commit to parse XSAVE extended state regions. Update the Linux port to use this function rather than setting x86_xcr0 directly. In the case that XML is not supported, don't bother setting x86_xcr0 to the default value but just omit the call to i387_set_xsave_mask as i387-fp.cc defaults to the SSE case used for non-XML. In addition, use x86_xsave_length to determine the size of the XSAVE register set via CPUID. --- gdbserver/configure.srv | 12 ++++++++---- gdbserver/i387-fp.cc | 16 ++++++++++++++-- gdbserver/i387-fp.h | 4 +++- gdbserver/linux-x86-low.cc | 10 ++++++---- 4 files changed, 31 insertions(+), 11 deletions(-) diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv index f0101994529..72256f82871 100644 --- a/gdbserver/configure.srv +++ b/gdbserver/configure.srv @@ -102,7 +102,8 @@ case "${gdbserver_host}" in i[34567]86-*-linux*) srv_tgtobj="${srv_tgtobj} arch/i386.o" srv_tgtobj="${srv_tgtobj} $srv_linux_obj" srv_tgtobj="${srv_tgtobj} linux-x86-low.o x86-low.o" - srv_tgtobj="${srv_tgtobj} nat/x86-dregs.o i387-fp.o" + srv_tgtobj="${srv_tgtobj} nat/x86-dregs.o" + srv_tgtobj="${srv_tgtobj} nat/x86-xstate.o i387-fp.o" srv_tgtobj="${srv_tgtobj} linux-x86-tdesc.o" srv_tgtobj="${srv_tgtobj} nat/linux-btrace.o" srv_tgtobj="${srv_tgtobj} nat/x86-linux.o" @@ -362,7 +363,8 @@ case "${gdbserver_host}" in srv_linux_thread_db=yes ;; x86_64-*-linux*) srv_tgtobj="$srv_linux_obj linux-x86-low.o x86-low.o" - srv_tgtobj="${srv_tgtobj} nat/x86-dregs.o i387-fp.o" + srv_tgtobj="${srv_tgtobj} nat/x86-dregs.o" + srv_tgtobj="${srv_tgtobj} nat/x86-xstate.o i387-fp.o" srv_tgtobj="${srv_tgtobj} arch/i386.o arch/amd64.o" srv_tgtobj="${srv_tgtobj} linux-x86-tdesc.o" srv_tgtobj="${srv_tgtobj} nat/linux-btrace.o" @@ -377,14 +379,16 @@ case "${gdbserver_host}" in ipa_obj="${ipa_obj} arch/amd64-ipa.o" ;; x86_64-*-mingw*) srv_regobj="" - srv_tgtobj="x86-low.o nat/x86-dregs.o i387-fp.o" + srv_tgtobj="x86-low.o nat/x86-dregs.o" + srv_tgtobj="${srv_tgtobj} nat/x86-xstate.o i387-fp.o" srv_tgtobj="${srv_tgtobj} win32-low.o win32-i386-low.o" srv_tgtobj="${srv_tgtobj} nat/windows-nat.o" srv_tgtobj="${srv_tgtobj} arch/amd64.o arch/i386.o" srv_mingw=yes ;; x86_64-*-cygwin*) srv_regobj="" - srv_tgtobj="x86-low.o nat/x86-dregs.o i387-fp.o" + srv_tgtobj="x86-low.o nat/x86-dregs.o" + srv_tgtobj="${srv_tgtobj} nat/x86-xstate.o i387-fp.o" srv_tgtobj="${srv_tgtobj} win32-low.o win32-i386-low.o" srv_tgtobj="${srv_tgtobj} nat/windows-nat.o" srv_tgtobj="${srv_tgtobj} arch/amd64.o arch/i386.o" diff --git a/gdbserver/i387-fp.cc b/gdbserver/i387-fp.cc index 49795ace9a9..b8d7a912f26 100644 --- a/gdbserver/i387-fp.cc +++ b/gdbserver/i387-fp.cc @@ -19,12 +19,18 @@ #include "server.h" #include "i387-fp.h" #include "gdbsupport/x86-xstate.h" +#include "nat/x86-xstate.h" + +/* Default to SSE. */ +static unsigned long long x86_xcr0 = X86_XSTATE_SSE_MASK; static const int num_mpx_bnd_registers = 4; static const int num_mpx_cfg_registers = 2; static const int num_avx512_k_registers = 8; static const int num_pkeys_registers = 1; +static x86_xsave_layout xsave_layout; + /* Note: These functions preserve the reserved bits in control registers. However, gdbserver promptly throws away that information. */ @@ -974,5 +980,11 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } } -/* Default to SSE. */ -unsigned long long x86_xcr0 = X86_XSTATE_SSE_MASK; +/* See i387-fp.h. */ + +void +i387_set_xsave_mask (uint64_t xcr0, int len) +{ + x86_xcr0 = xcr0; + xsave_layout = x86_fetch_xsave_layout (xcr0, len); +} diff --git a/gdbserver/i387-fp.h b/gdbserver/i387-fp.h index f536a2be15a..09b6a91aa25 100644 --- a/gdbserver/i387-fp.h +++ b/gdbserver/i387-fp.h @@ -28,6 +28,8 @@ void i387_fxsave_to_cache (struct regcache *regcache, const void *buf); void i387_cache_to_xsave (struct regcache *regcache, void *buf); void i387_xsave_to_cache (struct regcache *regcache, const void *buf); -extern unsigned long long x86_xcr0; +/* Set the XSAVE mask and fetch the XSAVE layout via CPUID. */ + +void i387_set_xsave_mask (uint64_t xcr0, int len); #endif /* GDBSERVER_I387_FP_H */ diff --git a/gdbserver/linux-x86-low.cc b/gdbserver/linux-x86-low.cc index 4a538b107be..1483e2a66d7 100644 --- a/gdbserver/linux-x86-low.cc +++ b/gdbserver/linux-x86-low.cc @@ -25,6 +25,7 @@ #include "i387-fp.h" #include "x86-low.h" #include "gdbsupport/x86-xstate.h" +#include "nat/x86-xstate.h" #include "nat/gdb_ptrace.h" #ifdef __x86_64__ @@ -873,6 +874,7 @@ x86_linux_read_description (void) int xcr0_features; int tid; static uint64_t xcr0; + static int xsave_len; struct regset_info *regset; tid = lwpid_of (current_thread); @@ -907,8 +909,6 @@ x86_linux_read_description (void) if (!use_xml) { - x86_xcr0 = X86_XSTATE_SSE_MASK; - /* Don't use XML. */ #ifdef __x86_64__ if (machine == EM_X86_64) @@ -938,11 +938,13 @@ x86_linux_read_description (void) xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET / sizeof (uint64_t))]; + xsave_len = x86_xsave_length (); + /* Use PTRACE_GETREGSET if it is available. */ for (regset = x86_regsets; regset->fill_function != NULL; regset++) if (regset->get_request == PTRACE_GETREGSET) - regset->size = X86_XSTATE_SIZE (xcr0); + regset->size = xsave_len; else if (regset->type != GENERAL_REGS) regset->size = 0; } @@ -953,7 +955,7 @@ x86_linux_read_description (void) && (xcr0 & X86_XSTATE_ALL_MASK)); if (xcr0_features) - x86_xcr0 = xcr0; + i387_set_xsave_mask (xcr0, xsave_len); if (machine == EM_X86_64) { From patchwork Fri Jul 14 15:51:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72706 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D277C3850214 for ; Fri, 14 Jul 2023 15:57:07 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id 3AA813858035 for ; Fri, 14 Jul 2023 15:55:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3AA813858035 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 4AF491A84E3C; Fri, 14 Jul 2023 11:55:56 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Cc: Aleksandar Paunovic Subject: [PATCH v6 12/15] gdbserver: Refactor the legacy region within the xsave struct Date: Fri, 14 Jul 2023 08:51:48 -0700 Message-Id: <20230714155151.21723-13-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:56 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" From: Aleksandar Paunovic Legacy fields of the XSAVE area are already defined within fx_save struct. Use class inheritance to remove code duplication. The two changed functions are called within all tests which run gdbserver. Signed-off-by: Aleksandar Paunovic Co-authored-by: John Baldwin --- gdbserver/i387-fp.cc | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/gdbserver/i387-fp.cc b/gdbserver/i387-fp.cc index b8d7a912f26..a122e2d860b 100644 --- a/gdbserver/i387-fp.cc +++ b/gdbserver/i387-fp.cc @@ -81,29 +81,7 @@ struct i387_fxsave { unsigned char xmm_space[256]; }; -struct i387_xsave { - /* All these are only sixteen bits, plus padding, except for fop (which - is only eleven bits), and fooff / fioff (which are 32 bits each). */ - unsigned short fctrl; - unsigned short fstat; - unsigned short ftag; - unsigned short fop; - unsigned int fioff; - unsigned short fiseg; - unsigned short pad1; - unsigned int fooff; - unsigned short foseg; - unsigned short pad12; - - unsigned int mxcsr; - unsigned int mxcsr_mask; - - /* Space for eight 80-bit FP values in 128-bit spaces. */ - unsigned char st_space[128]; - - /* Space for eight 128-bit XMM values, or 16 on x86-64. */ - unsigned char xmm_space[256]; - +struct i387_xsave : public i387_fxsave { unsigned char reserved1[48]; /* The extended control register 0 (the XFEATURE_ENABLED_MASK @@ -725,7 +703,6 @@ void i387_xsave_to_cache (struct regcache *regcache, const void *buf) { struct i387_xsave *fp = (struct i387_xsave *) buf; - struct i387_fxsave *fxp = (struct i387_fxsave *) buf; bool amd64 = register_size (regcache->tdesc, 0) == 8; int i, top; unsigned long val; @@ -962,7 +939,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) { int tag; if (fp->ftag & (1 << i)) - tag = i387_ftag (fxp, (i + 8 - top) % 8); + tag = i387_ftag (fp, (i + 8 - top) % 8); else tag = 3; val |= tag << (2 * i); From patchwork Fri Jul 14 15:51:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72708 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 13196385AF80 for ; Fri, 14 Jul 2023 15:57:30 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id C94D23857714 for ; Fri, 14 Jul 2023 15:55:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C94D23857714 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id EFC5B1A84E2E; Fri, 14 Jul 2023 11:55:56 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Cc: Aleksandar Paunovic Subject: [PATCH v6 13/15] gdbserver: Use x86_xstate_layout to parse the XSAVE extended state area. Date: Fri, 14 Jul 2023 08:51:49 -0700 Message-Id: <20230714155151.21723-14-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:57 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" From: Aleksandar Paunovic Replace the extended state area fields of i387_xsave with methods which return an offset into the XSAVE buffer. The two changed functions are called within all tests which runs gdbserver. Signed-off-by: Aleksandar Paunovic Co-authored-by: John Baldwin --- gdbserver/i387-fp.cc | 117 +++++++++++++++++++++++++------------------ 1 file changed, 69 insertions(+), 48 deletions(-) diff --git a/gdbserver/i387-fp.cc b/gdbserver/i387-fp.cc index a122e2d860b..f53a6cfc477 100644 --- a/gdbserver/i387-fp.cc +++ b/gdbserver/i387-fp.cc @@ -82,6 +82,8 @@ struct i387_fxsave { }; struct i387_xsave : public i387_fxsave { + /* Size of i387_fxsave is 416 bytes. */ + unsigned char reserved1[48]; /* The extended control register 0 (the XFEATURE_ENABLED_MASK @@ -93,34 +95,53 @@ struct i387_xsave : public i387_fxsave { /* The XSTATE_BV bit vector. */ unsigned long long xstate_bv; - unsigned char reserved3[56]; + /* The XCOMP_BV bit vector. */ + unsigned long long xcomp_bv; - /* Space for eight upper 128-bit YMM values, or 16 on x86-64. */ - unsigned char ymmh_space[256]; + unsigned char reserved3[48]; - unsigned char reserved4[128]; + /* Byte 576. End of registers with fixed position in XSAVE. + The position of other XSAVE registers will be calculated + from the appropriate CPUID calls. */ - /* Space for 4 bound registers values of 128 bits. */ - unsigned char mpx_bnd_space[64]; +private: + /* Base address of XSAVE data as an unsigned char *. Used to derive + pointers to XSAVE state components in the extended state + area. */ + unsigned char *xsave () + { return reinterpret_cast (this); } - /* Space for 2 MPX configuration registers of 64 bits +public: + /* Memory address of eight upper 128-bit YMM values, or 16 on x86-64. */ + unsigned char *ymmh_space () + { return xsave () + xsave_layout.avx_offset; } + + /* Memory address of 4 bound registers values of 128 bits. */ + unsigned char *bndregs_space () + { return xsave () + xsave_layout.bndregs_offset; } + + /* Memory address of 2 MPX configuration registers of 64 bits plus reserved space. */ - unsigned char mpx_cfg_space[16]; + unsigned char *bndcfg_space () + { return xsave () + xsave_layout.bndcfg_offset; } - unsigned char reserved5[48]; + /* Memory address of 8 OpMask register values of 64 bits. */ + unsigned char *k_space () + { return xsave () + xsave_layout.k_offset; } - /* Space for 8 OpMask register values of 64 bits. */ - unsigned char k_space[64]; + /* Memory address of 16 256-bit zmm0-15. */ + unsigned char *zmmh_space () + { return xsave () + xsave_layout.zmm_h_offset; } - /* Space for 16 256-bit zmm0-15. */ - unsigned char zmmh_low_space[512]; + /* Memory address of 16 512-bit zmm16-31 values. */ + unsigned char *zmm_space () + { return xsave () + xsave_layout.zmm_offset; } - /* Space for 16 512-bit zmm16-31 values. */ - unsigned char zmmh_high_space[1024]; - - /* Space for 1 32-bit PKRU register. The HW XSTATE size for this feature is - actually 64 bits, but WRPKRU/RDPKRU instructions ignore upper 32 bits. */ - unsigned char pkru_space[8]; + /* Memory address of 1 32-bit PKRU register. The HW XSTATE size for this + feature is actually 64 bits, but WRPKRU/RDPKRU instructions ignore upper + 32 bits. */ + unsigned char *pkru_space () + { return xsave () + xsave_layout.pkru_offset; } }; void @@ -242,7 +263,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) unsigned long long xstate_bv = 0; unsigned long long clear_bv = 0; char raw[64]; - char *p; + unsigned char *p; /* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */ int num_xmm_registers = amd64 ? 16 : 8; @@ -282,40 +303,40 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) if ((clear_bv & X86_XSTATE_AVX)) for (i = 0; i < num_xmm_registers; i++) - memset (((char *) &fp->ymmh_space[0]) + i * 16, 0, 16); + memset (fp->ymmh_space () + i * 16, 0, 16); if ((clear_bv & X86_XSTATE_SSE) && (clear_bv & X86_XSTATE_AVX)) memset (((char *) &fp->mxcsr), 0, 4); if ((clear_bv & X86_XSTATE_BNDREGS)) for (i = 0; i < num_mpx_bnd_registers; i++) - memset (((char *) &fp->mpx_bnd_space[0]) + i * 16, 0, 16); + memset (fp->bndregs_space () + i * 16, 0, 16); if ((clear_bv & X86_XSTATE_BNDCFG)) for (i = 0; i < num_mpx_cfg_registers; i++) - memset (((char *) &fp->mpx_cfg_space[0]) + i * 8, 0, 8); + memset (fp->bndcfg_space () + i * 8, 0, 8); if ((clear_bv & X86_XSTATE_K)) for (i = 0; i < num_avx512_k_registers; i++) - memset (((char *) &fp->k_space[0]) + i * 8, 0, 8); + memset (fp->k_space () + i * 8, 0, 8); if ((clear_bv & X86_XSTATE_ZMM_H)) for (i = 0; i < num_avx512_zmmh_low_registers; i++) - memset (((char *) &fp->zmmh_low_space[0]) + i * 32, 0, 32); + memset (fp->zmmh_space () + i * 32, 0, 32); if ((clear_bv & X86_XSTATE_ZMM)) { for (i = 0; i < num_avx512_zmmh_high_registers; i++) - memset (((char *) &fp->zmmh_high_space[0]) + 32 + i * 64, 0, 32); + memset (fp->zmm_space () + 32 + i * 64, 0, 32); for (i = 0; i < num_avx512_xmm_registers; i++) - memset (((char *) &fp->zmmh_high_space[0]) + i * 64, 0, 16); + memset (fp->zmm_space () + i * 64, 0, 16); for (i = 0; i < num_avx512_ymmh_registers; i++) - memset (((char *) &fp->zmmh_high_space[0]) + 16 + i * 64, 0, 16); + memset (fp->zmm_space () + 16 + i * 64, 0, 16); } if ((clear_bv & X86_XSTATE_PKRU)) for (i = 0; i < num_pkeys_registers; i++) - memset (((char *) &fp->pkru_space[0]) + i * 4, 0, 4); + memset (fp->pkru_space () + i * 4, 0, 4); } /* Check if any x87 registers are changed. */ @@ -326,7 +347,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < 8; i++) { collect_register (regcache, i + st0_regnum, raw); - p = ((char *) &fp->st_space[0]) + i * 16; + p = fp->st_space + i * 16; if (memcmp (raw, p, 10)) { xstate_bv |= X86_XSTATE_X87; @@ -343,7 +364,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_xmm_registers; i++) { collect_register (regcache, i + xmm0_regnum, raw); - p = ((char *) &fp->xmm_space[0]) + i * 16; + p = fp->xmm_space + i * 16; if (memcmp (raw, p, 16)) { xstate_bv |= X86_XSTATE_SSE; @@ -360,7 +381,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_xmm_registers; i++) { collect_register (regcache, i + ymm0h_regnum, raw); - p = ((char *) &fp->ymmh_space[0]) + i * 16; + p = fp->ymmh_space () + i * 16; if (memcmp (raw, p, 16)) { xstate_bv |= X86_XSTATE_AVX; @@ -377,7 +398,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_mpx_bnd_registers; i++) { collect_register (regcache, i + bnd0r_regnum, raw); - p = ((char *) &fp->mpx_bnd_space[0]) + i * 16; + p = fp->bndregs_space () + i * 16; if (memcmp (raw, p, 16)) { xstate_bv |= X86_XSTATE_BNDREGS; @@ -394,7 +415,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_mpx_cfg_registers; i++) { collect_register (regcache, i + bndcfg_regnum, raw); - p = ((char *) &fp->mpx_cfg_space[0]) + i * 8; + p = fp->bndcfg_space () + i * 8; if (memcmp (raw, p, 8)) { xstate_bv |= X86_XSTATE_BNDCFG; @@ -411,7 +432,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_avx512_k_registers; i++) { collect_register (regcache, i + k0_regnum, raw); - p = ((char *) &fp->k_space[0]) + i * 8; + p = fp->k_space () + i * 8; if (memcmp (raw, p, 8) != 0) { xstate_bv |= X86_XSTATE_K; @@ -428,7 +449,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_avx512_zmmh_low_registers; i++) { collect_register (regcache, i + zmm0h_regnum, raw); - p = ((char *) &fp->zmmh_low_space[0]) + i * 32; + p = fp->zmmh_space () + i * 32; if (memcmp (raw, p, 32) != 0) { xstate_bv |= X86_XSTATE_ZMM_H; @@ -447,7 +468,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_avx512_zmmh_high_registers; i++) { collect_register (regcache, i + zmm16h_regnum, raw); - p = ((char *) &fp->zmmh_high_space[0]) + 32 + i * 64; + p = fp->zmm_space () + 32 + i * 64; if (memcmp (raw, p, 32) != 0) { xstate_bv |= X86_XSTATE_ZMM; @@ -466,7 +487,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_avx512_xmm_registers; i++) { collect_register (regcache, i + xmm_avx512_regnum, raw); - p = ((char *) &fp->zmmh_high_space[0]) + i * 64; + p = fp->zmm_space () + i * 64; if (memcmp (raw, p, 16) != 0) { xstate_bv |= X86_XSTATE_ZMM; @@ -485,7 +506,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_avx512_ymmh_registers; i++) { collect_register (regcache, i + ymmh_avx512_regnum, raw); - p = ((char *) &fp->zmmh_high_space[0]) + 16 + i * 64; + p = fp->zmm_space () + 16 + i * 64; if (memcmp (raw, p, 16) != 0) { xstate_bv |= X86_XSTATE_ZMM; @@ -502,7 +523,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) for (i = 0; i < num_pkeys_registers; i++) { collect_register (regcache, i + pkru_regnum, raw); - p = ((char *) &fp->pkru_space[0]) + i * 4; + p = fp->pkru_space () + i * 4; if (memcmp (raw, p, 4) != 0) { xstate_bv |= X86_XSTATE_PKRU; @@ -707,7 +728,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) int i, top; unsigned long val; unsigned long long clear_bv; - gdb_byte *p; + unsigned char *p; /* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */ int num_xmm_registers = amd64 ? 16 : 8; @@ -768,7 +789,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->ymmh_space[0]; + p = fp->ymmh_space (); for (i = 0; i < num_xmm_registers; i++) supply_register (regcache, i + ymm0h_regnum, p + i * 16); } @@ -786,7 +807,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->mpx_bnd_space[0]; + p = fp->bndregs_space (); for (i = 0; i < num_mpx_bnd_registers; i++) supply_register (regcache, i + bnd0r_regnum, p + i * 16); } @@ -804,7 +825,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->mpx_cfg_space[0]; + p = fp->bndcfg_space (); for (i = 0; i < num_mpx_cfg_registers; i++) supply_register (regcache, i + bndcfg_regnum, p + i * 8); } @@ -821,7 +842,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->k_space[0]; + p = fp->k_space (); for (i = 0; i < num_avx512_k_registers; i++) supply_register (regcache, i + k0_regnum, p + i * 8); } @@ -838,7 +859,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->zmmh_low_space[0]; + p = fp->zmmh_space (); for (i = 0; i < num_avx512_zmmh_low_registers; i++) supply_register (regcache, i + zmm0h_regnum, p + i * 32); } @@ -867,7 +888,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->zmmh_high_space[0]; + p = fp->zmm_space (); for (i = 0; i < num_avx512_zmmh_high_registers; i++) supply_register (regcache, i + zmm16h_regnum, p + 32 + i * 64); for (i = 0; i < num_avx512_ymmh_registers; i++) @@ -888,7 +909,7 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) } else { - p = (gdb_byte *) &fp->pkru_space[0]; + p = fp->pkru_space (); for (i = 0; i < num_pkeys_registers; i++) supply_register (regcache, i + pkru_regnum, p + i * 4); } From patchwork Fri Jul 14 15:51:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72712 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 80D42385697F for ; Fri, 14 Jul 2023 15:58:08 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id 7AABB3858296 for ; Fri, 14 Jul 2023 15:55:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7AABB3858296 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id AE9F11A84B9B for ; Fri, 14 Jul 2023 11:55:57 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 14/15] x86: Remove X86_XSTATE_SIZE and related constants. Date: Fri, 14 Jul 2023 08:51:50 -0700 Message-Id: <20230714155151.21723-15-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:57 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" --- gdbsupport/x86-xstate.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/gdbsupport/x86-xstate.h b/gdbsupport/x86-xstate.h index 27fc0bd12f2..40963bda55b 100644 --- a/gdbsupport/x86-xstate.h +++ b/gdbsupport/x86-xstate.h @@ -99,11 +99,6 @@ constexpr bool operator!= (const x86_xsave_layout &lhs, #define X86_XSTATE_SSE_SIZE 576 #define X86_XSTATE_AVX_SIZE 832 -#define X86_XSTATE_BNDREGS_SIZE 1024 -#define X86_XSTATE_BNDCFG_SIZE 1088 -#define X86_XSTATE_AVX512_SIZE 2688 -#define X86_XSTATE_PKRU_SIZE 2696 -#define X86_XSTATE_MAX_SIZE 2696 /* In case one of the MPX XCR0 bits is set we consider we have MPX. */ @@ -112,13 +107,6 @@ constexpr bool operator!= (const x86_xsave_layout &lhs, #define HAS_AVX512(XCR0) (((XCR0) & X86_XSTATE_AVX512) != 0) #define HAS_PKRU(XCR0) (((XCR0) & X86_XSTATE_PKRU) != 0) -/* Get I386 XSAVE extended state size. */ -#define X86_XSTATE_SIZE(XCR0) \ - (HAS_PKRU (XCR0) ? X86_XSTATE_PKRU_SIZE : \ - (HAS_AVX512 (XCR0) ? X86_XSTATE_AVX512_SIZE : \ - (HAS_MPX (XCR0) ? X86_XSTATE_BNDCFG_SIZE : \ - (HAS_AVX (XCR0) ? X86_XSTATE_AVX_SIZE : X86_XSTATE_SSE_SIZE)))) - /* Initial value for fctrl register, as defined in the X86 manual, and confirmed in the (Linux) kernel source. When the x87 floating point feature is not enabled in an inferior we use this as the value of the From patchwork Fri Jul 14 15:51:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 72713 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 811AA3853559 for ; Fri, 14 Jul 2023 15:58:25 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id ED2D038582BE for ; Fri, 14 Jul 2023 15:55:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ED2D038582BE Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (c-98-35-126-114.hsd1.ca.comcast.net [98.35.126.114]) by mail.baldwin.cx (Postfix) with ESMTPSA id 5195E1A84C72 for ; Fri, 14 Jul 2023 11:55:58 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v6 15/15] gdbserver: Simplify handling of ZMM registers. Date: Fri, 14 Jul 2023 08:51:51 -0700 Message-Id: <20230714155151.21723-16-jhb@FreeBSD.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230714155151.21723-1-jhb@FreeBSD.org> References: <20230714155151.21723-1-jhb@FreeBSD.org> MIME-Version: 1.0 X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Fri, 14 Jul 2023 11:55:58 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" - Reuse num_xmm_registers directly for the count of ZMM0-15 registers as is already done for the YMM registers for AVX rather than using a new variable that is always the same. - Replace 3 identical variables for the count of upper ZMM16-31 registers with a single variable. Make use of this to merge various loops working on the ZMM XSAVE region so that all of the handling for the various sub-registers in this region are always handled in a single loop. - While here, fix some bugs in i387_cache_to_xsave on where if X86_XSTATE_ZMM was set on i386 (e.g. a 32-bit process on a 64-bit kernel), the -1 register nums would wrap around and store the value of GPRs in the XSAVE area. This should be harmless, but is definitely odd. Instead, check num_zmm_high_registers directly when checking X86_XSTATE_ZMM and skip the ZMM region handling entirely if the register count is 0. --- gdbserver/i387-fp.cc | 132 +++++++++++++++---------------------------- 1 file changed, 46 insertions(+), 86 deletions(-) diff --git a/gdbserver/i387-fp.cc b/gdbserver/i387-fp.cc index f53a6cfc477..91d3a0b8ca3 100644 --- a/gdbserver/i387-fp.cc +++ b/gdbserver/i387-fp.cc @@ -267,12 +267,8 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) /* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */ int num_xmm_registers = amd64 ? 16 : 8; - /* AVX512 extends the existing xmm/ymm registers to a wider mode: zmm. */ - int num_avx512_zmmh_low_registers = num_xmm_registers; - /* AVX512 adds 16 extra regs in Amd64 mode, but none in I386 mode.*/ - int num_avx512_zmmh_high_registers = amd64 ? 16 : 0; - int num_avx512_ymmh_registers = amd64 ? 16 : 0; - int num_avx512_xmm_registers = amd64 ? 16 : 0; + /* AVX512 adds 16 extra ZMM regs in Amd64 mode, but none in I386 mode.*/ + int num_zmm_high_registers = amd64 ? 16 : 0; /* The supported bits in `xstat_bv' are 8 bytes. Clear part in vector registers if its bit in xstat_bv is zero. */ @@ -321,18 +317,12 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) memset (fp->k_space () + i * 8, 0, 8); if ((clear_bv & X86_XSTATE_ZMM_H)) - for (i = 0; i < num_avx512_zmmh_low_registers; i++) + for (i = 0; i < num_xmm_registers; i++) memset (fp->zmmh_space () + i * 32, 0, 32); if ((clear_bv & X86_XSTATE_ZMM)) - { - for (i = 0; i < num_avx512_zmmh_high_registers; i++) - memset (fp->zmm_space () + 32 + i * 64, 0, 32); - for (i = 0; i < num_avx512_xmm_registers; i++) - memset (fp->zmm_space () + i * 64, 0, 16); - for (i = 0; i < num_avx512_ymmh_registers; i++) - memset (fp->zmm_space () + 16 + i * 64, 0, 16); - } + for (i = 0; i < num_zmm_high_registers; i++) + memset (fp->zmm_space () + i * 64, 0, 64); if ((clear_bv & X86_XSTATE_PKRU)) for (i = 0; i < num_pkeys_registers; i++) @@ -446,7 +436,7 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) { int zmm0h_regnum = find_regno (regcache->tdesc, "zmm0h"); - for (i = 0; i < num_avx512_zmmh_low_registers; i++) + for (i = 0; i < num_xmm_registers; i++) { collect_register (regcache, i + zmm0h_regnum, raw); p = fp->zmmh_space () + i * 32; @@ -458,55 +448,35 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf) } } - /* Check if any of ZMM16H-ZMM31H registers are changed. */ - if ((x86_xcr0 & X86_XSTATE_ZMM)) + /* Check if any of ZMM16-ZMM31 registers are changed. */ + if ((x86_xcr0 & X86_XSTATE_ZMM) && num_zmm_high_registers != 0) { - int zmm16h_regnum = (num_avx512_zmmh_high_registers == 0 - ? -1 - : find_regno (regcache->tdesc, "zmm16h")); + int zmm16h_regnum = find_regno (regcache->tdesc, "zmm16h"); + int ymm16h_regnum = find_regno (regcache->tdesc, "ymm16h"); + int xmm16_regnum = find_regno (regcache->tdesc, "xmm16"); - for (i = 0; i < num_avx512_zmmh_high_registers; i++) + for (i = 0; i < num_zmm_high_registers; i++) { - collect_register (regcache, i + zmm16h_regnum, raw); - p = fp->zmm_space () + 32 + i * 64; - if (memcmp (raw, p, 32) != 0) - { - xstate_bv |= X86_XSTATE_ZMM; - memcpy (p, raw, 32); - } - } - } - - /* Check if any XMM_AVX512 registers are changed. */ - if ((x86_xcr0 & X86_XSTATE_ZMM)) - { - int xmm_avx512_regnum = (num_avx512_xmm_registers == 0 - ? -1 - : find_regno (regcache->tdesc, "xmm16")); - - for (i = 0; i < num_avx512_xmm_registers; i++) - { - collect_register (regcache, i + xmm_avx512_regnum, raw); p = fp->zmm_space () + i * 64; - if (memcmp (raw, p, 16) != 0) + + /* ZMMH sub-register. */ + collect_register (regcache, i + zmm16h_regnum, raw); + if (memcmp (raw, p + 32, 32) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 32); + } + + /* YMMH sub-register. */ + collect_register (regcache, i + ymm16h_regnum, raw); + if (memcmp (raw, p + 16, 16) != 0) { xstate_bv |= X86_XSTATE_ZMM; memcpy (p, raw, 16); } - } - } - /* Check if any YMMH_AVX512 registers are changed. */ - if ((x86_xcr0 & X86_XSTATE_ZMM)) - { - int ymmh_avx512_regnum = (num_avx512_ymmh_registers == 0 - ? -1 - : find_regno (regcache->tdesc, "ymm16h")); - - for (i = 0; i < num_avx512_ymmh_registers; i++) - { - collect_register (regcache, i + ymmh_avx512_regnum, raw); - p = fp->zmm_space () + 16 + i * 64; + /* XMM sub-register. */ + collect_register (regcache, i + xmm16_regnum, raw); if (memcmp (raw, p, 16) != 0) { xstate_bv |= X86_XSTATE_ZMM; @@ -732,12 +702,8 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) /* Amd64 has 16 xmm regs; I386 has 8 xmm regs. */ int num_xmm_registers = amd64 ? 16 : 8; - /* AVX512 extends the existing xmm/ymm registers to a wider mode: zmm. */ - int num_avx512_zmmh_low_registers = num_xmm_registers; - /* AVX512 adds 16 extra regs in Amd64 mode, but none in I386 mode.*/ - int num_avx512_zmmh_high_registers = amd64 ? 16 : 0; - int num_avx512_ymmh_registers = amd64 ? 16 : 0; - int num_avx512_xmm_registers = amd64 ? 16 : 0; + /* AVX512 adds 16 extra ZMM regs in Amd64 mode, but none in I386 mode.*/ + int num_zmm_high_registers = amd64 ? 16 : 0; /* The supported bits in `xstat_bv' are 8 bytes. Clear part in vector registers if its bit in xstat_bv is zero. */ @@ -854,47 +820,41 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf) if ((clear_bv & X86_XSTATE_ZMM_H) != 0) { - for (i = 0; i < num_avx512_zmmh_low_registers; i++) + for (i = 0; i < num_xmm_registers; i++) supply_register_zeroed (regcache, i + zmm0h_regnum); } else { p = fp->zmmh_space (); - for (i = 0; i < num_avx512_zmmh_low_registers; i++) + for (i = 0; i < num_xmm_registers; i++) supply_register (regcache, i + zmm0h_regnum, p + i * 32); } } - if ((x86_xcr0 & X86_XSTATE_ZMM) != 0) + if ((x86_xcr0 & X86_XSTATE_ZMM) != 0 && num_zmm_high_registers != 0) { - int zmm16h_regnum = (num_avx512_zmmh_high_registers == 0 - ? -1 - : find_regno (regcache->tdesc, "zmm16h")); - int ymm16h_regnum = (num_avx512_ymmh_registers == 0 - ? -1 - : find_regno (regcache->tdesc, "ymm16h")); - int xmm16_regnum = (num_avx512_xmm_registers == 0 - ? -1 - : find_regno (regcache->tdesc, "xmm16")); + int zmm16h_regnum = find_regno (regcache->tdesc, "zmm16h"); + int ymm16h_regnum = find_regno (regcache->tdesc, "ymm16h"); + int xmm16_regnum = find_regno (regcache->tdesc, "xmm16"); if ((clear_bv & X86_XSTATE_ZMM) != 0) { - for (i = 0; i < num_avx512_zmmh_high_registers; i++) - supply_register_zeroed (regcache, i + zmm16h_regnum); - for (i = 0; i < num_avx512_ymmh_registers; i++) - supply_register_zeroed (regcache, i + ymm16h_regnum); - for (i = 0; i < num_avx512_xmm_registers; i++) - supply_register_zeroed (regcache, i + xmm16_regnum); + for (i = 0; i < num_zmm_high_registers; i++) + { + supply_register_zeroed (regcache, i + zmm16h_regnum); + supply_register_zeroed (regcache, i + ymm16h_regnum); + supply_register_zeroed (regcache, i + xmm16_regnum); + } } else { p = fp->zmm_space (); - for (i = 0; i < num_avx512_zmmh_high_registers; i++) - supply_register (regcache, i + zmm16h_regnum, p + 32 + i * 64); - for (i = 0; i < num_avx512_ymmh_registers; i++) - supply_register (regcache, i + ymm16h_regnum, p + 16 + i * 64); - for (i = 0; i < num_avx512_xmm_registers; i++) - supply_register (regcache, i + xmm16_regnum, p + i * 64); + for (i = 0; i < num_zmm_high_registers; i++) + { + supply_register (regcache, i + zmm16h_regnum, p + 32 + i * 64); + supply_register (regcache, i + ymm16h_regnum, p + 16 + i * 64); + supply_register (regcache, i + xmm16_regnum, p + i * 64); + } } }