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To handle this use case, we are adding an upper bound parameter on enhanced REP MOVSB:'__x86_max_rep_movsb_threshold'. As per large-bench results, we are configuring this parameter to the L2 cache size for AMD machines and applicable from Zen3 architecture supporting the ERMS feature. For architectures other than AMD, it is the computed value of non-temporal threshold parameter. Reviewed-by: Premachandra Mallappa --- sysdeps/x86/cacheinfo.c | 15 ++++++++++++++- .../x86_64/multiarch/memmove-vec-unaligned-erms.S | 4 ++-- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 3fb4a028d8..9d7f8992be 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -1,5 +1,5 @@ /* x86_64 cache info. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -533,6 +533,9 @@ long int __x86_shared_non_temporal_threshold attribute_hidden; /* Threshold to use Enhanced REP MOVSB. */ long int __x86_rep_movsb_threshold attribute_hidden = 2048; +/* Threshold to stop using Enhanced REP MOVSB. */ +long int __x86_max_rep_movsb_threshold attribute_hidden = 512 * 1024; + /* Threshold to use Enhanced REP STOSB. */ long int __x86_rep_stosb_threshold attribute_hidden = 2048; @@ -839,6 +842,11 @@ init_cacheinfo (void) /* Account for exclusive L2 and L3 caches. */ shared += core; } + /* ERMS feature is implemented from Zen3 architecture and it is + performing poorly for data above L2 cache size. Henceforth, adding + an upper bound threshold parameter to limit the usage of Enhanced + REP MOVSB operations and setting its value to L2 cache size. */ + __x86_max_rep_movsb_threshold = core; } } @@ -909,6 +917,11 @@ init_cacheinfo (void) else __x86_rep_movsb_threshold = rep_movsb_threshold; + /* Setting the upper bound of ERMS to the known default value of + non-temporal threshold for architectures other than AMD. */ + if (cpu_features->basic.kind != arch_kind_amd) + __x86_max_rep_movsb_threshold = __x86_shared_non_temporal_threshold; + # if HAVE_TUNABLES __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; # endif diff --git a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S index bd5dc1a3f3..c18eaf7ef6 100644 --- a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S @@ -1,5 +1,5 @@ /* memmove/memcpy/mempcpy with unaligned load/store and rep movsb - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -233,7 +233,7 @@ L(return): ret L(movsb): - cmp __x86_shared_non_temporal_threshold(%rip), %RDX_LP + cmp __x86_max_rep_movsb_threshold(%rip), %RDX_LP jae L(more_8x_vec) cmpq %rsi, %rdi jb 1f