From patchwork Tue Dec 29 11:47:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 41580 X-Patchwork-Delegate: azanella@linux.vnet.ibm.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B76EF388A018; Tue, 29 Dec 2020 11:48:25 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 7B9023887016 for ; Tue, 29 Dec 2020 11:48:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7B9023887016 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=huangpei@loongson.cn Received: from localhost.localdomain (unknown [196.245.9.36]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxj8thF+tfe0YHAA--.8248S3; Tue, 29 Dec 2020 19:48:14 +0800 (CST) From: Huang Pei To: Joseph Myers Subject: [PATCH V4 1/2] mips: add hp-timing support for MIPS R2 Date: Tue, 29 Dec 2020 19:47:40 +0800 Message-Id: <20201229114741.14685-2-huangpei@loongson.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201229114741.14685-1-huangpei@loongson.cn> References: <20201229114741.14685-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Dxj8thF+tfe0YHAA--.8248S3 X-Coremail-Antispam: 1UD129KBjvJXoW7Zr1ruF1xCF1fXF4rGFy3Jwb_yoW8Kw48pF 4kCF45GF4kX3y2k3WfXFsrGF15tFZ5Xr15KF13CrW3Jwn8JFyrXrW29ryYgw1xJFyxuF97 ZFW7WFyUuan7AFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBF14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1Y6r1xM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE47Wl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUHHq7UUUUU= X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Chenghua Xu , libc-alpha Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be enough for rtld. Linux/MIPS kernel added emulation for 'rdhwr %0, $2'，uncondionally. Userspace CAN NOT tell directly whether 'rdhwr' is not implemented, or disabled (by clear bit[2] of CP0 Hwena). If you had any doubt on the precision of 'rdhwr %0, $2', DO check both your hardware and software environment(such as in a para-virtualized guest). --- sysdeps/mips/hp-timing.h | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 sysdeps/mips/hp-timing.h diff --git a/sysdeps/mips/hp-timing.h b/sysdeps/mips/hp-timing.h new file mode 100644 index 0000000000..43cb695f2f --- /dev/null +++ b/sysdeps/mips/hp-timing.h @@ -0,0 +1,44 @@ +/* High precision, low overhead timing functions. MIPS version. + Copyright (C) 2020 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Huang Pei , 2020. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef _HP_TIMING_MIPS_H +#define _HP_TIMING_MIPS_H 1 + +#if IS_IN(rtld) && __mips_isa_rev >= 2 +/* MIPS R2 always have the timestamp register. but it's got only 8 seconds + * range, assuming half of cpu frequence 800Mhz . Use it for ld.so + * profiling only*/ +#define HP_TIMING_INLINE (1) + +/* We use 32bit values for the times. */ +typedef unsigned int hp_timing_t; + +/* Read the cp0 count, this maybe inaccurate. */ +#define HP_TIMING_NOW(Var) \ + ({ unsigned int _count; \ + asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \ + (Var) = _count; }) + +# include + +#else +# include +#endif /* IS_IN(rtld) && __mips_isa_rev >= 2 */ + +#endif /* hp-timing.h */ From patchwork Tue Dec 29 11:47:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 41581 X-Patchwork-Delegate: azanella@linux.vnet.ibm.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 22F623887038; Tue, 29 Dec 2020 11:48:33 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 68A923887016 for ; Tue, 29 Dec 2020 11:48:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 68A923887016 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=huangpei@loongson.cn Received: from localhost.localdomain (unknown [196.245.9.36]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxj8thF+tfe0YHAA--.8248S4; Tue, 29 Dec 2020 19:48:21 +0800 (CST) From: Huang Pei To: Joseph Myers Subject: [PATCH V4 2/2] mips: remove old syscall restart convention Date: Tue, 29 Dec 2020 19:47:41 +0800 Message-Id: <20201229114741.14685-3-huangpei@loongson.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201229114741.14685-1-huangpei@loongson.cn> References: <20201229114741.14685-1-huangpei@loongson.cn> X-CM-TRANSID: AQAAf9Dxj8thF+tfe0YHAA--.8248S4 X-Coremail-Antispam: 1UD129KBjvAXoWfGrW8Ww47tr47Kr4UCFyDKFg_yoW8Ar48Jo Z7Xrs5Jw48Gr48CF98A3y3J39xCry2qr1rtF1DWayxZ3Wxtr4q9a48Ga9xur4fur4jgrWr Xr93K3Z5KFWYqFZxn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYA7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6xArMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUboKZJUUUUU== X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Chenghua Xu , libc-alpha Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Before Linux/MIPS 2.6.36, kernel expected setting syscall number(aka "li v0, #sys_number") right precedes "syscall", so the kernel syscall restart sequence can use CP0 EPC - 4 to restart the syscall, because kernel DID NOT save v0 during syscall handling. Linux 2.6.36 canceled this restriction. See sysdeps/unix/sysv/linux/mips/{mips32,mips64}/sysdep.h Since glibc-2.24 the minimum kernel version is 3.2(much higer than 2.6.36), I think it is OK to remove the ugly register spill in syscall.S just because of the old convention This also remove the unaligned stack pointer. For consistency, it also remove all other old syscall restart sequence. --- sysdeps/unix/sysv/linux/mips/mips32/sysdep.h | 89 ++++----------- sysdeps/unix/sysv/linux/mips/mips64/syscall.S | 14 +-- sysdeps/unix/sysv/linux/mips/mips64/sysdep.h | 103 +++++------------- 3 files changed, 49 insertions(+), 157 deletions(-) diff --git a/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h b/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h index 49856c3249..601bd9abc7 100644 --- a/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h +++ b/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h @@ -60,18 +60,7 @@ GIT repository as commit 96187fb0bc30cd7919759d371d810e928048249d, that first appeared in the 2.6.36 release. Since then the kernel has had code that reloads $v0 upon syscall restart and resumes right at the - SYSCALL instruction, so no special arrangement is needed anymore. - - For backwards compatibility with existing kernel binaries we support - the old convention by choosing the instruction preceding SYSCALL - carefully. This also means we have to force a 32-bit encoding of the - microMIPS MOVE instruction if one is used. */ - -#ifdef __mips_micromips -# define MOVE32 "move32" -#else -# define MOVE32 "move" -#endif + SYSCALL instruction, so no special arrangement is needed anymore. */ #undef INTERNAL_SYSCALL #undef INTERNAL_SYSCALL_NCS @@ -109,97 +98,75 @@ union __mips_syscall_return }) # define INTERNAL_SYSCALL_MIPS16(number, err, nr, args...) \ - internal_syscall##nr ("lw\t%0, %2\n\t", \ - "R" (number), \ - number, err, args) + internal_syscall##nr (number, err, args) #else /* !__mips16 */ # define INTERNAL_SYSCALL(name, nr, args...) \ - internal_syscall##nr ("li\t%0, %2\t\t\t# " #name "\n\t", \ - "IK" (SYS_ify (name)), \ - SYS_ify (name), err, args) + internal_syscall##nr (SYS_ify (name), err, args) # define INTERNAL_SYSCALL_NCS(number, nr, args...) \ - internal_syscall##nr (MOVE32 "\t%0, %2\n\t", \ - "r" (__s0), \ - number, err, args) + internal_syscall##nr (number, err, args) #endif /* !__mips16 */ -#define internal_syscall0(v0_init, input, number, err, dummy...) \ +#define internal_syscall0(number, err, dummy...) \ ({ \ long int _sys_result; \ \ { \ - register long int __s0 asm ("$16") __attribute__ ((unused)) \ - = (number); \ - register long int __v0 asm ("$2"); \ + register long int __v0 asm ("$2") = number; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ - : input \ + : "r" (__v0) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall1(v0_init, input, number, err, arg1) \ +#define internal_syscall1(number, err, arg1) \ ({ \ long int _sys_result; \ \ { \ long int _arg1 = (long int) (arg1); \ - register long int __s0 asm ("$16") __attribute__ ((unused)) \ - = (number); \ - register long int __v0 asm ("$2"); \ + register long int __v0 asm ("$2") = number; \ register long int __a0 asm ("$4") = _arg1; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ - : input, "r" (__a0) \ + : "r" (__v0), "r" (__a0) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall2(v0_init, input, number, err, arg1, arg2) \ +#define internal_syscall2(number, err, arg1, arg2) \ ({ \ long int _sys_result; \ \ { \ long int _arg1 = (long int) (arg1); \ long int _arg2 = (long int) (arg2); \ - register long int __s0 asm ("$16") __attribute__ ((unused)) \ - = (number); \ - register long int __v0 asm ("$2"); \ + register long int __v0 asm ("$2") = number; \ register long int __a0 asm ("$4") = _arg1; \ register long int __a1 asm ("$5") = _arg2; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ - : input, "r" (__a0), "r" (__a1) \ + : "r" (__v0), "r" (__a0), "r" (__a1) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall3(v0_init, input, number, err, \ - arg1, arg2, arg3) \ +#define internal_syscall3(number, err, arg1, arg2, arg3) \ ({ \ long int _sys_result; \ \ @@ -207,28 +174,22 @@ union __mips_syscall_return long int _arg1 = (long int) (arg1); \ long int _arg2 = (long int) (arg2); \ long int _arg3 = (long int) (arg3); \ - register long int __s0 asm ("$16") __attribute__ ((unused)) \ - = (number); \ - register long int __v0 asm ("$2"); \ + register long int __v0 asm ("$2") = number; \ register long int __a0 asm ("$4") = _arg1; \ register long int __a1 asm ("$5") = _arg2; \ register long int __a2 asm ("$6") = _arg3; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ - : input, "r" (__a0), "r" (__a1), "r" (__a2) \ + : "r" (__v0), "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall4(v0_init, input, number, err, \ - arg1, arg2, arg3, arg4) \ +#define internal_syscall4(number, err, arg1, arg2, arg3, arg4) \ ({ \ long int _sys_result; \ \ @@ -237,20 +198,15 @@ union __mips_syscall_return long int _arg2 = (long int) (arg2); \ long int _arg3 = (long int) (arg3); \ long int _arg4 = (long int) (arg4); \ - register long int __s0 asm ("$16") __attribute__ ((unused)) \ - = (number); \ - register long int __v0 asm ("$2"); \ + register long int __v0 asm ("$2") = number; \ register long int __a0 asm ("$4") = _arg1; \ register long int __a1 asm ("$5") = _arg2; \ register long int __a2 asm ("$6") = _arg3; \ register long int __a3 asm ("$7") = _arg4; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ - : input, "r" (__a0), "r" (__a1), "r" (__a2) \ + : "r" (__v0), "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ @@ -272,8 +228,7 @@ long long int __nomips16 __mips_syscall5 (long int arg1, long int arg2, long int number); libc_hidden_proto (__mips_syscall5, nomips16) -#define internal_syscall5(v0_init, input, number, err, \ - arg1, arg2, arg3, arg4, arg5) \ +#define internal_syscall5(number, err, arg1, arg2, arg3, arg4, arg5) \ ({ \ union __mips_syscall_return _sc_ret; \ _sc_ret.val = __mips_syscall5 ((long int) (arg1), \ @@ -291,7 +246,7 @@ long long int __nomips16 __mips_syscall6 (long int arg1, long int arg2, long int number); libc_hidden_proto (__mips_syscall6, nomips16) -#define internal_syscall6(v0_init, input, number, err, \ +#define internal_syscall6(number, err, \ arg1, arg2, arg3, arg4, arg5, arg6) \ ({ \ union __mips_syscall_return _sc_ret; \ @@ -312,7 +267,7 @@ long long int __nomips16 __mips_syscall7 (long int arg1, long int arg2, long int number); libc_hidden_proto (__mips_syscall7, nomips16) -#define internal_syscall7(v0_init, input, number, err, \ +#define internal_syscall7(number, err, \ arg1, arg2, arg3, arg4, arg5, arg6, arg7) \ ({ \ union __mips_syscall_return _sc_ret; \ diff --git a/sysdeps/unix/sysv/linux/mips/mips64/syscall.S b/sysdeps/unix/sysv/linux/mips/mips64/syscall.S index a9baff3c17..089524a40b 100644 --- a/sysdeps/unix/sysv/linux/mips/mips64/syscall.S +++ b/sysdeps/unix/sysv/linux/mips/mips64/syscall.S @@ -27,14 +27,9 @@ .text NESTED (syscall, SZREG, ra) - .mask 0x00010000, -SZREG + .mask 0x00000000, 0 .fmask 0x00000000, 0 - PTR_ADDIU sp, -SZREG - cfi_adjust_cfa_offset (SZREG) - REG_S s0, (sp) - cfi_rel_offset (s0, 0) - - move s0, a0 + move v0, a0 move a0, a1 /* shift arg1 - arg7. */ move a1, a2 move a2, a3 @@ -43,13 +38,8 @@ NESTED (syscall, SZREG, ra) move a5, a6 move a6, a7 - move v0, s0 /* Syscall number -> v0 */ syscall /* Do the system call. */ - REG_L s0, (sp) - cfi_restore (s0) - PTR_ADDIU sp, SZREG - cfi_adjust_cfa_offset (-SZREG) bne a3, zero, L(error) ret diff --git a/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h b/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h index 73816816d5..ae38b56f1a 100644 --- a/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h +++ b/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h @@ -68,104 +68,74 @@ typedef long int __syscall_arg_t; GIT repository as commit 96187fb0bc30cd7919759d371d810e928048249d, that first appeared in the 2.6.36 release. Since then the kernel has had code that reloads $v0 upon syscall restart and resumes right at the - SYSCALL instruction, so no special arrangement is needed anymore. - - For backwards compatibility with existing kernel binaries we support - the old convention by choosing the instruction preceding SYSCALL - carefully. This also means we have to force a 32-bit encoding of the - microMIPS MOVE instruction if one is used. */ - -#ifdef __mips_micromips -# define MOVE32 "move32" -#else -# define MOVE32 "move" -#endif + SYSCALL instruction, so no special arrangement is needed anymore. */ #undef INTERNAL_SYSCALL -#define INTERNAL_SYSCALL(name, nr, args...) \ - internal_syscall##nr ("li\t%0, %2\t\t\t# " #name "\n\t", \ - "IK" (SYS_ify (name)), \ - 0, args) +#define INTERNAL_SYSCALL(name, nr, args...) \ + internal_syscall##nr ((SYS_ify (name)), args) #undef INTERNAL_SYSCALL_NCS #define INTERNAL_SYSCALL_NCS(number, nr, args...) \ - internal_syscall##nr (MOVE32 "\t%0, %2\n\t", \ - "r" (__s0), \ - number, args) + internal_syscall##nr (number, args) -#define internal_syscall0(v0_init, input, number, dummy...) \ +#define internal_syscall0(number, dummy...) \ ({ \ long int _sys_result; \ \ { \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ - : input \ + : "r" (__v0) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall1(v0_init, input, number, arg1) \ +#define internal_syscall1(number, arg1) \ ({ \ long int _sys_result; \ \ { \ __syscall_arg_t _arg1 = ARGIFY (arg1); \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ - : input, "r" (__a0) \ + : "r" (__v0), "r" (__a0) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall2(v0_init, input, number, arg1, arg2) \ +#define internal_syscall2(number, arg1, arg2) \ ({ \ long int _sys_result; \ \ { \ __syscall_arg_t _arg1 = ARGIFY (arg1); \ __syscall_arg_t _arg2 = ARGIFY (arg2); \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a1 asm ("$5") = _arg2; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ - : input, "r" (__a0), "r" (__a1) \ + : "r" (__v0), "r" (__a0), "r" (__a1) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall3(v0_init, input, number, arg1, arg2, arg3) \ +#define internal_syscall3(number, arg1, arg2, arg3) \ ({ \ long int _sys_result; \ \ @@ -173,28 +143,22 @@ typedef long int __syscall_arg_t; __syscall_arg_t _arg1 = ARGIFY (arg1); \ __syscall_arg_t _arg2 = ARGIFY (arg2); \ __syscall_arg_t _arg3 = ARGIFY (arg3); \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a1 asm ("$5") = _arg2; \ register __syscall_arg_t __a2 asm ("$6") = _arg3; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ - : input, "r" (__a0), "r" (__a1), "r" (__a2) \ + : "r" (__v0), "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall4(v0_init, input, number, arg1, arg2, arg3, \ - arg4) \ +#define internal_syscall4(number, arg1, arg2, arg3, arg4) \ ({ \ long int _sys_result; \ \ @@ -203,28 +167,22 @@ typedef long int __syscall_arg_t; __syscall_arg_t _arg2 = ARGIFY (arg2); \ __syscall_arg_t _arg3 = ARGIFY (arg3); \ __syscall_arg_t _arg4 = ARGIFY (arg4); \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a1 asm ("$5") = _arg2; \ register __syscall_arg_t __a2 asm ("$6") = _arg3; \ register __syscall_arg_t __a3 asm ("$7") = _arg4; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ - : input, "r" (__a0), "r" (__a1), "r" (__a2) \ + : "r" (__v0), "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall5(v0_init, input, number, arg1, arg2, arg3, \ - arg4, arg5) \ +#define internal_syscall5(number, arg1, arg2, arg3, arg4, arg5) \ ({ \ long int _sys_result; \ \ @@ -234,29 +192,23 @@ typedef long int __syscall_arg_t; __syscall_arg_t _arg3 = ARGIFY (arg3); \ __syscall_arg_t _arg4 = ARGIFY (arg4); \ __syscall_arg_t _arg5 = ARGIFY (arg5); \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a1 asm ("$5") = _arg2; \ register __syscall_arg_t __a2 asm ("$6") = _arg3; \ register __syscall_arg_t __a3 asm ("$7") = _arg4; \ register __syscall_arg_t __a4 asm ("$8") = _arg5; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ - : input, "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4) \ + : "r" (__v0), "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \ } \ _sys_result; \ }) -#define internal_syscall6(v0_init, input, number, arg1, arg2, arg3, \ - arg4, arg5, arg6) \ +#define internal_syscall6(number, arg1, arg2, arg3, arg4, arg5, arg6) \ ({ \ long int _sys_result; \ \ @@ -267,9 +219,7 @@ typedef long int __syscall_arg_t; __syscall_arg_t _arg4 = ARGIFY (arg4); \ __syscall_arg_t _arg5 = ARGIFY (arg5); \ __syscall_arg_t _arg6 = ARGIFY (arg6); \ - register __syscall_arg_t __s0 asm ("$16") __attribute__ ((unused))\ - = (number); \ - register __syscall_arg_t __v0 asm ("$2"); \ + register __syscall_arg_t __v0 asm ("$2") = number; \ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a1 asm ("$5") = _arg2; \ register __syscall_arg_t __a2 asm ("$6") = _arg3; \ @@ -277,12 +227,9 @@ typedef long int __syscall_arg_t; register __syscall_arg_t __a4 asm ("$8") = _arg5; \ register __syscall_arg_t __a5 asm ("$9") = _arg6; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ - v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ - : input, "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), \ + : "r" (__v0), "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), \ "r" (__a5) \ : __SYSCALL_CLOBBERS); \ _sys_result = __a3 != 0 ? -__v0 : __v0; \