From patchwork Fri Jan 19 13:18:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 25453 Received: (qmail 59505 invoked by alias); 19 Jan 2018 13:18:15 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 58968 invoked by uid 89); 19 Jan 2018 13:18:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR03-DB5-obe.outbound.protection.outlook.com From: Wilco Dijkstra To: Szabolcs Nagy , "libc-alpha@sourceware.org" CC: nd Subject: Re: [PATCH][AArch64] Use builtins for fpcr/fpsr Date: Fri, 19 Jan 2018 13:18:08 +0000 Message-ID: References: , <5A60A7BF.6090000@arm.com> In-Reply-To: <5A60A7BF.6090000@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB6PR0802MB2485; 7:99rv1PH0ep1XMl4UKUMGaC33yLj5l96H8MiF4wChqYHgkuqU9v/t1WkKGm57wUSHo+rOOrKxd976HCkWSwkUMG1hzMoTGl/V46mMabr/N661WlZBli13CodVLoV+rNo7qW9SJsrXdq61kPx3x61ExmlC7uvYOAyzpNbWmvGvKdMtpbD0YOYXvUVH0Lm7EDoU/+OPeuEqFjXY0X+1ZLTKVctMzyK2Whti9JpdOIn7R9iznxJTTZ5txthVxiEWwoNE x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: d6b321c9-3337-4b66-0ea2-08d55f3f1500 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(2017052603307)(7153060)(7193020); SRVR:DB6PR0802MB2485; x-ms-traffictypediagnostic: DB6PR0802MB2485: nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040470)(2401047)(5005006)(8121501046)(93006095)(93001095)(3002001)(3231023)(2400077)(944501161)(10201501046)(6055026)(6041268)(20161123564045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123558120)(6072148)(201708071742011); SRVR:DB6PR0802MB2485; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:DB6PR0802MB2485; x-forefront-prvs: 0557CBAD84 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39380400002)(376002)(396003)(39860400002)(366004)(346002)(189003)(199004)(377424004)(54534003)(2950100002)(106356001)(26005)(99286004)(2501003)(2906002)(3846002)(229853002)(6436002)(55016002)(105586002)(4326008)(3660700001)(9686003)(8936002)(53936002)(6116002)(5250100002)(8676002)(81166006)(316002)(68736007)(76176011)(6506007)(72206003)(110136005)(66066001)(5660300001)(305945005)(3280700002)(2900100001)(14454004)(33656002)(86362001)(6246003)(81156014)(97736004)(478600001)(575784001)(102836004)(25786009)(7736002)(7696005)(74316002); DIR:OUT; SFP:1101; SCL:1; SRVR:DB6PR0802MB2485; H:DB6PR0801MB2053.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: o8FeFu6bDgQudkbqx/MXaX8q7lI3BE2LNKw9yJIWZlLGU171Aq4r1U8dtyLpQMwziAOxnD73RDLJn2jvo6mGPQ== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6b321c9-3337-4b66-0ea2-08d55f3f1500 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Jan 2018 13:18:08.1759 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0802MB2485 Szabolcs Nagy wrote: > this will have to wait for the next release, but please > increase the gcc prereq to 6.0 because i see ice on gcc-5: aarch64-none-linux-gnu-gcc ../sysdeps/aarch64/fpu/fesetenv.c -c [..] ../sysdeps/aarch64/fpu/fesetenv.c: In function '__fesetenv': ../sysdeps/aarch64/fpu/fesetenv.c:75:1: error: unrecognizable insn:  }  ^ (insn 23 22 4 6 (unspec_volatile [             (mem:SI (plus:DI (reg/v/f:DI 85 [ envp ])                     (const_int 4 [0x4])) [2 envp_8(D)->__fpsr+0 S4 A32])         ] UNSPECV_SET_FPSR) ../sysdeps/aarch64/fpu/fesetenv.c:41 -1      (nil)) ../sysdeps/aarch64/fpu/fesetenv.c:75:1: internal compiler error: in extract_insn, at recog.c:2343 Looks like it's merging a MEM into a register operand. Since GCC5 is no longer supported I've updated it to GCC6: Since GCC has support for accessing FPSR/FPCR, use them when possible so that the asm instructions can be removed eventually. Although GCC 5 supports the builtins, it has an optimization bug, so use them from GCC 6 onwards. GLIBC build and test OK. ChangeLog: 2018-01-19 Wilco Dijkstra * sysdeps/aarch64/fpu/fpu_control.h: Use builtins for accessing FPCR/FPSR. diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 570e3dca78adbbccdc21ca879c582e1e09196f2d..d0cc5afc9faf42249a45b7f6b24a374f944998fd 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -21,17 +21,24 @@ /* Macros for accessing the FPCR and FPSR. */ -#define _FPU_GETCW(fpcr) \ +#if __GNUC_PREREQ (6,0) +# define _FPU_GETCW(fpcr) (fpcr = __builtin_aarch64_get_fpcr ()) +# define _FPU_SETCW(fpcr) __builtin_aarch64_set_fpcr (fpcr) +# define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) +# define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) +#else +# define _FPU_GETCW(fpcr) \ __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) -#define _FPU_SETCW(fpcr) \ +# define _FPU_SETCW(fpcr) \ __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) -#define _FPU_GETFPSR(fpsr) \ +# define _FPU_GETFPSR(fpsr) \ __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr)) -#define _FPU_SETFPSR(fpsr) \ +# define _FPU_SETFPSR(fpsr) \ __asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr)) +#endif /* Reserved bits should be preserved when modifying register contents. These two masks indicate which bits in each of FPCR and