From patchwork Thu Jun 30 16:02:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 13523 Received: (qmail 33138 invoked by alias); 30 Jun 2016 16:02:40 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 33124 invoked by uid 89); 30 Jun 2016 16:02:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=91137, yyy, 31PM, 31pm X-Spam-User: qpsmtpd, 2 recipients X-HELO: mail-qk0-f175.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=q1XVomqiuF/csKcZJZmXd7pG0wOK9jLBvPfd8i9mXJk=; b=WP3zXIGR3+ocJWnnt030RpSNsulzzd5DkAdMdhKUNVCKm5dq+dV4KgwGovFe1wqSTS 9XR3erN/R/vE2whoEB4XpF7PdSFK0gP0x2Qi0igDTPeGVZfjHiQAMx5rlUHVW/JCy3Zz 20RAxWXVYKnVh+tiO+Qp6WWloAJSPgXnAkJrP0Xwqra+5NQ/T2l3rVg75UVGCfQWeve5 cRqlt+/LaFJoSv6Ud0Q7m2EnaMeUhmYMMOZKJff6T9cJRkbts+mdp3hgZQb6Tb+9vdsF snHaMsux2lI/f9SDSFMkiMcymziXIfFV95lPeZUDdOHQif6HKgtXygFvftWpLD3CYIPV 5oAA== X-Gm-Message-State: ALyK8tKMVqYfAf2HrtBfW2Hg95/SbvQJqpjLBBdhzjbg8A1Mf4QcIvHxu/QdCg1IvxQh1GFypPMUEI2+Gaiwyg== X-Received: by 10.55.214.135 with SMTP id p7mr20194427qkl.195.1467302543303; Thu, 30 Jun 2016 09:02:23 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20160630143534.GD7564@devel.intra.reserved-bit.com> References: <20160630030947.GD3824@devel.intra.reserved-bit.com> <20160630034351.GE3824@devel.intra.reserved-bit.com> <20160630114416.GA7564@devel.intra.reserved-bit.com> <20160630125142.GB7564@devel.intra.reserved-bit.com> <20160630142318.GC7564@devel.intra.reserved-bit.com> <20160630143534.GD7564@devel.intra.reserved-bit.com> From: "H.J. Lu" Date: Thu, 30 Jun 2016 09:02:22 -0700 Message-ID: Subject: Re: PATCH: Check GLIBC_IFUNC to enable/disable ifunc features To: Siddhesh Poyarekar Cc: Andreas Schwab , "Carlos O'Donell" , GNU C Library On Thu, Jun 30, 2016 at 7:35 AM, Siddhesh Poyarekar wrote: > On Thu, Jun 30, 2016 at 04:33:31PM +0200, Andreas Schwab wrote: >> I think it is useful to be able to selectively disable some features, by >> prefixing it with - for example. > > Yeah, that sounds good too. > This patch implements it. From ef5d9973fcfbf789cdd32b11fafe54e7c1d47d7c Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Mon, 27 Jun 2016 15:13:50 -0700 Subject: [PATCH] Add GLIBC_IFUNC to control IFUNC selection The current IFUNC selection is based on microbenchmarks in glibc. It should give the best performance for most workloads. But other choices may have better performance for a particular workload or on the hardware which wasn't available at the selection was made. The environment variable, GLIBC_IFUNC=-xxx,yyy,-zzz...., can be used to enable CPU/ARCH feature yyy, disable CPU/ARCH feature yyy and zzz, where the feature name is case-sensitive and has to match the ones in cpu-features.h. It can be used by glibc developers to override the IFUNC selection to tune for a new processor or improve performance for a particular workload. It isn't intended for normal end users. Since all CPU/ARCH features are hardware optimizations without security implication, except for Prefer_MAP_32BIT_EXEC, which can only be disabled, we check GLIBC_IFUNC for programs, including set*id ones. NOTE: the IFUNC selection may change over time. Please check all multiarch implementations when experimenting. * sysdeps/i386/dl-machine.h (dl_platform_init): Pass the array of environment strings to init_cpu_features. * sysdeps/x86/libc-start.c (__libc_start_main): Likewise. * sysdeps/x86/cpu-features.c (equal): New function. (CHECK_GLIBC_IFUNC_CPU_OFF): New macro. (CHECK_GLIBC_IFUNC_ARCH_OFF): Likewise. (CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH): Likewise. (CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH): Likewise. (init_cpu_features): Updated to take the array of environment strings. Process GLIBC_IFUNC environment variable. --- sysdeps/i386/dl-machine.h | 3 +- sysdeps/x86/cpu-features.c | 303 +++++++++++++++++++++++++++++++++++++++++++- sysdeps/x86/libc-start.c | 2 +- sysdeps/x86_64/dl-machine.h | 3 +- 4 files changed, 307 insertions(+), 4 deletions(-) diff --git a/sysdeps/i386/dl-machine.h b/sysdeps/i386/dl-machine.h index 4e3968a..7584931 100644 --- a/sysdeps/i386/dl-machine.h +++ b/sysdeps/i386/dl-machine.h @@ -240,7 +240,8 @@ dl_platform_init (void) #ifdef SHARED /* init_cpu_features has been called early from __libc_start_main in static executable. */ - init_cpu_features (&GLRO(dl_x86_cpu_features)); + init_cpu_features (&GLRO(dl_x86_cpu_features), + &_dl_argv[_dl_argc + 1]); #endif } diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 9ce4b49..2d7a09b 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -91,8 +91,137 @@ get_common_indeces (struct cpu_features *cpu_features, } } +#ifdef __x86_64__ +typedef long long op_t; +#else +typedef int op_t; +#endif + +/* Return true if the first LEN bytes of strings A and B are the same + where LEN != 0. We can't use string/memory functions because they + trigger an ifunc resolve loop. */ + +static bool +equal (const char *a, const char *b, size_t len) +{ + size_t op_len = len % sizeof (op_t); + if (op_len) + { + switch (op_len) + { + case 1: + if (*(char *) a != *(char *) b) + return false; + break; + case 2: + if (*(short *) a != *(short *) b) + return false; + break; + case 3: + if (*(short *) a != *(short *) b + || *(char *) (a + 2) != *(char *) (b + 2)) + return false; + break; +#ifdef __x86_64__ + case 4: + if (*(int *) a != *(int *) b) + return false; + break; + default: + if (*(int *) a != *(int *) b + || *(int *) (a + op_len - 4) != *(int *) (b + op_len - 4)) + return false; + break; +#else + default: + break; +#endif + } + /* Align length to size of op_t. */ + len -= op_len; + if (len == 0) + return true; + a += op_len; + b += op_len; + } + + /* Compare one op_t at a time. */ + do + { + if (*(op_t *) a != *(op_t *) b) + return false; + len -= sizeof (op_t); + if (len == 0) + return true; + a += sizeof (op_t); + b += sizeof (op_t); + } + while (1); +} + +/* Disable a CPU feature NAME. We don't enable a CPU feature which isn't + availble. */ +#define CHECK_GLIBC_IFUNC_CPU_OFF(name) \ + if (equal (n, #name, sizeof (#name) - 1)) \ + { \ + cpu_features->cpuid[index_cpu_##name].reg_##name \ + &= ~bit_cpu_##name; \ + break; \ + } + +/* Disable an ARCH feature NAME. We don't enable an ARCH feature which + isn't availble or has security implication. */ +#define CHECK_GLIBC_IFUNC_ARCH_OFF(name) \ + if (equal (n, #name, sizeof (#name) - 1)) \ + { \ + cpu_features->feature[index_arch_##name] \ + &= ~bit_arch_##name; \ + break; \ + } + +/* Enable/disable an ARCH feature NAME. */ +#define CHECK_GLIBC_IFUNC_ARCH_BOTH(name, disable) \ + if (equal (n, #name, sizeof (#name) - 1)) \ + { \ + if (disable) \ + cpu_features->feature[index_arch_##name] \ + &= ~bit_arch_##name; \ + else \ + cpu_features->feature[index_arch_##name] \ + |= bit_arch_##name; \ + break; \ + } + +/* Enable/disable an ARCH feature NAME. Enable an ARCH feature only + if the ARCH feature NEED is also enabled. */ +#define CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH(name, need, disable) \ + if (equal (n, #name, sizeof (#name) - 1)) \ + { \ + if (disable) \ + cpu_features->feature[index_arch_##name] \ + &= ~bit_arch_##name; \ + else if (CPU_FEATURES_ARCH_P (cpu_features, need)) \ + cpu_features->feature[index_arch_##name] \ + |= bit_arch_##name; \ + break; \ + } + +/* Enable/disable an ARCH feature NAME. Enable an ARCH feature only + if the CPU feature NEED is also enabled. */ +#define CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH(name, need, disable) \ + if (equal (n, #name, sizeof (#name) - 1)) \ + { \ + if (disable) \ + cpu_features->feature[index_arch_##name] \ + &= ~bit_arch_##name; \ + else if (CPU_FEATURES_CPU_P (cpu_features, need)) \ + cpu_features->feature[index_arch_##name] \ + |= bit_arch_##name; \ + break; \ + } + static inline void -init_cpu_features (struct cpu_features *cpu_features) +init_cpu_features (struct cpu_features *cpu_features, char **env) { unsigned int ebx, ecx, edx; unsigned int family = 0; @@ -268,4 +397,176 @@ no_cpuid: cpu_features->family = family; cpu_features->model = model; cpu_features->kind = kind; + + /* The current IFUNC selection is based on microbenchmarks in glibc. + It should give the best performance for most workloads. But other + choices may have better performance for a particular workload or on + the hardware which wasn't available when the selection was made. + The environment variable, GLIBC_IFUNC=-xxx,yyy,-zzz...., can be + used to enable CPU/ARCH feature yyy, disable CPU/ARCH feature yyy + and zzz, where the feature name is case-sensitive and has to match + the ones in cpu-features.h. It can be used by glibc developers to + tune for a new processor or override the IFUNC selection to improve + performance for a particular workload. + + Since all CPU/ARCH features are hardware optimizations without + security implication, except for Prefer_MAP_32BIT_EXEC, which can + only be disabled, we check GLIBC_IFUNC for programs, including + set*id ones. + + NOTE: the IFUNC selection may change over time. Please check all + multiarch implementations when experimenting. */ + + while (*env != NULL) + { + const char *p, *end; + size_t len = sizeof ("GLIBC_IFUNC="); + + end = *env; + for (p = end; *p != '\0'; p++) + if (--len == 0 && equal (end, "GLIBC_IFUNC=", 12)) + { + len = strlen (p); + end = p + len; + do + { + const char *c, *n; + bool disable; + size_t nl; + + for (c = p; *c != ','; c++) + if (c >= end) + break; + + len = c - p; + disable = *p == '-'; + if (disable) + { + n = p + 1; + nl = len - 1; + } + else + { + n = p; + nl = len; + } + switch (nl) + { + default: + break; + case 3: + if (disable) + { + CHECK_GLIBC_IFUNC_CPU_OFF (AVX); + CHECK_GLIBC_IFUNC_CPU_OFF (CX8); + CHECK_GLIBC_IFUNC_CPU_OFF (FMA); + CHECK_GLIBC_IFUNC_CPU_OFF (HTT); + CHECK_GLIBC_IFUNC_CPU_OFF (RTM); + } + break; + case 4: + if (disable) + { + CHECK_GLIBC_IFUNC_CPU_OFF (AVX2); + CHECK_GLIBC_IFUNC_CPU_OFF (CMOV); + CHECK_GLIBC_IFUNC_CPU_OFF (ERMS); + CHECK_GLIBC_IFUNC_CPU_OFF (FMA4); + CHECK_GLIBC_IFUNC_CPU_OFF (SSE2); + CHECK_GLIBC_IFUNC_ARCH_OFF (I586); + CHECK_GLIBC_IFUNC_ARCH_OFF (I686); + } + break; + case 5: + if (disable) + { + CHECK_GLIBC_IFUNC_CPU_OFF (SSSE3); + } + break; + case 6: + if (disable) + { + CHECK_GLIBC_IFUNC_CPU_OFF (SSE4_1); + CHECK_GLIBC_IFUNC_CPU_OFF (SSE4_2); + } + break; + case 7: + if (disable) + { + CHECK_GLIBC_IFUNC_CPU_OFF (AVX512F); + CHECK_GLIBC_IFUNC_CPU_OFF (OSXSAVE); + } + break; + case 8: + if (disable) + { + CHECK_GLIBC_IFUNC_CPU_OFF (AVX512DQ); + CHECK_GLIBC_IFUNC_CPU_OFF (POPCOUNT); + } + CHECK_GLIBC_IFUNC_ARCH_BOTH (Slow_BSF, disable); + break; + case 10: + if (disable) + { + CHECK_GLIBC_IFUNC_ARCH_OFF (AVX_Usable); + CHECK_GLIBC_IFUNC_ARCH_OFF (FMA_Usable); + } + break; + case 11: + if (disable) + { + CHECK_GLIBC_IFUNC_ARCH_OFF (AVX2_Usable); + CHECK_GLIBC_IFUNC_ARCH_OFF (FMA4_Usable); + } + CHECK_GLIBC_IFUNC_ARCH_BOTH (Prefer_ERMS, disable); + CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (Slow_SSE4_2, + SSE4_2, + disable); + break; + case 13: + if (disable) + { + CHECK_GLIBC_IFUNC_ARCH_OFF (AVX512F_Usable); + } + CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH + (AVX_Fast_Unaligned_Load, AVX_Usable, disable); + break; + case 15: + if (disable) + { + CHECK_GLIBC_IFUNC_ARCH_OFF (AVX512DQ_Usable); + } + CHECK_GLIBC_IFUNC_ARCH_BOTH (Fast_Rep_String, disable); + break; + case 18: + CHECK_GLIBC_IFUNC_ARCH_BOTH (Fast_Copy_Backward, + disable); + break; + case 19: + CHECK_GLIBC_IFUNC_ARCH_BOTH (Fast_Unaligned_Load, + disable); + CHECK_GLIBC_IFUNC_ARCH_BOTH (Fast_Unaligned_Copy, + disable); + break; + case 20: + CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH + (Prefer_No_VZEROUPPER, AVX_Usable, disable); + break; + case 21: + if (disable) + { + CHECK_GLIBC_IFUNC_ARCH_OFF (Prefer_MAP_32BIT_EXEC); + } + break; + case 26: + CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH + (Prefer_PMINUB_for_stringop, SSE2, disable); + break; + } + p += len + 1; + } + while (p < end); + return; + } + env++; + } } diff --git a/sysdeps/x86/libc-start.c b/sysdeps/x86/libc-start.c index 3b5ea6e..7dec1ca 100644 --- a/sysdeps/x86/libc-start.c +++ b/sysdeps/x86/libc-start.c @@ -34,7 +34,7 @@ __libc_start_main (int (*main) (int, char **, char ** MAIN_AUXVEC_DECL), void (*fini) (void), void (*rtld_fini) (void), void *stack_end) { - init_cpu_features (&_dl_x86_cpu_features); + init_cpu_features (&_dl_x86_cpu_features, &argv[argc + 1]); return generic_start_main (main, argc, argv, init, fini, rtld_fini, stack_end); } diff --git a/sysdeps/x86_64/dl-machine.h b/sysdeps/x86_64/dl-machine.h index ed0c1a8..071a2e1 100644 --- a/sysdeps/x86_64/dl-machine.h +++ b/sysdeps/x86_64/dl-machine.h @@ -227,7 +227,8 @@ dl_platform_init (void) #ifdef SHARED /* init_cpu_features has been called early from __libc_start_main in static executable. */ - init_cpu_features (&GLRO(dl_x86_cpu_features)); + init_cpu_features (&GLRO(dl_x86_cpu_features), + &_dl_argv[_dl_argc + 1]); #endif } -- 2.7.4