From patchwork Thu Dec 15 15:37:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Senkevich X-Patchwork-Id: 18484 Received: (qmail 5844 invoked by alias); 15 Dec 2016 15:38:37 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 5820 invoked by uid 89); 15 Dec 2016 15:38:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_PASS, URIBL_RED autolearn=ham version=3.3.2 spammy=H*r:sk:mail-ua, HX-HELO:sk:mail-ua, Hx-spam-relays-external:sk:mail-ua, H*RU:sk:mail-ua X-HELO: mail-ua0-f172.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=bJe56szfR6ga3jIY8RPisg1v3E4yyPf0NwKIIQt4oFc=; b=GxywU6RnmdhnLfsX1fRvx0w0nhlBcZGsZJXoXg95RC7rvmJukypQrC1TWbtKFTXR9j kdUcF0zAv4L8HqwRbjVE88xd3+G7sspdqITmGmlUySTwiPGSaoUyYPDl/pidIp17Wt+f +TSiIXc0IUSCvD3FW9sC5yHaJz1afgK2JWYdWuTjRlgwEf0GCpLXl2fjEfNkATx0lhAW mSaADgmwer08d+ZbjYYY9PBGNyphs7T9FVKQ9PclUJ2ISnD+ndf/4kACWdRF0jKEKkIS FYY6YeiecoBszJEyNctK82333Xcz8fRzy0a8dLy8rLZ+YbLO7+L05TEgbDT7KsxMaQIQ ZtaQ== X-Gm-Message-State: AIkVDXI0TpJBRLHV9Uh55wP9gOMWASRAmwIBp+VUh/yqC9OYsyy7T9qXozGZvjHtRYxynOS/u1sI/V5G6HqgLw== X-Received: by 10.176.8.83 with SMTP id b19mr1259147uaf.33.1481816304929; Thu, 15 Dec 2016 07:38:24 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: From: Andrew Senkevich Date: Thu, 15 Dec 2016 18:37:54 +0300 Message-ID: Subject: Re: [PATCH][x86_64] Disable TSX on some Haswell processors To: "Carlos O'Donell" Cc: libc-alpha , Andi Kleen 2016-12-14 22:13 GMT+03:00 Carlos O'Donell : . . . . . > > Case 0x3f needs a comment explaining why we break out early. > >> + case 0x3f: >> + if (stepping >= 4) >> + break; Here is version with added comment and ChangeLog. Ok for commit? --- WBR, Andrew diff --git a/ChangeLog b/ChangeLog index cf798fb..ef4c3b4 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2016-12-15 Andrew Senkevich + + * sysdeps/x86/cpu-features.c (get_common_indeces): Add + stepping identification. + (init_cpu_features): Add handle of Haswell. + 2016-12-15 Joseph Myers [BZ #20947] diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index e228a76..d158402 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -22,7 +22,7 @@ static void get_common_indeces (struct cpu_features *cpu_features, unsigned int *family, unsigned int *model, - unsigned int *extended_model) + unsigned int *extended_model, unsigned int *stepping) { if (family) { @@ -34,6 +34,7 @@ get_common_indeces (struct cpu_features *cpu_features, *family = (eax >> 8) & 0x0f; *model = (eax >> 4) & 0x0f; *extended_model = (eax >> 12) & 0xf0; + *stepping = eax & 0x0f; if (*family == 0x0f) { *family += (eax >> 20) & 0xff; @@ -116,11 +117,12 @@ init_cpu_features (struct cpu_features *cpu_features) /* This spells out "GenuineIntel". */ if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) { - unsigned int extended_model; + unsigned int extended_model, stepping; kind = arch_kind_intel; - get_common_indeces (cpu_features, &family, &model, &extended_model); + get_common_indeces (cpu_features, &family, &model, &extended_model, + &stepping); if (family == 0x06) { @@ -201,6 +203,20 @@ init_cpu_features (struct cpu_features *cpu_features) | bit_arch_Fast_Unaligned_Copy | bit_arch_Prefer_PMINUB_for_stringop); break; + + case 0x3f: + /* Xeon E7 v3 with stepping >= 4 has working TSX. */ + if (stepping >= 4) + break; + case 0x3c: + case 0x45: + case 0x46: + /* Disable Intel TSX on Haswell processors (except Xeon E7 v3) + to avoid TSX on kernels that weren't updated with the latest + microcode package (which disables broken feature + by default). */ + cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_cpu_RTM); + break; } } @@ -227,11 +243,12 @@ init_cpu_features (struct cpu_features *cpu_features) /* This spells out "AuthenticAMD". */ else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) { - unsigned int extended_model; + unsigned int extended_model, stepping; kind = arch_kind_amd; - get_common_indeces (cpu_features, &family, &model, &extended_model); + get_common_indeces (cpu_features, &family, &model, &extended_model, + &stepping); ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx; @@ -268,7 +285,7 @@ init_cpu_features (struct cpu_features *cpu_features) else { kind = arch_kind_other; - get_common_indeces (cpu_features, NULL, NULL, NULL); + get_common_indeces (cpu_features, NULL, NULL, NULL, NULL); } /* Support i586 if CX8 is available. */