From patchwork Tue Oct 25 14:33:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Larsson X-Patchwork-Id: 16798 Received: (qmail 101415 invoked by alias); 25 Oct 2016 14:34:17 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 101402 invoked by uid 89); 25 Oct 2016 14:34:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=Riegel, riegel, apparent, HCC:D*net X-HELO: mx2.bahnhof.se X-Spam-Score: 0.67 Message-ID: <580F6D57.2000309@gaisler.com> Date: Tue, 25 Oct 2016 16:33:59 +0200 From: Andreas Larsson User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: Torvald Riegel CC: Adhemerval Zanella , GNU C Library , David Miller , "software@gaisler.com" Subject: Re: Remove sparcv8 support References: <48cdf008-b66a-d411-a07a-5a38595978b9@linaro.org> <5809D90E.1090005@gaisler.com> <1477329945.7146.95.camel@localhost.localdomain> In-Reply-To: <1477329945.7146.95.camel@localhost.localdomain> On 2016-10-24 19:25, Torvald Riegel wrote: > On Fri, 2016-10-21 at 10:59 +0200, Andreas Larsson wrote: >> On 2016-10-20 21:47, Adhemerval Zanella wrote: >>> The sparcv8 build is broken since GLIBC 2.23 due the new pthread >>> barrier implementation [1] and since then there is no thread or >>> interest on fixing it (Torvald has suggested some options on >>> 2.23 release thread). It won't help with both new pthread rdlock >>> and cond implementation, although I would expect that it relies >>> on same atomic primitive that was not present for pthread barrier. >>> >>> AFAIK, recent commercial sparc chips from Oracle all supports >>> sparcv9. The only somewhat recent sparc chip with just sparcv8 >>> support is LEON4, which I really doubt it cares for glibc support. >> >> Hi! >> >> We do care about GLIBC support for many different LEON3 and LEON4 >> systems. GLIBC support for sparcv8 is important for us and it is >> important for our customers. Both LEON3 and LEON4 are continuously used >> in new hardware designs. > > If you do care about it, it would be nice if you could (help) maintain > sparcv8 (e.g., regularly testing most recent glibc on sparcv8, at the > very least early during the freeze of each release). This ensures that > you won't get surprises such as this one, when nobody else is spending > resources on it. Yes, it is apparent that we need to keep up better to avoid problems like this. >> We are not always using the latest version of GLIBC (the latest step we >> took was to GLIBC 2.20), so unfortunately we missed this issue. We will >> look into what the extent of the missing support is. Any pointers are >> most welcome. >> >> Do you have a link to the suggested options on the 2.23 release thread? >> I dug around a bit in the archives, but did not find it. >> >> (As a side note, most of the recent LEON3 and LEON4 chips have CAS >> instruction support, but pure sparcv8 support is of course the baseline.) > > Yes, the lack of CAS is the major problem I am aware of. If the chips > you mention do support CAS, then a patch that adds support for the > CAS-based atomic operations in glibc would fix the barrier problem > (because the generic barrier should just work). The patch would also > have to add configure bits or whatever would be appropriate so that > glibc can figure out whether it is supposed to be run on a sparcv8 with > or without CAS. Perhaps not the kosher way to do it (happy to get feedback if some other method should be used), but changing sysdeps/sparc/sparc32/pthread_barrier_wait.c to: #if defined(__GCC_ATOMIC_INT_LOCK_FREE) && (__GCC_ATOMIC_INT_LOCK_FREE > 1) #include #else #error No support for pthread barriers on pre-v9 sparc. #endif and fixing missing undefs for sparc32 for sendmsg and recvmsg (sparc32 was not adjusted in commit abf29edd4a3918) made me able to cross-compile glibc 2.24 using gcc 4.9.4 and -mcpu=leon3, boot with a buildroot based system and run cross-compiled nptl/tst-barrier[1234] without failures. I will continue with building and run the rest of the test framework, especially tst-barrier5. Best regards, Andreas Larsson --- a/sysdeps/unix/sysv/linux/sparc/kernel-features.h +++ b/sysdeps/unix/sysv/linux/sparc/kernel-features.h @@ -32,8 +32,10 @@ #include_next /* 32-bit SPARC kernels do not support - futex_atomic_cmpxchg_inatomic. */ + futex_atomic_cmpxchg_inatomic or sendmsg/recvmsg. */ #if !defined __arch64__ && !defined __sparc_v9__ # undef __ASSUME_REQUEUE_PI # undef __ASSUME_SET_ROBUST_LIST +# undef __ASSUME_SENDMSG_SYSCALL +# undef __ASSUME_RECVMSG_SYSCALL #endif