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Wed, 18 Oct 2023 13:08:44 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 39ID8fmq12386950 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 18 Oct 2023 13:08:41 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9C15220040; Wed, 18 Oct 2023 13:08:41 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7F3A720043; Wed, 18 Oct 2023 13:08:41 +0000 (GMT) Received: from a35lp69.lnxne.boe (unknown [9.152.108.100]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 18 Oct 2023 13:08:41 +0000 (GMT) From: Stefan Liebler To: libc-alpha@sourceware.org Cc: Stefan Liebler Subject: [PATCH] s390: Fix undefined behaviour in feenableexcept, fedisableexcept [BZ #30960] Date: Wed, 18 Oct 2023 15:08:40 +0200 Message-ID: <20231018130840.3249206-1-stli@linux.ibm.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: v_qinSkIY2OFP4kynatwWHVb6tVj1Rsu X-Proofpoint-ORIG-GUID: v_qinSkIY2OFP4kynatwWHVb6tVj1Rsu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-18_11,2023-10-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=652 impostorscore=0 mlxscore=0 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310180109 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org If feenableexcept or fedisableexcept gets excepts=FE_INVALID=0x80 as input, we have a signed left shift: 0x80 << 24 which is not representable as int and thus is undefined behaviour according to C standard. This patch casts excepts as unsigned int before shifting, which is defined. For me, the observed undefined behaviour is that the shift is done with "unsigned"-instructions, which is exactly what we want. Furthermore, I don't get any exception-flags. After the fix, the code is using the same instruction sequence as before. --- sysdeps/s390/fpu/fedisblxcpt.c | 3 ++- sysdeps/s390/fpu/feenablxcpt.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/sysdeps/s390/fpu/fedisblxcpt.c b/sysdeps/s390/fpu/fedisblxcpt.c index 728f103f43..84b2c5e64a 100644 --- a/sysdeps/s390/fpu/fedisblxcpt.c +++ b/sysdeps/s390/fpu/fedisblxcpt.c @@ -26,7 +26,8 @@ fedisableexcept (int excepts) _FPU_GETCW (temp); old_exc = (temp & FPC_EXCEPTION_MASK) >> FPC_EXCEPTION_MASK_SHIFT; - new_flags = (temp & (~((excepts & FE_ALL_EXCEPT) << FPC_EXCEPTION_MASK_SHIFT))); + new_flags = (temp & (~(((unsigned int) excepts & FE_ALL_EXCEPT) + << FPC_EXCEPTION_MASK_SHIFT))); _FPU_SETCW (new_flags); return old_exc; diff --git a/sysdeps/s390/fpu/feenablxcpt.c b/sysdeps/s390/fpu/feenablxcpt.c index 0807e610a2..76d25316f4 100644 --- a/sysdeps/s390/fpu/feenablxcpt.c +++ b/sysdeps/s390/fpu/feenablxcpt.c @@ -26,7 +26,8 @@ feenableexcept (int excepts) _FPU_GETCW (temp); old_exc = (temp & FPC_EXCEPTION_MASK) >> FPC_EXCEPTION_MASK_SHIFT; - new_flags = (temp | ((excepts & FE_ALL_EXCEPT) << FPC_EXCEPTION_MASK_SHIFT)); + new_flags = (temp | ((unsigned int) (excepts & FE_ALL_EXCEPT) + << FPC_EXCEPTION_MASK_SHIFT)); _FPU_SETCW (new_flags); return old_exc;