From patchwork Mon Apr 24 05:03:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 68204 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55B6A3858C50 for ; Mon, 24 Apr 2023 05:03:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 55B6A3858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1682312638; bh=t1+BhM+WYijeLdG+6fQdnl8pQeeVViSb6sRIvjzF8l0=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Zqvnct49bXeUru7cJoJUybE1BWblpiHt9P2S7OW63Y43ebZ9M8mwSGhkyN8TPuUPn B7jc7/nL94o3++CQUbbaQuGSaG74p8KlZbnINWZs6z2iqqwvy6uVaaYooOcNcgZMn9 rqj53EXb3XoMPiVAiwXifsbf8CDFbJIqp7Vlbyjc= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 879A13858D32 for ; Mon, 24 Apr 2023 05:03:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 879A13858D32 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50847469a7fso5690556a12.0 for ; Sun, 23 Apr 2023 22:03:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682312611; x=1684904611; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=t1+BhM+WYijeLdG+6fQdnl8pQeeVViSb6sRIvjzF8l0=; b=eG9gL5Ll1WKu+8/7XbUulJO9CubZK+eHwaDu/aJIL5fn0FbYelXqe26Qbpo4UbNflV OwY73opxMbohVMZXDw47KGJVjIWjqcJlyve+UBsAh0moQIHbOvn72jSS3bnPk/tTlkla Smbwok1GM/ZiccNnmiAJtWr6esSUSSQb5iLy6JHwYbUWfm+FgjtkBm6uqpwmjmxXkqBi 5dwKvbFfNfFleD1msEUz5QsesGHa+t8OiF5UCI9DWPMCA2/xQnGdqMhlOpPdrleHdecM 11kGanqzJgo+JwXq2P7ywk6CaJ+LHOUyII6v2WBNOo1DqwiYORKLuY4DCTjC3oxGFKVD /86g== X-Gm-Message-State: AAQBX9eJKQSS7UpaLmUMY9H93jG+WcSGXUF/8+6J2I50mejGD0pMFlkb HryT/oqsPeiouv2kPbOuAQXZIurfis4= X-Google-Smtp-Source: AKy350Z7rhVtMqdHp5TR/1vsUzm22WPTQK5pHWvolBKFICAhPeBpFYDjXZ0E4GyP1p5uQ/o7Zng7FA== X-Received: by 2002:aa7:c2c5:0:b0:506:943a:6a5f with SMTP id m5-20020aa7c2c5000000b00506943a6a5fmr10037914edp.36.1682312610544; Sun, 23 Apr 2023 22:03:30 -0700 (PDT) Received: from noahgold-desk.intel.com ([192.55.55.52]) by smtp.gmail.com with ESMTPSA id l18-20020a056402345200b00506935b7c75sm4206449edc.69.2023.04.23.22.03.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:03:30 -0700 (PDT) To: libc-alpha@sourceware.org Cc: goldstein.w.n@gmail.com, hjl.tools@gmail.com, carlos@systemhalted.org Subject: [PATCH v1] x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 2` Date: Mon, 24 Apr 2023 00:03:29 -0500 Message-Id: <20230424050329.1501348-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Current `non_temporal_threshold` set to roughly '3/4 * sizeof_L3 / ncores_per_socket'. This patch updates that value to roughly 'sizeof_L3 / 2` The original value (specifically dividing the `ncores_per_socket`) was done to limit the amount of other threads' data a `memcpy`/`memset` could evict. Dividing by 'ncores_per_socket', however leads to exceedingly low non-temporal threshholds and leads to using non-temporal stores in cases where `rep movsb` is multiple times faster. Furthermore, non-temporal stores are written directly to disk so using it at a size much smaller than L3 can place soon to be accessed data much further away than it otherwise could be. As well, modern machines are able to detect streaming patterns (especially if `rep movsb` is used) and provide LRU hints to the memory subsystem. This in affect caps the total amount of eviction at 1/cache_assosiativity, far below meaningfully thrashing the entire cache. As best I can tell, the benchmarks that lead this small threshold where done comparing non-temporal stores versus standard cacheable stores. A better comparison (linked below) is to be `rep movsb` which, on the measure systems, is nearly 2x faster than non-temporal stores at the low-end of the previous threshold, and within 10% for over 100MB copies (well past even the current threshold). In cases with a low number of threads competing for bandwidth, `rep movsb` is ~2x faster up to `sizeof_L3`. Benchmarks comparing non-temporal stores, rep movsb, and cacheable stores where done using: https://github.com/goldsteinn/memcpy-nt-benchmarks Sheets results (also available in pdf on the github): https://docs.google.com/spreadsheets/d/e/2PACX-1vS183r0rW_jRX6tG_E90m9qVuFiMbRIJvi5VAE8yYOvEOIEEc3aSNuEsrFbuXw5c3nGboxMmrupZD7K/pubhtml --- sysdeps/x86/dl-cacheinfo.h | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index ec88945b39..f25309dbc8 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -604,20 +604,11 @@ intel_bug_no_cache_info: = ((cpu_features->features[CPUID_INDEX_1].cpuid.ebx >> 16) & 0xff); } - - /* Cap usage of highest cache level to the number of supported - threads. */ - if (shared > 0 && threads > 0) - shared /= threads; } /* Account for non-inclusive L2 and L3 caches. */ if (!inclusive_cache) - { - if (threads_l2 > 0) - core /= threads_l2; - shared += core; - } + shared += core; *shared_ptr = shared; *threads_ptr = threads; @@ -730,17 +721,19 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) cpu_features->level3_cache_linesize = level3_cache_linesize; cpu_features->level4_cache_size = level4_cache_size; - /* The default setting for the non_temporal threshold is 3/4 of one - thread's share of the chip's cache. For most Intel and AMD processors - with an initial release date between 2017 and 2020, a thread's typical - share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4 - threshold leaves 125 KBytes to 500 KBytes of the thread's data - in cache after a maximum temporal copy, which will maintain - in cache a reasonable portion of the thread's stack and other - active data. If the threshold is set higher than one thread's - share of the cache, it has a substantial risk of negatively - impacting the performance of other threads running on the chip. */ - unsigned long int non_temporal_threshold = shared * 3 / 4; + /* The default setting for the non_temporal threshold is 1/2 of size + of chip's cache. For most Intel and AMD processors with an + initial release date between 2017 and 2023, a thread's typical + share of the cache is from 18-64MB. Using the 1/2 L3 is meant to + estimate the point where non-temporal stores begin outcompeting + other methods. As well the point where the fact that non-temporal + stores are forced back to disk would already occured to the + majority of the lines in the copy. Note, concerns about the + entire L3 cache being evicted by the copy are mostly alleviated + by the fact that modern HW detects streaming patterns and + provides proper LRU hints so that the the maximum thrashing + capped at 1/assosiativity. */ + unsigned long int non_temporal_threshold = shared / 2; /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best if that operation cannot overflow. Minimum of 0x4040 (16448) because the