From patchwork Mon Mar 7 15:00:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Pandey X-Patchwork-Id: 51678 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C88E3858C20 for ; Mon, 7 Mar 2022 15:46:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9C88E3858C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1646668003; bh=y37lLjjqxxUBrg1r1WJPThH+PZLzRgFPMH4VmOOqIjA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=xUcxIxnwtoxw015DXGz0M6KzwWHwU6Gxwhu+8LKKX1hEkPcnaTCjvUlbGYzlRh3z/ h3Fdqop8dSVUYUE3jeMlxHKHkHQCFzozYJUY3A/rf51JlCeNj2EeawQ1QnRNNtqVI9 2sX9pY0aiHdytT6r7cwyRRikFaTrQmGtnMpi5TBQ= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 2CB563858000 for ; Mon, 7 Mar 2022 15:02:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2CB563858000 X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="251983656" X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="251983656" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 07:02:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="610639859" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga004.fm.intel.com with ESMTP; 07 Mar 2022 07:02:02 -0800 Received: from gskx-1.sc.intel.com (gskx-1.sc.intel.com [172.25.149.211]) by scymds01.sc.intel.com with ESMTP id 227F21de016772; Mon, 7 Mar 2022 07:02:02 -0800 To: libc-alpha@sourceware.org Subject: [PATCH 006/126] x86_64: Fix svml_d_acos8_core_avx512.S code formatting Date: Mon, 7 Mar 2022 07:00:01 -0800 Message-Id: <20220307150201.10590-7-skpgkp2@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220307150201.10590-1-skpgkp2@gmail.com> References: <20220307150201.10590-1-skpgkp2@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FORGED_GMAIL_RCVD, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HK_RANDOM_ENVFROM, HK_RANDOM_FROM, KAM_DMARC_NONE, KAM_DMARC_STATUS, NML_ADSP_CUSTOM_MED, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Sunil K Pandey via Libc-alpha From: Sunil Pandey Reply-To: Sunil K Pandey Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This commit contains following formatting changes 1. Instructions proceeded by a tab. 2. Instruction less than 8 characters in length have a tab between it and the first operand. 3. Instruction greater than 7 characters in length have a space between it and the first operand. 4. Tabs after `#define`d names and their value. 5. 8 space at the beginning of line replaced by tab. 6. Indent comments with code. 7. Remove redundent .text section. --- .../fpu/multiarch/svml_d_acos8_core_avx512.S | 499 +++++++++--------- 1 file changed, 249 insertions(+), 250 deletions(-) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_acos8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_acos8_core_avx512.S index 4f617ac850..f4c72c3618 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_acos8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_acos8_core_avx512.S @@ -28,280 +28,279 @@ /* Offsets for data table __svml_dacos_data_internal */ -#define SgnBit 0 -#define OneHalf 64 -#define SmallNorm 128 -#define MOne 192 -#define Two 256 -#define sqrt_coeff_1 320 -#define sqrt_coeff_2 384 -#define sqrt_coeff_3 448 -#define sqrt_coeff_4 512 -#define poly_coeff_1 576 -#define poly_coeff_2 640 -#define poly_coeff_3 704 -#define poly_coeff_4 768 -#define poly_coeff_5 832 -#define poly_coeff_6 896 -#define poly_coeff_7 960 -#define poly_coeff_8 1024 -#define poly_coeff_9 1088 -#define poly_coeff_10 1152 -#define poly_coeff_11 1216 -#define poly_coeff_12 1280 -#define PiH 1344 -#define Pi2H 1408 +#define SgnBit 0 +#define OneHalf 64 +#define SmallNorm 128 +#define MOne 192 +#define Two 256 +#define sqrt_coeff_1 320 +#define sqrt_coeff_2 384 +#define sqrt_coeff_3 448 +#define sqrt_coeff_4 512 +#define poly_coeff_1 576 +#define poly_coeff_2 640 +#define poly_coeff_3 704 +#define poly_coeff_4 768 +#define poly_coeff_5 832 +#define poly_coeff_6 896 +#define poly_coeff_7 960 +#define poly_coeff_8 1024 +#define poly_coeff_9 1088 +#define poly_coeff_10 1152 +#define poly_coeff_11 1216 +#define poly_coeff_12 1280 +#define PiH 1344 +#define Pi2H 1408 #include - .text - .section .text.evex512,"ax",@progbits + .section .text.evex512, "ax", @progbits ENTRY(_ZGVeN8v_acos_skx) - pushq %rbp - cfi_def_cfa_offset(16) - movq %rsp, %rbp - cfi_def_cfa(6, 16) - cfi_offset(6, -16) - andq $-64, %rsp - subq $192, %rsp - vmovups __svml_dacos_data_internal(%rip), %zmm7 - vmovups OneHalf+__svml_dacos_data_internal(%rip), %zmm8 - -/* S ~ 2*sqrt(Y) */ - vmovups SmallNorm+__svml_dacos_data_internal(%rip), %zmm11 - vmovups Two+__svml_dacos_data_internal(%rip), %zmm14 - vmovups sqrt_coeff_1+__svml_dacos_data_internal(%rip), %zmm15 - vmovups sqrt_coeff_2+__svml_dacos_data_internal(%rip), %zmm2 - vmovups sqrt_coeff_3+__svml_dacos_data_internal(%rip), %zmm1 - vmovups MOne+__svml_dacos_data_internal(%rip), %zmm10 - vmovaps %zmm0, %zmm6 - -/* x = -|arg| */ - vorpd %zmm6, %zmm7, %zmm5 - vandpd %zmm6, %zmm7, %zmm4 - -/* Y = 0.5 + 0.5*(-x) */ - vfmadd231pd {rn-sae}, %zmm5, %zmm8, %zmm8 - -/* x^2 */ - vmulpd {rn-sae}, %zmm5, %zmm5, %zmm9 - vrsqrt14pd %zmm8, %zmm12 - vcmppd $17, {sae}, %zmm11, %zmm8, %k1 - vcmppd $17, {sae}, %zmm10, %zmm5, %k0 - vmovups poly_coeff_5+__svml_dacos_data_internal(%rip), %zmm10 - vmovups poly_coeff_7+__svml_dacos_data_internal(%rip), %zmm11 - vminpd {sae}, %zmm8, %zmm9, %zmm3 - vmovups poly_coeff_3+__svml_dacos_data_internal(%rip), %zmm9 - vxorpd %zmm12, %zmm12, %zmm12{%k1} - vaddpd {rn-sae}, %zmm8, %zmm8, %zmm0 - vcmppd $21, {sae}, %zmm8, %zmm3, %k4 - -/* X